CN103887235B - A kind of array base palte and manufacture method, display device - Google Patents
A kind of array base palte and manufacture method, display device Download PDFInfo
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- CN103887235B CN103887235B CN201410086570.7A CN201410086570A CN103887235B CN 103887235 B CN103887235 B CN 103887235B CN 201410086570 A CN201410086570 A CN 201410086570A CN 103887235 B CN103887235 B CN 103887235B
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000002161 passivation Methods 0.000 claims abstract description 180
- 229910052751 metal Inorganic materials 0.000 claims abstract description 95
- 239000002184 metal Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000003860 storage Methods 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 230000008021 deposition Effects 0.000 claims abstract description 23
- 239000012212 insulator Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 53
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 239000004411 aluminium Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 7
- 239000011733 molybdenum Substances 0.000 claims description 7
- 238000013007 heat curing Methods 0.000 claims description 4
- 239000012528 membrane Substances 0.000 claims description 4
- 238000003745 diagnosis Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 142
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of array base palte and manufacture method, display device, in order to reduce production cost, and then the metal of protection periphery via subsequent deposition, it is to avoid metal and the bad situation of resin stickiness.Manufacturing method of array base plate includes manufacturing on underlay substrate successively grid, gate insulator, semiconductor active layer, source-drain electrode, the first passivation layer, pixel electrode, the second passivation layer, storage electric capacity upper substrate and the 3rd passivation layer；On the 3rd passivation layer, etching is positioned at above drain electrode, run through the first via of first, second, and third passivation layer, be positioned at above pixel electrode, run through second and the 3rd passivation layer the second via, be positioned at storage electric capacity upper substrate above, run through the 3rd via of the 3rd passivation layer, be positioned at above perimeter leads district source electrode, run through the 4th via of first, second, and third passivation layer, be positioned at above perimeter leads district grid, run through the 5th via of gate insulator, first, second, and third passivation layer.
Description
Technical field
The present invention relates to display technology field, particularly relate to a kind of array base palte and manufacture method, display device.
Background technology
Current Medical flat detector, X ray through human body is converted into visible ray, convert optical signals to the signal of telecommunication, the inconvenience that avoiding takes pictures prints the pictures, successfully present object appearance in real time, Fig. 1 is the structure chart of the pixel region of the flat panel detector array base palte adopting 11 road mask plates making to obtain in prior art, wherein, this array base palte includes glass substrate 10, grid 11, gate insulator 12, semiconductor active layer 13, drain electrode 14, source electrode 15, first passivation layer 16, pixel electrode 17, second passivation layer 18, storage electric capacity upper substrate 19, 3rd passivation layer 110, it is positioned at the ground metal layer 111 on storage electric capacity upper substrate 19, resin passivation layer 112 and public electrode 113, wherein, pixel electrode 17, storage electric capacity upper substrate 19 and public electrode 113 are tin indium oxide (IndiumTinOxides, ITO) conductive film.Via 001 above drain electrode 14 has carried out repeatedly trepanning, needing making via, resin passivation layer 112 to need to make via after being coated with after depositing particularly as follows: the first passivation layer 16 needs to make via, the 3rd passivation layer 110 after needing making via, the second passivation layer 18 deposition after depositing, it is bad that such repeatedly punching easily causes pixel.
The structure chart that Fig. 2 (a) and Fig. 2 (b) is flat panel detector array base palte perimeter leads district of the prior art, via 21 and 22 in Fig. 2 (a) has carried out repeatedly trepanning equally, when deposition metallic aluminium 20 in position in the hole at via 21 and 22, via 21 place needs to etch away the metallic aluminium of deposition, the corrosion of ITO below metallic aluminium can be caused, the interior metallic aluminium deposited of via 22 and ITO poor adhesion below, during the extraneous integrated chip of follow-up welding, easily cause coming off of aluminum and ITO, time serious, the ITO that can cause the inside connected together loosens, and then with the phenomenon that the resin of top comes off together.Similarly, the via 23 and 24 in Fig. 2 (b) has been also carried out repeatedly trepanning, can cause the corrosion of ITO below metallic aluminium and the problem of metallic aluminium and ITO poor adhesion below equally.
In sum, the via of the top that drains in array base palte pixel region of the prior art has carried out repeatedly trepanning, and in actual production, trepanning can produce certain skew, and the residual of resin can cause pixel bad；Via place in array base palte perimeter leads district has been also carried out repeatedly trepanning, the electrode being used as lead-in wire in lead district adopts metal aluminium electrode, the ITO corrosion of lead-in wire electrode zone and metallic aluminium and ITO poor adhesion below can be caused, it is easy to cause the bad problem that comes off.
Summary of the invention
Embodiments provide a kind of array base palte and manufacture method, display device, in order to reduce production cost, and then the metal of protection periphery via subsequent deposition, it is to avoid metal and the bad situation of resin stickiness.
The manufacture method of a kind of array base palte that the embodiment of the present invention provides, described method includes:
Grid, gate insulator, semiconductor active layer, source-drain electrode, the first passivation layer, pixel electrode, the second passivation layer, storage electric capacity upper substrate and the 3rd passivation layer is manufactured successively on underlay substrate；
Described 3rd passivation layer etches the first via, second via, 3rd via, 4th via and the 5th via, wherein, described first via is positioned at described drain electrode top, run through described first passivation layer, second passivation layer and the 3rd passivation layer, described second via is positioned at above described pixel electrode, run through described second passivation layer and the 3rd passivation layer, described 3rd via is positioned at above described storage electric capacity upper substrate, run through described 3rd passivation layer, described 4th via is positioned at above perimeter leads district source electrode, run through described first passivation layer, second passivation layer and the 3rd passivation layer, described 5th via is positioned at above perimeter leads district grid, run through described gate insulator, first passivation layer, second passivation layer and the 3rd passivation layer；
Described 3rd passivation layer deposits metal level, described drain electrode and described pixel electrode are electrically connected by described first via and described second via by the metal level being deposited in hole, described storage electric capacity upper substrate is electrically connected with the ground lead in perimeter leads district by described 3rd via by the metal level being deposited in hole, in described 4th via, the metal level of deposition is for electrically connecting the source electrode in perimeter leads district with the wire in perimeter leads district, and the metal level that described five faults in diagnosis and treatment inner hole deposition amasss is for electrically connecting the grid in perimeter leads district with the wire in perimeter leads district.
The manufacture method of the array base palte provided by the embodiment of the present invention, owing to the manufacture method of this array base palte includes etching the first via on described 3rd passivation layer, second via, 3rd via, 4th via and the 5th via, wherein, described first via is positioned at described drain electrode top, run through described first passivation layer, second passivation layer and the 3rd passivation layer, described second via is positioned at above described pixel electrode, run through described second passivation layer and the 3rd passivation layer, described 3rd via is positioned at above described storage electric capacity upper substrate, run through described 3rd passivation layer, described 4th via is positioned at above perimeter leads district source electrode, run through described first passivation layer, second passivation layer and the 3rd passivation layer, described 5th via is positioned at above perimeter leads district grid, run through described gate insulator, first passivation layer, second passivation layer and the 3rd passivation layer, first via, second via, 3rd via, 4th via and the 5th via prepare in same one-time process, effectively avoid repeatedly the problem that trepanning causes, reduce production cost, and then avoid the because of metal source electrode of periphery via, when drain electrode etching and ITO etching, cause to the corrosion in grid upper aperture and in source electrode upper aperture.
On described 3rd passivation layer, the first via, the second via, the 3rd via, the 4th via and the 5th via is etched it is preferred that described, including:
Described 3rd passivation layer is coated with photoresist, adopts semipermeable membrane or gray-tone mask exposure, the photoresist of grid upper area in perimeter leads district is exposed entirely, the photoresist half-exposure of source electrode upper area；Photoresist half-exposure to the upper area that drains in pixel region, pixel electrode upper area and storage electric capacity upper substrate upper area；The photoresist in other region is not exposed, adopts dry etching to obtain the first via, the second via, the 3rd via, the 4th via and the 5th via；Or
Described 3rd passivation layer is coated with photoresist, to grid upper area, source electrode upper area in perimeter leads district；The photoresist of the upper area that drains in pixel region, pixel electrode upper area and storage electric capacity upper substrate upper area is exposed entirely, the photoresist in other region is not exposed, adopts dry etching to obtain the first via, the second via, the 3rd via, the 4th via and the 5th via.
So, the present invention etches the first via, the second via, the 3rd via, the 4th via and the 5th via by above-mentioned method on described 3rd passivation layer, simpler in actual production, easy.
It is preferred that described method also includes: make the 4th passivation layer on described metal level.
So, when described method also includes: make the 4th passivation layer on described metal level, simple in actual production, easy.
It is preferred that described 4th passivation layer is photosensitive resin or non-photo-sensing resin.
So, when the 4th passivation layer is photosensitive resin or non-photo-sensing resin, simpler in actual production, convenient.
It is preferred that described making the 4th passivation layer includes:
Coated with resins on described metal level, and described resin is carried out heat cure process, form the 4th passivation layer.
So, include when making the 4th passivation layer: coated with resins on described metal level, and described resin is carried out heat cure process, when forming four passivation layers, simpler in actual production, convenient.
It is preferred that described method also includes: etch the 6th via on described 4th passivation layer, described 6th via is positioned at described drain electrode top, runs through described 4th passivation layer.
So, when described method also includes: etch the 6th via on described 4th passivation layer, described 6th via is positioned at described drain electrode top, when running through described four passivation layer, simpler in actual production, convenient.
It is preferred that after described etching the 6th via, described method also includes: make public electrode on described 4th passivation layer.
So, when, after etching the 6th via, described method also includes: make public electrode on described 4th passivation layer, simpler in actual production, convenient.
The embodiment of the present invention additionally provides a kind of array base palte, and described substrate includes:
Underlay substrate, the grid being sequentially located on described underlay substrate, gate insulator, semiconductor active layer, source-drain electrode, the first passivation layer, pixel electrode, the second passivation layer, storage electric capacity upper substrate, the 3rd passivation layer, metal level, and the first via, the second via, the 3rd via, the 4th via and the 5th via；
Wherein, described first via is positioned at described drain electrode top, runs through described first passivation layer, the second passivation layer and the 3rd passivation layer；Described second via is positioned at above described pixel electrode, runs through described second passivation layer and the 3rd passivation layer；Described drain electrode and described pixel electrode are electrically connected by described first via and described second via by the metal level being deposited in hole；Described 3rd via is positioned at above described storage electric capacity upper substrate, runs through described 3rd passivation layer, and described storage electric capacity upper substrate is electrically connected with the ground lead in perimeter leads district by described 3rd via by the metal level being deposited in hole；Described 4th via is positioned at above perimeter leads district source electrode, runs through described first passivation layer, the second passivation layer and the 3rd passivation layer, and the source electrode in perimeter leads district is electrically connected with the wire in perimeter leads district by described 4th via by the metal level being deposited in hole；Described 5th via is positioned at above perimeter leads district grid, running through described gate insulator, the first passivation layer, the second passivation layer and the 3rd passivation layer, the grid in perimeter leads district is electrically connected with the wire in perimeter leads district by described 5th via by the metal level being deposited on inner hole deposition long-pending.
The array base palte provided by the embodiment of the present invention, owing to described substrate includes: underlay substrate, it is sequentially located at the grid on described underlay substrate, gate insulator, semiconductor active layer, source-drain electrode, first passivation layer, pixel electrode, second passivation layer, storage electric capacity upper substrate, 3rd passivation layer, metal level, and first via, second via, 3rd via, 4th via and the 5th via, this array base palte can effectively avoid the problem that repeatedly trepanning causes, reduce production cost, and then avoid the because of metal source electrode of periphery via, when drain electrode etching and ITO etching, cause to the corrosion in grid upper aperture and in source electrode upper aperture.
It is preferred that the complex metal layer that described metal level is metallic aluminium and metal molybdenum.
So, when the complex metal layer that metal level is metallic aluminium and metal molybdenum, it is possible to increase the adhesive attraction between the connected metal level of described metal level.
The embodiment of the present invention additionally provides a kind of display device, and described display device includes array base palte recited above.
The display device provided by the embodiment of the present invention, owing to this display device includes array base palte recited above, therefore the production cost of this display device is relatively low.
Accompanying drawing explanation
Fig. 1 is the dot structure schematic diagram of the Medical flat detector array substrate that prior art manufacture obtains；
The perimeter leads district grid of Fig. 2 (a) and Fig. 2 (b) Medical flat detector array substrate that respectively prior art manufacture obtains and the schematic diagram of source electrode upper area via；
The manufacture method flow chart of a kind of array base palte that Fig. 3 provides for the embodiment of the present invention；
A kind of array base palte that Fig. 4 (a) and Fig. 4 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after grid and perimeter leads district；
A kind of array base palte that Fig. 5 (a) and Fig. 5 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after source electrode, drain electrode and perimeter leads district；
A kind of array base palte that Fig. 6 (a) and Fig. 6 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after the first passivation layer and perimeter leads district；
A kind of array base palte that Fig. 7 (a) and Fig. 7 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after the second passivation layer and perimeter leads district；
A kind of array base palte that Fig. 8 (a) and Fig. 8 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after the via on the 3rd passivation layer and the 3rd passivation layer and perimeter leads district；
A kind of array base palte manufacture that Fig. 9 (a) and Fig. 9 (b) respectively embodiment of the present invention provide overlaps the structural representation in the pixel region after metal and perimeter leads district；
A kind of array base palte that Figure 10 (a) and Figure 10 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after resin passivation layer and via thereon and perimeter leads district；
A kind of array base palte that Figure 11 (a) and Figure 11 (b) respectively embodiment of the present invention provide manufactures the structural representation in the pixel region after public electrode and perimeter leads district.
Detailed description of the invention
Embodiments provide a kind of array base palte and manufacture method, display device, in order to reduce production cost, the metal of protection periphery via, it is to avoid metal and the bad effect of resin stickiness.
As it is shown on figure 3, the specific embodiment of the invention provides the manufacture method of a kind of array base palte, described method includes:
S301, successively manufacture grid, gate insulator, semiconductor active layer, source-drain electrode, the first passivation layer, pixel electrode, the second passivation layer, storage electric capacity upper substrate and the 3rd passivation layer on underlay substrate；
S302, described 3rd passivation layer etches the first via, second via, 3rd via, 4th via and the 5th via, wherein, described first via is positioned at described drain electrode top, run through described first passivation layer, second passivation layer and the 3rd passivation layer, described second via is positioned at above described pixel electrode, run through described second passivation layer and the 3rd passivation layer, described 3rd via is positioned at above described storage electric capacity upper substrate, run through described 3rd passivation layer, described 4th via is positioned at above perimeter leads district source electrode, run through described first passivation layer, second passivation layer and the 3rd passivation layer, described 5th via is positioned at above perimeter leads district grid, run through described gate insulator, first passivation layer, second passivation layer and the 3rd passivation layer；
S303, on described 3rd passivation layer deposit metal level, described drain electrode and described pixel electrode are electrically connected by described first via and described second via by the metal level being deposited in hole, described storage electric capacity upper substrate is electrically connected with the ground lead in perimeter leads district by described 3rd via by the metal level being deposited in hole, in described 4th via, the metal level of deposition is for electrically connecting the source electrode in perimeter leads district with the wire in perimeter leads district, and the metal level that described five faults in diagnosis and treatment inner hole deposition amasss is for electrically connecting the grid in perimeter leads district with the wire in perimeter leads district.
Below in conjunction with the manufacture method of the array base palte in the accompanying drawing detailed description specific embodiment of the invention, the array base palte that specific embodiment of the invention manufacture obtains is for Medical flat detector.In the specific embodiment of the invention during manufacturing array substrate, the pixel region of array base palte and perimeter leads district manufacture simultaneously and obtain.
As shown in Fig. 4 (a) and Fig. 4 (b), first on glass substrate substrate 30, deposit metal molybdenum Mo, coating photoresist in the metal molybdenum of deposition, by photoresist being exposed, developing, and the metal molybdenum that post-develop photoresist is not covered with carries out wet etching, remove remaining photoresist after etching, obtain the grid 31 of array base palte pixel region as shown in Figure 4 (a) and the grid 31 in array base palte perimeter leads district as shown in Figure 4 (b).Grid in the specific embodiment of the invention is not limited to metal Mo, it is also possible to for other metal, the composition metal that single-layer metal or the multiple layer metal such as metallic aluminium Al, metal nickel, crome metal Cr etc. forms.
As shown in Fig. 5 (a) and Fig. 5 (b), manufacturing, the grid 31 obtained is sequentially depositing gate insulator, semiconductor active layer and metal level, coating photoresist on the metal level that deposition obtains, adopt semipermeable membrane mask plate or GTG exposure, development, first carry out wet etching after development and obtain source electrode 34 and the gate insulator 32 in array base palte perimeter leads district, as shown in Fig. 5 (b).Then ashing photoresist again, and carry out dry etching, obtain the source electrode 34 of array base palte pixel region, drain electrode 35, semiconductor active layer 33 and gate insulator 32, as shown in Fig. 5 (a).Wherein, semiconductor active layer 33 and source electrode 34, drain electrode 35 can also be formed by two step masks.
As shown in Fig. 6 (a) and Fig. 6 (b), on the substrate of Fig. 5 (a) and Fig. 5 (b), successive sedimentation the first passivation layer and pixel electrode, pixel electrode in the specific embodiment of the invention is ITO, coating photoresist on the pixel electrode that deposition obtains, by photoresist being exposed, developing, and the pixel electrode that post-develop photoresist is not covered with carries out wet etching, remaining photoresist is removed after etching, obtain pixel electrode 37 and first passivation layer 36 of array base palte pixel region, as shown in Figure 6 (a).Also obtaining first passivation layer 36 in array base palte perimeter leads district, as shown in Figure 6 (b), at this moment, the first passivation layer 36 and gate insulator 32 well protect the source electrode 34 in perimeter leads district simultaneously.
As shown in Fig. 7 (a) and Fig. 7 (b), on the substrate of Fig. 6 (a) and Fig. 6 (b), successive sedimentation the second passivation layer and storage electrode, storage electrode in the specific embodiment of the invention is ITO, coating photoresist on the storage electrode that deposition obtains, by photoresist being exposed, developing, and the storage electrode that post-develop photoresist is not covered with carries out wet etching, remaining photoresist is removed after etching, obtain storage electric capacity upper substrate 39 and second passivation layer 38 of array base palte pixel region, as shown in Figure 7 (a).Also obtaining second passivation layer 38 in array base palte perimeter leads district, as shown in Figure 7 (b) shows, now, the source electrode 34 in perimeter leads district is still protected, will not be corroded simultaneously.
As shown in Fig. 8 (a) and Fig. 8 (b), on the substrate of Fig. 7 (a) and Fig. 7 (b), deposit the 3rd passivation layer, the 3rd passivation layer that deposition obtains adopt patterning processes obtain the via 01 above the drain electrode 35 of array base palte pixel region, the via 02 above pixel electrode 37, the via 03 above storage electric capacity upper substrate 39 and the 3rd passivation layer 310, as shown in Figure 8 (a).Also obtain the via 04 above array base palte perimeter leads district source electrode 34, via 05 above grid 31 and the 3rd passivation layer 310, as shown in Figure 8 (b) shows simultaneously.Wherein, the specific embodiment of the invention obtains via 01, via 02, via 03, via 04 and via 05 by patterning processes and can adopt two kinds of methods.
Method one:
Being coated with photoresist on the 3rd passivation layer, adopt semipermeable membrane or gray-tone mask exposure, in array substrate perimeter leads district, the photoresist of grid 31 upper area exposes entirely, the photoresist half-exposure of source electrode 34 upper area；Array substrate pixel region drains 35 upper areas, pixel electrode 37 upper area, storage electric capacity upper substrate 39 upper area photoresist half-exposure；The photoresist in other region is not exposed, adopts dry etching to obtain via 01, via 02, via 03, via 04 and via 05.Owing in array base palte perimeter leads district, the thin film number of plies of grid upper area is many, thickness is big, and the thin film number of plies in other place is few, thickness is little, therefore first etch in a part of array base palte perimeter leads district after the thickness of the thin film of grid upper area, again the photoresist ashing at the via place in half-exposure region is fallen, then etches together, it is ensured that all of via etch and do not damage metal below.
Method two:
Being coated with photoresist on the 3rd passivation layer, the photoresist of grid 31 upper area in array substrate perimeter leads district, the photoresist of source electrode 34 upper area exposes entirely；And the photoresist of the photoresist of the photoresist of 35 upper areas that drains in array substrate pixel region, pixel electrode 37 upper area, storage electric capacity upper substrate 39 upper area exposes entirely, photoresist in other region is not exposed, adopts dry etching to obtain via 01, via 02, via 03, via 04 and via 05.
As shown in Fig. 9 (a) and Fig. 9 (b), on the substrate of Fig. 8 (a) and Fig. 8 (b), deposition metal level, coating photoresist on the metal level of deposition, by photoresist being exposed, developing, and the metal level that post-develop photoresist is not covered with carries out wet etching, removes remaining photoresist after etching, obtain the metal level 311 connecting drain electrode 35 and pixel electrode 37 of array base palte pixel region and be used as the metal level 311 of storage electric capacity upper substrate 39 lead-in wire, as shown in Fig. 9 (a).Also obtain the metal electrode 311 being used as to be used as gate line lead-in wire above the metal electrode 311 of data cable lead wire and grid above the source electrode 34 in array base palte perimeter leads district, as shown in Figure 9 (b) simultaneously.Metal level in the specific embodiment of the invention is the complex metal layer of metallic aluminium Al and metal molybdenum Mo, owing to the metal of the grid in the specific embodiment of the invention, source electrode and drain electrode is Mo, when the bottom of metal level is metal Mo, metal level 311 is better with the adhesiveness of grid, source electrode and drain electrode, in order to better make lead-in wire, the metal of metal level the top is metal Al.Metal level is not done concrete restriction by the specific embodiment of the invention, the composition metal that metal level can also can form for multiple layer metal for single-layer metal.
As shown in Figure 10 (a) and Figure 10 (b), coated with resins on the substrate of Fig. 9 (a) and Fig. 9 (b), the resin of this coating is carried out heat cure process formation passivation layer, this passivation layer is carried out the coating of photoresist, exposed and developed, carry out dry etching afterwards and remove photoresist, forming the passivation layer 312 of array base palte pixel region and via 06, as shown in Figure 10 (a) shows, in etching process, the passivation layer being coated in array base palte perimeter leads district is all etched away, as shown in Figure 10 (b).In the specific embodiment of the invention, the resin of coating can use sense photopolymer resin, it is possible to use non-photo-sensing resin.The dielectric constant of resin passivation layer is little, and can be coated with larger thickness, increases the distance of vertical direction, it is possible to play the effect reducing electric capacity.
As shown in Figure 11 (a) and Figure 11 (b), deposition ito thin film on the substrate of Figure 10 (a) and Figure 10 (b), coating photoresist on the ito thin film of deposition, by photoresist is exposed, development, and the ITO that post-develop photoresist is not covered with carries out wet etching, wet etching selects the etching liquid without nitric acid, optionally etch away the ITO come out, remaining photoresist is removed after etching, obtain the public electrode 313 of array base palte pixel region as shown in Figure 11 (a) shows, in etching process, the ITO being deposited on array base palte perimeter leads district is all etched away, as shown in Figure 11 (b), owing to selecting the etching liquid without nitric acid that ITO is optionally etched, metal will not be caused corrosiveness by this etching liquid, bad without generation adhesiveness etc..
As shown in Fig. 9 (a) and Fig. 9 (b), the specific embodiment of the invention provides a kind of array base palte, and described substrate includes:
Underlay substrate 30, the grid 31 being sequentially located on described underlay substrate 30, gate insulator 32, semiconductor active layer 33, source electrode 34, drain electrode the 35, first passivation layer 36, pixel electrode the 37, second passivation layer 38, storage electric capacity upper substrate the 39, the 3rd passivation layer 310, metal level 311, and the first via the 01, second via the 02, the 3rd via the 03, the 4th via 04 and the 5th via 05；
Wherein, described first via 01 is positioned at above described drain electrode 35, runs through described first passivation layer the 36, second passivation layer 38 and the 3rd passivation layer 310；Described second via 02 is positioned at above described pixel electrode 37, runs through described second passivation layer 38 and the 3rd passivation layer 310；Described drain electrode 35 and described pixel electrode 37 are electrically connected by described first via 01 and described second via 02 by the metal level 311 being deposited in hole；Described 3rd via 03 is positioned at above described storage electric capacity upper substrate 39, runs through described 3rd passivation layer 310, and described storage electric capacity upper substrate 39 is electrically connected with the ground lead in perimeter leads district by described 3rd via 03 by the metal level 311 being deposited in hole；Described 4th via 04 is positioned at above described source electrode 34, runs through described first passivation layer the 36, second passivation layer 38 and the 3rd passivation layer 310, and described source electrode 34 is electrically connected with the wire in perimeter leads district by described 4th via 04 by the metal level 311 being deposited in hole；Described 5th via 05 is positioned at above described grid 31, running through described gate insulator the 32, first passivation layer the 36, second passivation layer 38 and the 3rd passivation layer 310, described grid 31 is electrically connected with the wire in perimeter leads district by described 5th via 05 by the metal level 311 being deposited on inner hole deposition long-pending.
Unless otherwise defined, technical term used herein or scientific terminology should be and have the ordinary meaning that the personage of general technical ability understands in art of the present invention." first ", " second " that use in present patent application description and claims and similar word are not offered as any order, quantity or importance, and are used only to distinguish different ingredients.
The specific embodiment of the invention additionally provides a kind of display device, this display device includes array base palte recited above, specifically, display device in the present invention is liquid crystal indicator, this liquid crystal indicator can be fringing field rotation in surface (FringeFieldSwitching, FFS) pattern, it is also possible to change (AdvancedSuperDimensionSwitch for senior super Wei Chang, ADS) pattern, it is not made concrete restriction by the specific embodiment of the invention.
Obviously, the present invention can be carried out various change and modification without deviating from the spirit and scope of the present invention by those skilled in the art.So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. the manufacture method of an array base palte, it is characterised in that described method includes:
Grid, gate insulator, semiconductor active layer, source-drain electrode, the first passivation layer, pixel electrode, the second passivation layer, storage electric capacity upper substrate and the 3rd passivation layer is manufactured successively on underlay substrate；
Etching the first via, the second via, the 3rd via, the 4th via and the 5th via on described 3rd passivation layer, wherein, described first via is positioned at drain electrode top, runs through described first passivation layer, the second passivation layer and the 3rd passivation layer；Described second via is positioned at above described pixel electrode, runs through described second passivation layer and the 3rd passivation layer；Described 3rd via is positioned at above described storage electric capacity upper substrate, runs through described 3rd passivation layer；Described 4th via is positioned at above perimeter leads district source electrode, runs through described first passivation layer, the second passivation layer and the 3rd passivation layer；Described 5th via is positioned at above perimeter leads district grid, runs through described gate insulator, the first passivation layer, the second passivation layer and the 3rd passivation layer；
Described 3rd passivation layer deposits metal level, described drain electrode and described pixel electrode are electrically connected by described first via and described second via by the metal level being deposited in hole, described storage electric capacity upper substrate is electrically connected with the ground lead in perimeter leads district by described 3rd via by the metal level being deposited in hole, in described 4th via, the metal level of deposition is for electrically connecting the source electrode in perimeter leads district with the wire in perimeter leads district, and the metal level that described five faults in diagnosis and treatment inner hole deposition amasss is for electrically connecting the grid in perimeter leads district with the wire in perimeter leads district.
2. method according to claim 1, it is characterised in that described etch the first via, the second via, the 3rd via, the 4th via and the 5th via on described 3rd passivation layer, including:
Described 3rd passivation layer is coated with photoresist, adopts semipermeable membrane or gray-tone mask exposure, the photoresist of grid upper area in perimeter leads district is exposed entirely, the photoresist half-exposure of source electrode upper area；Photoresist half-exposure to the upper area that drains in pixel region, pixel electrode upper area and storage electric capacity upper substrate upper area；The photoresist in other region is not exposed, adopts dry etching to obtain the first via, the second via, the 3rd via, the 4th via and the 5th via；Or
Described 3rd passivation layer is coated with photoresist, to grid upper area, source electrode upper area in perimeter leads district；The photoresist of the upper area that drains in pixel region, pixel electrode upper area and storage electric capacity upper substrate upper area is exposed entirely, the photoresist in other region is not exposed, adopts dry etching to obtain the first via, the second via, the 3rd via, the 4th via and the 5th via.
3. method according to claim 1, it is characterised in that described method also includes: make the 4th passivation layer on described metal level.
4. method according to claim 3, it is characterised in that described 4th passivation layer is photosensitive resin or non-photo-sensing resin.
5. the method according to the arbitrary claim of claim 3-4, it is characterised in that described making the 4th passivation layer includes:
Coated with resins on described metal level, and described resin is carried out heat cure process, form the 4th passivation layer.
6. method according to claim 5, it is characterised in that described method also includes: etch the 6th via on described 4th passivation layer, described 6th via is positioned at described drain electrode top, runs through described 4th passivation layer.
7. method according to claim 6, it is characterised in that after described etching the 6th via, described method also includes: make public electrode on described 4th passivation layer.
8. an array base palte, it is characterised in that described substrate includes:
Underlay substrate, the grid being sequentially located on described underlay substrate, gate insulator, semiconductor active layer, source-drain electrode, the first passivation layer, pixel electrode, the second passivation layer, storage electric capacity upper substrate, the 3rd passivation layer, metal level, and the first via, the second via, the 3rd via, the 4th via and the 5th via；
Wherein, described first via is positioned at drain electrode top, runs through described first passivation layer, the second passivation layer and the 3rd passivation layer；Described second via is positioned at above described pixel electrode, runs through described second passivation layer and the 3rd passivation layer；Described drain electrode and described pixel electrode are electrically connected by described first via and described second via by the metal level being deposited in hole；Described 3rd via is positioned at above described storage electric capacity upper substrate, runs through described 3rd passivation layer, and described storage electric capacity upper substrate is electrically connected with the ground lead in perimeter leads district by described 3rd via by the metal level being deposited in hole；Described 4th via is positioned at above perimeter leads district source electrode, runs through described first passivation layer, the second passivation layer and the 3rd passivation layer, and the source electrode in perimeter leads district is electrically connected with the wire in perimeter leads district by described 4th via by the metal level being deposited in hole；Described 5th via is positioned at above perimeter leads district grid, running through described gate insulator, the first passivation layer, the second passivation layer and the 3rd passivation layer, the grid in perimeter leads district is electrically connected with the wire in perimeter leads district by described 5th via by the metal level being deposited on inner hole deposition long-pending.
9. array base palte according to claim 8, it is characterised in that described metal level is the complex metal layer of metallic aluminium and metal molybdenum.
10. a display device, it is characterised in that described device includes the array base palte described in the arbitrary claim of claim 8-9.
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| CN103579219A (en) * | 2012-07-27 | 2014-02-12 | 北京京东方光电科技有限公司 | Planar array substrate, sensor and manufacturing method of planar array substrate |
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| CN103579219A (en) * | 2012-07-27 | 2014-02-12 | 北京京东方光电科技有限公司 | Planar array substrate, sensor and manufacturing method of planar array substrate |
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