CN103887196B - The method using wicket graphics test structure detection polysilicon bottom bridging defect - Google Patents
The method using wicket graphics test structure detection polysilicon bottom bridging defect Download PDFInfo
- Publication number
- CN103887196B CN103887196B CN201410060130.4A CN201410060130A CN103887196B CN 103887196 B CN103887196 B CN 103887196B CN 201410060130 A CN201410060130 A CN 201410060130A CN 103887196 B CN103887196 B CN 103887196B
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- wicket
- test structure
- graphics test
- graphics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention discloses the method using wicket graphics test structure detection polysilicon bottom bridging defect, relate to integrated circuit fabrication process field.The method is: set up wicket graphics test structure；Described test structure is positioned over the monitoring product test position of Electron-beam measuring instrument, at the surface deposited masking layer of described wicket graphics test structure, carries out flow according to FEOL；Use etching technics that described wicket graphics test structure is performed etching；Use described Electron-beam measuring instrument that the described wicket graphics test structure after etching is detected, judge whether the polysilicon of described wicket graphics test structure exists bridging, if then existing defects, if the most described wicket graphics test structure not existing defects.Use the method can find in time in line defect, provide data refer for development Yield lmproved, shorten the R&D cycle；There is provided monitoring means for product, shorten impact interval, provide safeguard for product yield.
Description
Technical field
The present invention relates to integrated circuit fabrication process field, particularly relate to etching polysilicon defect
Detection.
Background technology
Along with development and the critical size of integrated circuit technology are scaled, it is possible to online and
Time detect that the defect of dimension limit is most important to Yield lmproved, use for this semiconductor manufacturing
Multiple detection method, such as: details in a play not acted out on stage, but told through dialogues scanning, bright field scanning and electron beam (E-beam) scanning
Deng.But not all defect all can be detected, for instance in the polysilicon gate of dimension limit
Pole etching residue defect A is just not easy to be detected, as illustrated in figs. ia and ib.
Its reason is, the size of such defect and thickness are beyond the ability model of optical detection
Enclosing, and do not have the difference of voltage contrast, it is the most weak with the secondary electron signal difference of background,
It is difficult to be detected by Electron-beam measuring instrument.Currently for this kind of defect, it usually needs tie in technique
Testing electrical property after bundle could react, but this considerably increases the difficulty of on-line analysis.As
If Fig. 1 a is the scattergram that the testing electrical property after technique terminates lost efficacy, Fig. 1 b is typical etching
Defect.
Chinese patent (CN103346076A) discloses the method improving grid oxygen active area defect,
Should be at Grown gate oxide；Depositing polysilicon layer on gate oxide；Carry out N-type
Polysilicon gate pre-doping；Formed on the polysilicon layer and include the folded of PEOX layer and O3TEOS layer
The polysilicon gate mask layer of layer；Polysilicon gate mask layer is formed anti-reflecting layer；In antireflection
Form photoresist on Ceng, and utilize photoresist etches polycrystalline silicon layer to form polysilicon gate.
This patent has supplied a kind of to prevent active area in the manufacturing process of polysilicon grating structure
Produce the method improving grid oxygen active area defect of defect.But solution is not in dimension limit
The etching polysilicon gate residual defects problem that is not easy to be detected.
Chinese patent (CN102420116B) discloses the method eliminating recess defect of gate electrode,
Wherein, substrate sequentially generates from bottom to top the first oxide layer, polysilicon layer, the second oxidation
Layer, silicon nitride layer, amorphous carbon layer；Etch nitride silicon layer and amorphous carbon layer are formed by nitrogenizing
The mask that silicon and amorphous carbon are constituted, using mask as hard mask to polysilicon layer, the second oxidation
Layer performs etching, and forms grid and is positioned at part the second oxide layer on grid；Afterwards at grid
The both sides growth sidewall oxide of pole；The first oxide layer the only reservation of removing substrate surface are positioned at
Gate oxide layers below grid；Silicon growth layer layer in substrate；Remove silicon nitride layer.
This patent solves and there is concave defects in prior art in semiconductor device and cause device
The problem of hydraulic performance decline, increases protective layer by the substrate under polysilicon layer and polysilicon real
Now avoid recess defect of gate electrode.But do not solve to be in the etching polysilicon gate of dimension limit
Residual defects is not easy the problem being detected.
Summary of the invention
The present invention solves and be currently in the etching polysilicon gate residual defects of dimension limit not
The problem being easily detected, thus employing wicket graphics test structure detection polycrystalline is provided
The technical scheme of the method for bridging defect bottom silicon.
Invent described employing wicket graphics test structure detection polysilicon bottom bridging defect
Method, comprises the steps:
Step 1. sets up wicket graphics test structure；
Described test structure is positioned over the monitoring product test position of Electron-beam measuring instrument by step 2.
Put, at the surface deposited masking layer of described wicket graphics test structure, enter according to FEOL
Row flow；
Step 3. uses etching technics to perform etching described wicket graphics test structure；
Step 4. uses described Electron-beam measuring instrument to the described wicket graphics test after etching
Structure detects, it is judged that whether the polysilicon of described wicket graphics test structure exists bridge
Even, if then existing defects, if the most described wicket graphics test structure not existing defects.
Preferably, the wire spacing of wicket graphics test structure described in step 1 and monitoring product
The wire spacing of polysilicon gate identical, the active area knot of described wicket graphics test structure
Structure is identical with the active area structure of the polysilicon of described monitoring product.
Preferably, described wicket graphics test structure includes: active without gate oxide of surface
There is the polycrystalline that the active area of gate oxide, the polysilicon of many ground connection and Duo Gen are unsettled in district, surface
Silicon.
Preferably, the polysilicon of many described ground connection is arranged at described surface having without gate oxide
Source region and described surface have on the active area of gate oxide, the one of the polysilicon of every described ground connection
End is both secured to the polysilicon block of ground connection surely, arranges in the polysilicon of every two described quasi-ground connection
Having a described unsettled polysilicon, the polysilicon block of described quasi-ground connection is arranged at surface grid oxygen
Changing on the active area of layer, described unsettled polysilicon is the most parallel with the polysilicon of described ground connection
Arrangement.
Preferably, test position described in step 2 is the position of Cutting Road.
Preferably, mask layer described in step 2 is deposited on active without gate oxide of described surface
There are the active area of gate oxide, the polysilicon of described ground connection and described unsettled in district, described surface
Polysilicon surface.
Beneficial effects of the present invention:
The present invention, by setting up wicket graphics test structure, uses Electron-beam measuring instrument to this knot
Structure and polysilicon gate to be detected detect, owing to this type of defect is sensitive to special construction, and electricity
Son bundle detector is the highest to the sensitivity of material surface structure, in polysilicon gate the most to be detected
Polysilicon structure difference, connect wicket graphics test structure polysilicon in positive potential
Under the conditions of, it is more difficult to reach surface potential balance, thus can produce under the condition of scanning with often
, there is bridging in the image difference of rule polysilicon.The method is used to find in line defect in time,
There is provided data refer for development Yield lmproved, shorten the R&D cycle；Monitoring is provided for product
Means, shorten impact interval, provide safeguard for product yield.
Accompanying drawing explanation
Fig. 1 a is the scattergram that testing electrical property lost efficacy；
Fig. 1 b is the typical polysilicon bottom bridging defect map causing electrical property failure；
Fig. 2 is employing wicket graphics test structure detection polysilicon bottom bridge of the present invention
The even method flow diagram of defect；
Fig. 3 is wicket graphics test structural representation；
Fig. 4 is that polysilicon bottom bridging causes unsettled polysilicon in wicket test structure to become
Bright schematic diagram；
In accompanying drawing: the most unsettled polysilicon；2. the polysilicon of ground connection；3. there is gate oxidation on surface
The active area of layer;4. surface is without the active area of gate oxide;The polysilicon block of the most quasi-ground connection;6.
Bridging；A. etching residue defect.
Detailed description of the invention
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as this
The restriction of invention.
As in figure 2 it is shown, the present invention provides at the bottom of employing wicket graphics test structure detection polysilicon
The method of portion's bridging 6 defect, comprises the steps:
Set up as a example by wicket graphics test structure by 55 nm logic products:
Step 1. is set up little according to the sensitivity characteristic of polysilicon gate Facing material structure to be detected
Graph window test structure (as shown in Figure 3)；
Wicket graphics test structure is positioned over the monitoring product of Electron-beam measuring instrument by step 2.
Test position, at the surface deposited masking layer of wicket graphics test structure, according to FEOL
Carry out flow；
Step 3. uses etching technics to perform etching wicket graphics test structure；
Step 4. uses Electron-beam measuring instrument to carry out the wicket graphics test structure after etching
Detection, it is judged that whether the polysilicon of wicket graphics test structure exists bridging 6, if then appointing
A polysilicon of anticipating will be connected with neighbouring polysilicon, owing to the Grounding of polysilicon is alternately
, so necessarily having a unsettled polysilicon of script 1 to become ground state, thus change
, as shown in Figure 4, then there is bridging 6 in polysilicon imaging results under electron beam flaw scanner
Defect, if otherwise there is not bridging 6 defect in wicket graphics test structure.
The Electron-beam measuring instrument parameter regulation used in the present embodiment it is critical only that so that active area
And having obvious bright voltage contrast between polysilicon, one of which implementation method is as follows: land electricity
Pressure energy: 1000eV, electric current: 10nA, Pixel Dimensions: 60nm.
The principle of the present invention is, utilizes the characteristic that this type of defect is sensitive to special construction, Yi Ji electricity
Son bundle detector characteristic structure sensitive to Facing material, sets up wicket graphics test structure,
Checked by Electron-beam measuring instrument.This type of defect is sensitive to special construction, i.e. this type of defect
It is more prone at certain ad-hoc location, owing to this position is that narrow active area is formed with polysilicon
The junction of groove, and polysilicon trench is minimum in this position, and this kind of structure is due to active
Difference of height between district and sealing coat relatively other positions are bigger, thus cause follow-up anti-reflecting layer
Thickness bigger, be finally more prone to the defect of etching.The method can be examined timely and effectively
Survey the defect problem of online product, reduce product impact.
In a preferred embodiment, the wire spacing of step 1 wicket graphics test structure and prison
The wire spacing of the polysilicon gate of control product is identical, the active area of wicket graphics test structure
Structure is identical with the active area structure of monitoring product.
In a preferred embodiment, before polycrystalline silicon growth, by the active area of bulk in Fig. 3
Gate oxide removes (forming the polysilicon block 5 of quasi-ground connection), for follow-up by polysilicon ground connection.
Wicket graphics test structure includes: there is grid oxygen on surface without active area 4, the surface of gate oxide
Change the unsettled polysilicon 1 of polysilicon 2 and Duo Gen of the active area 3 of layer, many ground connection, ground connection
Polysilicon 2 be special construction.
In a preferred embodiment, the polysilicon 2 of many ground connection is arranged at surface without gate oxide
Active area 4 and surface have on the active area 3 of gate oxide, the polysilicon 2 of every ground connection
One end is both secured to the polysilicon block 5 of ground connection surely, sets in the polysilicon 2 of every two quasi-ground connection
Being equipped with a unsettled polysilicon 1, the polysilicon of quasi-ground connection 2 pieces is arranged at surface gate oxidation
On the active area 3 of layer, unsettled polysilicon 1 is the most arranged in parallel with the polysilicon 2 of ground connection.
In a preferred embodiment, step 2 test position is the free area not affecting normal function
Position such as Cutting Road.
In a preferred embodiment, step 2 mask layer is deposited on active without gate oxide of surface
There are the active area 3 of gate oxide, the polysilicon 2 of ground connection and unsettled polysilicon in district 4, surface
1 surface.
The foregoing is only preferred embodiment of the present invention, not thereby limit the enforcement of the present invention
Mode and protection domain, to those skilled in the art, it should can appreciate that all utilizations
Equivalent done by description of the invention and diagramatic content and obviously change gained
The scheme arrived, all should be included in protection scope of the present invention.
Claims (4)
1. the method using wicket graphics test structure detection polysilicon bottom bridging defect, its
It is characterised by, comprises the steps:
Step 1. sets up wicket graphics test structure；
Described test structure is positioned over the monitoring product test position of Electron-beam measuring instrument by step 2.
Put, at the surface deposited masking layer of described wicket graphics test structure, enter according to FEOL
Row flow；
Step 3. uses etching technics to perform etching described wicket graphics test structure；
Step 4. uses described Electron-beam measuring instrument to the described wicket graphics test after etching
Structure detects, it is judged that whether the polysilicon of described wicket graphics test structure exists bridge
Even, if then existing defects, if the most described wicket graphics test structure not existing defects；
Described wicket graphics test structure includes: surface is without the active area of gate oxide, surface
There is the polysilicon that the active area of gate oxide, the polysilicon of many ground connection and Duo Gen are unsettled；Many
The polysilicon of described ground connection is arranged at described surface without the active area of gate oxide and described surface
Having on the active area of gate oxide, one end of the polysilicon of every described ground connection is both secured to surely
The polysilicon block of ground connection, the polysilicon of every two described quasi-ground connection is provided with one described unsettled
Polysilicon, the polysilicon block of described quasi-ground connection is arranged at surface the active area of gate oxide
On, described unsettled polysilicon is the most arranged in parallel with the polysilicon of described ground connection.
2. use wicket graphics test structure detection polysilicon bottom bridge as claimed in claim 1
The even method of defect, it is characterised in that described in step 1 between the line of wicket graphics test structure
Distance is identical with the wire spacing of the polysilicon gate of monitoring product, described wicket graphics test
The active area structure of structure is identical with the active area structure of described monitoring product.
3. use wicket graphics test structure detection polysilicon bottom as claimed in claim 1
The method of bridging defect, it is characterised in that test position described in step 2 is the position of Cutting Road.
4. use wicket graphics test structure detection polysilicon bottom as claimed in claim 1
The method of bridging defect, it is characterised in that mask layer described in step 2 be deposited on described surface without
The active area of gate oxide, described surface have the active area of gate oxide, the polycrystalline of described ground connection
Silicon and described unsettled polysilicon surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410060130.4A CN103887196B (en) | 2014-02-21 | 2014-02-21 | The method using wicket graphics test structure detection polysilicon bottom bridging defect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410060130.4A CN103887196B (en) | 2014-02-21 | 2014-02-21 | The method using wicket graphics test structure detection polysilicon bottom bridging defect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103887196A CN103887196A (en) | 2014-06-25 |
| CN103887196B true CN103887196B (en) | 2017-01-04 |
Family
ID=50956031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410060130.4A Active CN103887196B (en) | 2014-02-21 | 2014-02-21 | The method using wicket graphics test structure detection polysilicon bottom bridging defect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103887196B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010556A (en) * | 2017-11-23 | 2018-05-08 | 长江存储科技有限责任公司 | A kind of method for the small defect failure address for being used to be accurately positioned large-size device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072191A (en) * | 1997-12-16 | 2000-06-06 | Advanced Micro Devices, Inc. | Interlevel dielectric thickness monitor for complex semiconductor chips |
| US6858450B1 (en) * | 2002-11-05 | 2005-02-22 | Advanced Micro Devices, Inc. | Method of alternating grounded/floating poly lines to monitor shorts |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100741858B1 (en) * | 2006-05-18 | 2007-07-24 | 삼성전자주식회사 | Monitoring pattern for detecting a defect in a seiconductor device and method for detecting a defect |
-
2014
- 2014-02-21 CN CN201410060130.4A patent/CN103887196B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072191A (en) * | 1997-12-16 | 2000-06-06 | Advanced Micro Devices, Inc. | Interlevel dielectric thickness monitor for complex semiconductor chips |
| US6858450B1 (en) * | 2002-11-05 | 2005-02-22 | Advanced Micro Devices, Inc. | Method of alternating grounded/floating poly lines to monitor shorts |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103887196A (en) | 2014-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102944196B (en) | A kind of method detecting circularity of circular contact hole of semiconductor | |
| CN103871922A (en) | Method for detecting polycrystalline silicon grid etching defect by adopting voltage contrast test structure | |
| Donovan et al. | Early detection of electrical defects in deep trench capacitors using voltage contrast inspection | |
| TWI526697B (en) | Structure for inspecting defects in word line array fabricated by sadp process and method thereof | |
| CN103163442B (en) | Wafer test method | |
| CN110783214B (en) | Wafer level test method and test structure thereof | |
| CN102832152B (en) | A kind of method of on-line checkingi contact hole | |
| CN104425302A (en) | Defect detection method and device of semiconductor device | |
| CN104143519A (en) | Product through hole etching defect detection method | |
| CN104733343A (en) | Gate-oxide layer defect detecting method and device electric leakage detection method | |
| CN103943527B (en) | The method using Test Constructure of detection etching polysilicon gate defect | |
| JP5144747B2 (en) | SOLAR CELL MANUFACTURING METHOD, SOLAR CELL MANUFACTURING DEVICE, AND SOLAR CELL | |
| CN206312895U (en) | A kind of receivable test structure of wafer | |
| JP2008166691A (en) | Teg pattern, testing method of semiconductor element using the pattern | |
| CN103887196B (en) | The method using wicket graphics test structure detection polysilicon bottom bridging defect | |
| CN103904000B (en) | The method using electric capacity contrast test structure detection polysilicon bottom bridging defect | |
| CN103887283A (en) | Polycrystalline silicon residue monitoring structure | |
| KR20180033367A (en) | Method for measuring pattern and method for manufacturing semiconductor device including the same | |
| CN103887195B (en) | Use the method that ion punctures the detection not enough defect of polysilicon bottom etching | |
| CN103943608B (en) | A kind of test structure detecting residual polycrystalline silicon | |
| CN104217973B (en) | The method of detection polysilicon gate oxide layer disappearance | |
| CN204155929U (en) | The test structure of plasma induced damage | |
| CN103824802B (en) | The forming method of semiconductor structure | |
| Li et al. | In-line monitoring of overlay and process window using design-assisted voltage contrast inspection for 14nm FINFET technology | |
| CN104701209A (en) | Gate-oxide layer defect detection method and device failure positioning method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |