CN103855104A - 对湿气密封的半导体模块和用于其制造的方法 - Google Patents
对湿气密封的半导体模块和用于其制造的方法 Download PDFInfo
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- CN103855104A CN103855104A CN201310624507.XA CN201310624507A CN103855104A CN 103855104 A CN103855104 A CN 103855104A CN 201310624507 A CN201310624507 A CN 201310624507A CN 103855104 A CN103855104 A CN 103855104A
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Abstract
对湿气密封的半导体模块和用于其制造的方法。半导体模块包括:具有两个外壁区段的壳体,外壁区段布置在壳体的相对侧上;盖,其从外壁区段之一延伸向外壁区段的另一个;以及布置在外壁区段之间并与其间隔开的、限定第一井筒的边界的第一井筒壁。此外半导体模块具有带上侧的电路载体;以及半导体芯片,其布置在壳体中和电路载体的上侧上。导电的第一连接端元件延伸通过第一井筒并且从壳体伸出。第一浇注料布置在电路载体和盖之间以及部分地在第一连接端元件和第一井筒壁之间,第一浇注料与第一连接端元件共同作用地将第一井筒密封。第一井筒壁在其朝向电路载体的侧上具有下端部,下端部浸入第一浇注料中。
Description
技术领域
本发明涉及对湿气密封的半导体模块和用于其制造的方法。
背景技术
本发明涉及半导体模块。为了半导体模块的电接触和接线需要电连接端,这些电连接端必须被引导穿过壳体到壳体的外侧。由于壳体处的对应的引线,水蒸气和/或其他物质可能进入到半导体模块的内部,这可能例如由于腐蚀导致在模块中存在的元件的损坏。尽管出于各种原因用硅胶浇注半导体模块,但是这种胶对于水蒸气或其他有害物质不是特别好的屏障,从而所述问题几乎没有改善。
在其他模块结构中,处于硅胶上面的壳体内部区域用由环氧树脂制成的硬化浇注物填充,所述硬化浇注物置于硅胶上。这种模块虽然比包含硅胶、但不含硬化浇注物的模块对气体和水蒸气密封性更好。但是硬化浇注物硅胶连同壳体。硅胶具有高的热体积膨胀系数,这在半导体模块的强温度变换负荷时可以形成过压或欠压,通过所述过压或欠压可能引起在模块内部中的损坏。在胶中的过压情况下,可能出现在底板和壳体之间的胶的溢出。在欠压情况下可能形成胶中的缝隙。由此出发,在市场上存在的对应模块中,附加的硬化浇注物的目的在于,使半导体模块内部中的组件在机械上稳定。
发明内容
本发明的任务在于,提供半导体模块,该半导体模块良好地被保护以防腐蚀和/或由于湿气和/或其他围绕半导体模块的有害物质可能引起的其他损坏。另一任务在于,提供一种用于制造这种半导体模块的方法。这些任务通过按照权利要求1所述的半导体模块或者通过按照权利要求21所述的用于制造半导体模块的方法来解决。本发明的构型和改进方案是从属权利要求的主题。
半导体模块包括:带有两个外壁区段的壳体,所述外壁区段布置在壳体的相对侧上;盖,其从所述外壁区段之一延伸向所述外壁区段的另一个;以及布置在这些外壁区段之间的并且与其间隔开的第一井筒壁,所述第一井筒壁限定第一井筒的边界。此外,该半导体模块还具有带有上侧的电路载体以及半导体芯片,所述半导体芯片布置在壳体中并且在该电路载体的上侧上。导电的第一连接端元件延伸通过第一井筒并且从壳体中伸出。在电路载体和盖之间以及部分地在第一连接端元件和第一井筒壁之间有第一浇注料,所述第一浇注料与第一连接端元件共同作用地将第一井筒密封。在第一井筒壁的朝向电路载体的一侧上,第一井筒壁具有下端部,该下端部浸入第一浇注料中。可选地,第一浇注料在此可以连续地从电路载体穿过伸展直至超过整个与电路载体材料配合地连接的半导体芯片。只要该半导体芯片通过接合线连接到其背离电路载体的一侧上,则第一浇注料可以同样可选地也连续地延伸超过全部接合线。
此外,在第一浇注料和盖之间以及部分地在第一连接端元件和第一井筒壁之间有第二浇注料,其同样与第一连接端元件共同作用地将第一井筒密封。在壳体中此外还存在一个或多个体积区域,所述体积区域分别直接地与第一浇注料邻接并且用气体填充。通过在所述一个或多个体积区域中存在的气体,第一浇注料的例如由于温度变化引起的体积变化被补偿,使得不会形成对在模块中存在的元件的干扰性负荷。
水蒸气进入到模块壳体内部基本上通过在第二浇注料封闭井筒的区域中的第二浇注料的长度和横截面来确定,以及通过第二浇注料的水蒸气扩散系数来确定。总之,半导体模块对抗水蒸气至模块壳体内部的进入的所希望的最小密封性可以通过上述参数的组合来调整。按照意义,上面所述的也适于其他有害物质作为水蒸气进入到模块壳体内部。
为了制造这种半导体模块,提供一件式或多件式的壳体,该壳体具有两个外部区段、盖和第一井筒壁。外壁区段处于壳体的相对侧上。同样,提供带有上侧的电路载体、半导体芯片和导电的第一连接端元件。半导体芯片、电路载体、壳体和第一连接端相对彼此被布置为,使得该盖从所述外壁区段之一伸展到所述外壁区段的另一个,第一井筒壁布置在外壁区段之间并且限定第一井筒的边界,半导体芯片布置在壳体中并且布置在电路载体的上侧上,并且第一连接端元件延伸通过第一井筒并且从壳体伸出。
在壳体的内部空间中,填入第一浇注料并且随后该第一浇注料交联,使得交联的第一浇注料布置在电路载体和盖之间以及部分地布置在第一连接端元件和第一井筒壁之间并且与第一浇注料共同作用地密封第一井筒,其中第一井筒壁具有下端部,该下端部浸入第一浇注料中。
在第一浇注料交联之后,将第二浇注料填入壳体的内部空间中,使得第二浇注料布置在第一浇注料和盖之间以及部分布置在第一连接端元件和第一井筒壁之间并且与第一连接端元件共同作用地密封第一井筒,并且在壳体中保留一个或多个分别直接与第一浇注料邻接的并且用气体填充的体积区域。
附图说明
本发明的各种可能的构型下面参照附图来阐述。在图中所示的组件不必相互合乎比例地示出,更确切地重点是阐明本发明的原理。此外,在图中相同的附图标记表示相同或彼此对应的元件。
图1A至1C示出了在制造带有整块底板的半导体模块时的不同步骤。
图2A至2C示出了在制造带有整块底板的另一半导体模块时的不同步骤。
图3示出了半导体模块,其与按照图1C的半导体模块不同之处在于没有底板。
图4示出了半导体模块,在其中分别布置有电连接端元件的井筒通过连接通道相互连接。
图5示出了半导体模块,其与按照图3的半导体模块不同之处在于第二浇注料不伸展至壳体盖的朝向电路载体的那侧。
图6示出了半导体模块,其与按照图4的半导体模块不同之处在于第二浇注料不伸展至壳体盖的朝向电路载体的那侧。
图7示出了半导体模块的一件式壳体。
图8A至8C示出了在制造带有多件式壳体的半导体模块的制造中的不同步骤。
图9示出了比较模块,其按照本发明的半导体模块来构建,但是其中在第一浇注料中产生的空腔中使用用于检测相对空气湿度的传感器。
图10示出了图表,从中针对两个不同的、按照本发明构建的半导体模块得知当将比较模块引入潮湿气氛中时在空腔中存在的相对空气湿度的变化曲线,在所述半导体模块中分别用填充有空气的空腔来代替半导体芯片。
图11示出了根据图6的布置在截平面E-E中的水平视图,所述截平面延伸经过井筒和体积区域。
具体实施方式
图1A示出了部分制成的半导体模块100的横截面。该半导体模块100包括壳体6、一个或多个衬底2、一个或多个半导体芯片8、以及一个或多个导电连接端元件91,92。
壳体6具有:两个外壁区段61,这些外壁区段布置在壳体6的相对侧上;盖62,该盖从外壁区段61中的一个伸展至外壁区段61中的另一个;以及一个或多个布置在外壁区段61之间并且与其间隔开的井筒壁63。此外,存在一个或多个井筒65,它们中的每一个通过至少一个井筒壁63限定边界。导电的连接端元件91,92(其从壳体6伸展出去)分别延伸经过井筒65之一。在该情况下,与本发明的所有其他半导体模块100一样,半导体模块100的一个、多个或全部连接端元件91、92与最接近相关连接端元件91、92的井筒壁63间隔开。
与此无关地,井筒壁63可以可选地环状包围连接端元件91、92中的一个或多个。同样也存在如下可能性,井筒65通过外壁区段61和井筒壁63来限定边界,使得外壁区段61和井筒壁63一起环状包围连接端元件91、92之一。
衬底2包括带有朝向壳体6的上侧201的电绝缘的电路载体20。半导体芯片8布置在壳体6中并且布置在电路载体20的上侧201上。在另外的构型中,也可以使用例如由金属制成的导电电路载体20。将结构化的上金属化层21施加到电路载体20的上侧201上,并且将可以是非结构化或者结构化的下金属化层22施加到电路载体的与上侧201相对的下侧202上。衬底2例如可以是DCB衬底(DCB=direct copper bonded(直接铜接合))、DAB衬底(DAB=direct aluminum blazed(直接铝钎焊))或者AMB衬底(AMB=active metal brazed(活性金属钎焊))。
一个或多个半导体芯片8安装在上侧的金属化层21上并且借助连接层81——例如焊料、导电粘合剂或压力烧结的含银的连接层——以机械方式或可选地也以导电方式连接。半导体芯片8例如可以是由如晶体管、MOSFET、IGBT、晶闸管、JFET(尤其是HEMT[HEMT=High Electron Mobility Transistor(高电子迁移率晶体管)])的可控半导体芯片和/或如功率二极管的不可控半导体芯片构成的任意组合。半导体芯片8可以被构造为功率半导体芯片,其具有例如大于10A或者大于50A的高标称电流和/或拥有例如400v或者更大的高标称截止电压。附加地,半导体芯片8的每个的基面大于2.4mm×2.4mm,或者大于5mm×5mm。
为了半导体芯片8的布线设置有接合线5,所述接合线接合到上侧金属化层21的区段上。代替接合线5同样可以使用金属夹,所述金属夹借助焊料、导电粘合剂或带有烧结的导电粉的层例如被连接到半导体芯片的上侧和/或上侧的金属化层21。
为了将功率半导体模块外部地连接到例如电压供给、负载、控制装置等等上,设置有电连接端元件91、92,它们可以导电地和/或以机械方式与上侧的金属化层21连接。从半导体模块100的连接端元件91、92中仅仅示出了几个示例性例子。原则上,连接端元件91、92的数量和结构方式可以任意选择并且适配于在半导体模块100中要实现的电路。连接端元件91、92中的几个例如可以用于将半导体模块100连接到供给电压,例如中间回路电压或要整流的交流电压。在连接端元件91、92中的另外的连接端元件上可以连接负载、例如电感负载如电动机,以便利用半导体模块100来控制所述负载。连接端元件91、92中的又一些另外的连接端元件可以用作控制输入端或控制输出端,或者用作用于输出信号的输出连接端,这些信号代表涉及半导体模块100的状态的信息。
为了将连接端元件91、92与上金属化层21导电连接,可以将所述连接端元件钎焊、熔焊、烧结或导电粘合到上金属化层21上或者通过线接合连接到其上。连接端元件91、92例如可以被构造为直线或弯曲的金属引脚,被构造为冲孔的和弯曲的金属薄板,被构造为小管,被构造为导电接触弹簧等等。在引脚的情况下,连接端元件也可以被***到套中,这些套被钎焊、熔焊、或导电粘合到上金属化层21上。与半导体模块100的另外的连接端元件91、92的构型无关地,连接端元件91、92、例如所示的连接端元件92也可以拥有多个连接腿,在其上连接端元件与上金属化层21导电连接。
在连接端元件91、92的自由的、与衬底2间隔开的端部上,连接端元件91、92可以根据所希望的电连接技术被任意地构造,例如,如所示地构造为旋拧孔,但是也可以被构造为焊接接触部,弹簧接触部,压入接触部(压配合接触部),夹子接触部等等。
与其构型无关,一个或者多个连接端元件91、92可以如示出地布置在两个处于壳体6相对侧上的外壁区段61之间并且与其间隔开。
可选地,衬底2可以布置在整块的底板1上,并且在衬底2的下金属化层22上在使用连接层42的情况下以机械方式与底板1连接。连接层42例如可以是焊接层、压力烧结的含银连接层或者粘合剂层。底板1本身可以被构造为金属板,例如由铜、铝或带有这些金属中至少之一的合金制成的金属板,或者由金属基质复合材料(MMC)构造。可选地,底板1还可以具有涂层,以便例如改善烧结的连接层的可焊接性或粘附性。与底板1的构型无关,底板1可以具有至少1mm、至少2mm或者至少3mm的厚度。下金属化层22可以例如具有小于或等于1mm的厚度或者小于或等于0.63mm的厚度。
带有以所述方式具有一个或多个半导体芯片8和一个或多个连接端元件91、92的预先装备的衬底2(该衬底2可以可选地与底板1连接)的单元现在可以与壳体6连接。为此,可以将壳体6一件式地构造,并且对于连接端元件91、92的每个具有井筒65,该井筒构造为使得连接端元件91、92当壳体6安置到单元上时可以***到所属的井筒65中,使得连接端元件的自由端部可以到达壳体6的外侧用于连接端元件91、92的电接触。
安置到单元上的壳体6可以借助连接装置9、例如粘合剂与该单元连接。
在安置壳体6之后,可选地也在将单元与壳体6连接之后,可以将第一浇注料51例如硅胶填充到其中。为此,第一浇注料51可以经由填充井筒64填充到壳体6的内部,使得浇注料分布到衬底2上,其中填充井筒由所述井筒65之一构成。第一浇注料51的量在此这样分配,使得井筒壁63的朝向载体20的端部631浸入到第一浇注料51中并且在第一浇注料51接着被交联以便减少或者去除其可流动性之后仍然保持浸入其中。在此该交联可以通过提高温度、通过在正常环境条件下长时间的存放或者通过用紫外光照射来进行。在图1B中示出了结果。在该构型中如在本发明的所有其他构型中那样,所述交联被进行为使得仅仅存在小的交联度,从而第一浇注料51仅仅被提供以便在如下程度上封闭井筒65,即第二浇注料52当其接下来如后面还要阐述的一样被填充到井筒65中时仅能到达通过第一浇注料51产生的浇注部位并且由此保留在第一浇注料51之上的位置处。
通过井筒壁63的朝向载体20的端部631在第一浇注料51交联之后也浸入到其中,当之后(如下面描述地)填充第二浇注料时,第一浇注料51与处于该井筒65中的连接端元件91、92共同作用地密封所涉及的井筒65。填充井筒64也在其端部631的区域中通过第一浇注料51相应地被密封。原则上,浸入深度t63在第一浇注料51交联之后可以在半导体模块100的井筒65(包括填充井筒64)中的一个、多个或每个的井筒壁63的朝着载体20的端部631处大于或等于0.5mm。
与此无关地,在半导体模块100的井筒壁63中的一个、多个或每个处,在上侧201和所涉及的井筒壁63的朝向载体20的端部631之间的距离d2可以为最大4mm或最大2mm。
在第一浇注料51交联之后,井筒65和可选的填充井筒64分别在其朝向载体20的端部631处被第一浇注料51封闭,使得于是第二浇注料52——例如环氧树脂或者具有对水蒸气足够高扩散阻力或足够低扩散系数的其他浇注物——可以填充到壳体6的内部中,该第二浇注料52构成对抗水蒸气和/或其他有害物质进入到壳体6内部的屏障。在该构型中如本发明的所有其他构型中那样,第二浇注料52可以为此针对水蒸气具有如下扩散系数,所述扩散系数在温度为40℃时小于。
在特别的构型中,本发明的第二浇注料对于水蒸气可以具有分别在40℃时小于 、小于、或者小于 的扩散系数。在所示的例子中,第二浇注料52必须分别单独地被填充到井筒65和填充井筒64中,因为它们现在被封闭了,使得第二浇注料52不能如先前第一浇注料51那样可以侧向分布在壳体内部。填充到井筒65中并且然后被硬化的第二浇注料52与在所涉及的井筒65中的连接端元件91、92共同作用地密封该井筒65。填充井筒64也通过第二浇注料52被密封。该结果在图1C中示出。
在本发明的全部半导体模块100中,第一浇注料51可以可选地在交联之后具有大于第二浇注料52在其交联之后所具有的渗透的渗透。与此无关地,完成交联的第二浇注料52的渗透可以大于壳体6的渗透。在任何情况下,按照DIN ISO 2137来确定渗透。第一浇注料例如可以具有至少20的渗透,例如在30至90的范围中。与此无关地,第二浇注料可以可选地同样在本发明的全部半导体模块100中例如具有最高20的渗透,例如在10至20的范围中。
与此无关地,在借助前面的图阐述的也如在本发明所有其他实施例中那样,完成交联的第二浇注料52具有如下渗透:其从胶的渗透延伸直至环氧树脂或聚酯树脂的渗透或硬度。例如环氧树脂、聚酯树脂、硅树脂或硅胶适合作为第二浇注料52。
如在图1C中所示,硬化的第二浇注料52相对于电路载体20的上侧201的填充高度延伸直至壳体盖62的朝向电路载体20的下侧622的水平之上。
在任何情况下,一个或多个用气体、例如空气填充的体积区域60被保留,在这些体积区域中的每一个直接地邻接第一浇注料51,使得通过温度变换负荷引起的第一浇注料51的体积变化在很大程度上被补偿,因为位于一个或多个体积区域60中的空气在需要时被压缩或者被膨胀,而在此不会出现半导体模块100的处于壳体6中的元件的显著的压力负荷。这里,“体积区域”理解为连续的、用气体填充的空间区域的最大体积,所述空间区域直接邻接第一浇注料51并且在其中气体中的小部分可以***。
如同样由图1C可知,交联的第一浇注料51相对于上侧201的水平的填充高度可以被选择为,使得直接邻接到第一浇注料51的体积区域60中的每个、多个或全部在半导体模块100内部在垂直于上侧201的竖直方向v上具有相同的或者不同的高度t60,所述高度中的每个高度例如大于或等于1mm或大于或等于5mm。由此保证了:对于热引起的第一浇注料51的膨胀可以提供足够的体积,在其中第一浇注料51可以膨胀。
此外在图1C中示出了,井筒65——在垂直于电路载体20的上侧201的方向v上测量——具有填充高度t65。半导体模块100的不同井筒65的填充高度t65在此可以是相同或不同的。例如在半导体模块100的一个、多个或全部井筒65中各自的填充高度t65可以为至少1mm。该可选的标准也可以在本发明的所有其他半导体模块100中实现。
为了能够实现一个或多个体积区域60的特别有效的作用,有利的是在半导体模块100的井筒65的一个、多个或全部中,所涉及井筒65的外尺寸b65平行于上侧201地测量小于或等于5mm。
图2A示出了部分完成的半导体模块100的横截面,该部分完成的半导体模块100与按照图1A的部分完成的半导体模块100的不同之处仅仅在于,各个井筒65和填充井筒64通过水平延伸的连接通道66相互连接。连接通道66可以可选地被布置为,使得全部井筒65和填充井筒64构成通道***,当第二浇注料52经由填充井筒64被填充到壳体6的内部中时,第二浇注料52经由所示通道***分布到各个井筒65和填充井筒64上并且密封它们。
图2B示出了在第一浇注料填充和交联之后的布置,图2C示出了在第二浇注料52的填充和硬化之后的布置。
图3示出了半导体模块100的横截面,半导体模块100与在图1C中所示的半导体模块100的不同之处仅仅在于,它不具有如先前所述的底板1和连接层42,而是下金属化层22自由地靠置在半导体模块100的下侧上,并且壳体6在至衬底2的连接区域中的走向以及连接装置9的走向被适配。
图4示出了半导体模块100的横截面,其与在图2C中所示的半导体模块100的不同之处仅仅在于,它不具有如先前所述的底板1和连接层42,而是下金属化层22自由地靠置在半导体模块100的下侧上,并且壳体6在至衬底2的连接区域中的走向以及连接装置9的走向被适配。
图5示出了半导体模块100的另一个例子。其不同于按照图3的半导体模块100之处仅仅在于,硬化的第二浇注料52相对于电路载体20的上侧201的填充高度小于在电路载体20的上侧201和壳体盖62的朝向电路载体20的下侧622之间的距离。
相应地,图6示出了半导体模块100,其与在图4中所示半导体模块100的不同之处仅仅在于,硬化的第二浇注料52相对于电路载体20的上侧201的填充高度小于在电路载体20的上侧201和壳体盖62的朝向电路载体20的下侧622之间的距离。
图7示出了半导体模块100的壳体6,这里例如在图1C中描述的半导体模块100的壳体6。一般而言,半导体模块100的壳体6可以一件式、也即由一个唯一部分构成并且由统一的材料制成,例如由热塑性塑料或热固性塑料制成。这种壳体6例如可以通过喷铸来制造。只要允许要制造的壳体6的底切,就可以通过喷铸来一体制造壳体6。代替地也存在如下可能性:单独地通过喷铸来制造两个或多个壳体部件并且之后将它们彼此固定连接,使得形成一件式壳体6。这种连接可以材料配合地、例如借助粘合剂来进行,通过激光焊接、超声波焊接或者热焊接、或者通过旋拧或者任意其他连接技术来进行。
原则上,壳体6可以在未组装状态下就已经如所阐述的那样一件式地构造,也即在壳体6还没有安装在带有预先装备的衬底2(带有或没有底板1)的上述单元上的状态下。
但是代替于此地,壳体6也可以由两个或多个部分组成,这例如借助图8A、8B和8C来阐述。图8A在下部示出了带有预先装备的衬底2和与衬底2连接的底板1的单元,所述底板1如先前借助图1A至1C所描述的那样。此外,示出了带有围绕的壳体框架的壳体6,所述壳体框架构成侧壁61,以及示出了与壳体框架无关的盖62,在盖62上为了实现井筒65(包括填充井筒64)而构造有井筒壁63。此外,连接通道66集成在盖62中。
原则上,壳体6和/或第二浇注料52具有大于50℃、大于120℃、大于140℃、或者甚至大于150℃的玻璃转变温度,这可以用可用的塑料或浇注料来实现。
在本发明意义上的全部半导体模块100中同样存在如下可能性:对于壳体6和/或第二浇注料52使用具有在55℃至95℃范围中的、例如为大约90℃的玻璃转变温度的材料。这种构型引起:在半导体模块100的运行期间超过玻璃转变温度,使得壳体6或第二浇注料52的水蒸气穿透性上升并且湿气从壳体6的内部逸出并且向壳体6的外部环境输出。在常见的环境条件中,40℃的温度和90%rH的相对空气湿度通常不会被超过。
壳体框架和盖62可以(分别单独地假设)一件式、也即由一个唯一的部件构造并且由统一的材料制成,例如由热塑性或热固性塑料制成。在此,壳体框架和盖62由相同的或者由不同的材料构成。壳体框架和壳体盖62的制造例如可以通过喷铸来进行。壳体6可以在未组装状态下就已经如所阐述的那样一件式地构造,也即在壳体6还没有安装在带有预先装备的衬底2(带有或没有底板1)的上述单元上的状态下。
其他的安装现在可以进行为使得壳体框架安置到带有预先装备的衬底2的单元上并且与其例如借助连接装置9或者以其他方式连接,这结果在图8B中示出。
之后,将壳体盖62安置到该复合体上(如在图8C中所示)并且随后与壳体框架连接。所述连接可以材料配合地例如借助粘合剂来进行,通过激光焊接、超声波焊接或者热焊接、或者通过旋拧或者任意其他连接技术来进行。如在图8A中所示,在壳体框架和盖62之间的连接可以被构造为凹槽-弹簧连接。由此,一方面使得盖62在壳体框架处的安装变得容易,另一方面使得在盖62和壳体框架之间的缝隙7的长度变大并且随之而来地减小如下危险:有害物质经过缝隙7并且可能经过处于其中的粘合剂而进入到壳体6内部。在图8A至8C中所示的例子中,在壳体框架上构造有凹槽,并且在壳体盖62上构造有弹簧。但是相反地,也可以在壳体框架上构造弹簧并且在壳体盖62上构造凹槽。除了壳体6不是一件式地被构造之外,在图8C中所示的布置与按照图1C的布置是相同的。通过相同的方式,任意其他半导体模块100的壳体6也可以构造并且制造为两件或多件式。
在壳体框架和盖62之间的连接的制造原则上可以在第一浇注料51和/或第二浇注料52的填充之前或之后进行,代替地也可以通过填充第二浇注料52来进行。在后一种所述的情况下,第二浇注料52也用作粘合剂,该粘合剂将壳体框架和盖62连接。
为了完成半导体模块100,如其在图8C中所示,在其壳体6中还填充第一浇注料51并且其后根据先前所述方法填充第二浇注料52。
在本发明的全部半导体模块中,第二浇注料52与井筒65共同作用地表现为对抗湿气和可能其他有害物质进入壳体6内部的有效屏障。在井筒65和分别通过其延伸的连接端元件91、92之间的缝隙越小,填充开口64的横截面越小并且第二浇注料52的层厚越大,屏障作用越大。
为了对于确定的半导体模块100测试所述密封作用,可以使用比较模块或“模拟(Dummy)”模块101,如其示例性地在图9中所示。这种比较模块101可以同样如所基于的半导体模块100那样构造,具有如下的唯一区别,将经由连接线路31、32可读出的用于确定在第一浇注料51(例如参见图1C)中产生的空腔35中存在的相对空气湿度的传感器元件安装到所述空腔35中。可选地,也可以在空腔35中布置温度传感器元件和/或压力传感器元件。所述传感器元件中的一个、多个或全部可以如所示那样集成在一个共同的传感器30中。但是这些传感器元件也可以集成在分开的传感器中,这些传感器处于空腔中,或者例如用于确定温度和相对空气湿度的两个传感器元件可以集成在一个共同的传感器30中,而压力传感器元件集成在另外的传感器中,所述另外的传感器同样布置在空腔35中。在需要时,也可以使用多于两个的电连接线路,用于对传感器30和(只要存在)一个或多个附加的传感器进行接线。
这种比较模块101例如可以通过如下方式被制造,在用第一浇注料51和第二浇注料52浇注壳体6内部的半导体模块100中又去除第一浇注料51。这例如可以通过如下方式来进行,将完成的半导体模块100的壳体6钻孔直至到达第一浇注料51并且通过所形成的孔去除如此多的第一浇注料51,使得形成能够在其中置入一个或多个传感器30的空腔35。将所述一个或多个传感器30置入空腔35中在此进行为,使得在一个或多个传感器30之后保留用空气填充的测量体积33,该测量体积的相对空气湿度被检测。连接端31、32在此通过所述孔向外引导并且然后所述孔被密封地封闭,这例如可以借助粘合剂例如环氧树脂粘合剂来进行。
代替地或补充地,这种传感器30可以以相应的方式也置入到所述体积区域60中或者所述体积区域60之一中。在这种情况下,所涉及的体积区域60构成空腔35。第一浇注料51通过孔的部分去除在该情况下被取消。
同样存在如下可能性,在填充第一浇注料51时将一个或多个传感器30嵌入其中。为了确保保留带有空气体积的空腔35——所述空气体积达到直至位于传感器30中的传感器元件,传感器30可以被空气可穿透的例如栅格状的保护罩覆盖,当第一浇注料51被填充到壳体6中时,该保护罩保持住第一浇注料51。
此外,也可以在填充浇注料51和52之前将一个或多个这种传感器30布置在体积区域60中并且然后如已经阐述地首先将第一浇注料51并且接着将第二浇注料52填充到壳体6中。
原则上,也可以设想另外的变型方案,利用这些变型方案可以产生这种比较模块101。在任何情况下,这取决于处于壳体6中的、用空气填充的测量体积33直接邻接第一浇注料51,其中所述测量体积达到直至处于传感器30中的传感器元件。
借助这种比较模块101现在能够实现:当比较模块101处于具有恒定温度TEXT、恒定相对空气湿度rHEXT和恒定压力pEXT的定义环境中并且测量体积33中的相对空气湿度的时间发展被测量时,通过测量在空腔35中的相对空气湿度来研究密封效果。在此前提是:在开始测量之前模块内部具有明显小于在定义环境中的相对湿度的湿度以及与定义环境中的压力相同或基本相同的空气压力。明显较小的相对湿度这一前提可以通过在高温下干燥半导体模块100来实现。因为相对空气湿度强烈地与温度相关,因此用于测量相对空气湿度的时间发展的比较模块作好准备地首先被置于确定的温度例如20℃,并且然后在时刻t0被引入到定义的环境中,该环境具有相同的温度并且其相对空气湿度高于在时刻t0时(同样在确定温度时)在空腔35中存在的相对空腔湿度rH35(t=t0)。因为在空腔35中存在的相对空气湿度的值与在空腔35中主导的参量压力和温度相关,因此同样可以测量这些参量的时间发展,从而能够实现,将时间相关地测量的相对空气湿度换算成压力和温度的标准值(例如1013.25hPa和20℃)并且由此实现可比较的结果。
从时刻t0开始,环境中包含的湿气进入到壳体6中并且在此也到达处于空腔35中的气体(例如空气),使得空气的相对湿度rH35(t)随时间t上升。目前将持续时间D用作对于密封效果的度量,在所述持续时间之后在空腔35中在时刻t0时存在的起始相对空气湿度rH35(t=t0)——关于1013.25hPa的压力和20℃——升高了在相对环境空气湿度rH35(t=t0+D)和起始相对空气湿度rH35(t=t0)之间的差的0.6倍——同样是关于1013.25hPa的压力和20℃。所述持续时间D例如可以为至少24小时,至少48小时,至少168小时或者至少400小时。
为此图10针对两个不同良好地密封的半导体模块示出了在空腔35中存在的相对空气湿度rH35(t)从时刻t0起——即从将所涉及的比较模块101置入到具有定义的相对湿度rHEXT、定义的温度TEXT和定义的压力PEXT的该环境中起——相应的时间发展。曲线1对应于较差地密封的比较模块101的变化曲线,并且曲线2相应于较好地密封的比较模块101的变化曲线。在所示的例子中,在空腔35中的起始相对空气湿度rH35(t=t0)在20℃的温度时处于20%,而在相应比较模块101的环境中的定义的相对湿度rHEXT在20℃时为90%。
现在为了确定密封效果,分别确定如下持续时间,在所述持续时间中在空腔35中的相对湿度rH35(t)相对于高度为20%的起始相对空气湿度rH35(t=t0)上升了所述差(90%-20%=70%)的0.6倍、也即0.6*70%=42%,也即直至相对空气湿度rH35(t)上升到20%+42%=62%的值。在较差地密封的比较模块101(曲线K1)的情况下,在时刻t1、也即在持续时间D1=t1-t0之后达到该62%的值,在较好地密封的比较模块101(曲线K2)的情况下,在时刻t2、也即在持续时间D2=t2-t0之后达到该62%的值。在所示的例子中,D1=28小时,D2=310小时。
图11示出了按照图2C的布置在截平面E-E中的水平视图,所述截平面延伸经过井筒65和(在该例子中唯一的)体积区域60。然而,也可以在图1C和3至6的半导体模块100的相应剖面的情况下得到同样的剖视图。
如在该视图中可见的,半导体模块100的通过井筒壁63限定边界的全部井筒65如在填充井筒64中一样或者仅仅通过第二浇注料52被密封或者如在其他井筒65中一样通过第二浇注料52与延伸在所涉及的井筒65中的连接端元件91、92连接地被密封,使得在壳体6外部的氛围不能直接通过井筒64、65到达第一浇注料51。
同样可见,半导体模块100仅仅包括一个唯一的体积区域,其在电路载体20的上侧201上的正交投影具有面积A60。在其他半导体模块100中,也可以存在两个或更多成对地相互独立的体积区域60。在此,“独立”意味着在两个独立的体积区域60之间不能自由地进行气体交换。在两个或更多在此意义上独立的体积区域60的情况下,其在电路载体20的上侧201上的正交投影可以构成连续的面积A60,但是或者构成两个或更多独立的面积,其总面积又是A60。与半导体模块100是否仅仅拥有正好一个唯一的或者两个或更多这样的体积区域60无关,A60说明直接邻接第一浇注料51的全部体积区域60的总投影面。
在图11中还用虚线示出了(因为是隐藏的),电路载体20的上侧201的侧向边界线,其面积大小用A20表示。半导体模块100现在可以被构建为使得A60与A20的比大于或等于0.7,也即A60为A20的至少70%。
在本发明中设计的井筒65能够实现使用仅仅非常少量的第二浇注料52,同时实现对抗湿气和其他有害物质进入壳体6的好的密封效果。例如第二浇注料52可以具有关于上侧201的面A20小于或等于1克每平方厘米的总量。
与此无关地,硬化的第二浇注料52和壳体6的材料可以被选择为使得水在第二浇注料52中和在壳体中的可溶解性分别为第二浇注料52和壳体6的总重量的最大0.5重量%或者最大0.2重量%。
前面阐述了对于半导体模块100的可能构型的各种实施例。在此背景中在一个实施例中所述的一个或多个特征可以以任意方式与来自一个或多个其他实施例中的一个或多个特征组合,只要这些特征不相互排除。
前面阐述了半导体模块100的各种实施例。在这些实施例中如在本发明的所有其他实施例中一样,在此可以可选地使用这种浇注料作为第一浇注料51,其在交联之后作为胶、例如作为硅胶存在。然而原则上可以使用浇注料51,其在交联之后具有根据DIN ISO 2137的小于40的渗透并且由此具有比典型的交联的胶更小的渗透(根据DIN ISO 2137在40-70范围中的渗透)。
Claims (22)
1.一种半导体模块,包括:
具有两个外壁区段(61)的壳体(6),所述外壁区段布置在壳体(6)的相对侧上;盖(62),其从所述外壁区段(61)中的一个延伸向所述外壁区段(61)中的另一个;以及布置在这些外壁区段(61)之间并且与其间隔开的第一井筒壁(63),所述第一井筒壁限定第一井筒(65)的边界;
带有上侧(201)的电路载体(20);
半导体芯片(8),其布置在壳体(6)中并且布置在电路载体(20)的上侧(201)上;
导电的第一连接端元件(91,92),其延伸通过第一井筒(65)并且从壳体(6)中伸出;
第一浇注料(51),该第一浇注料布置在电路载体(20)和盖(62)之间以及部分地在第一连接端元件(91,92)和第一井筒壁(63)之间,并且该第一浇注料与第一连接端元件(91,92)共同作用地将第一井筒(65)密封;
第二浇注料(52),该第二浇注料布置在第一浇注料(51)和盖(62)之间以及部分地在第一连接端元件(91,92)和第一井筒壁(63)之间,并且该第二浇注料与第一连接端元件(91,92)共同作用地将第一井筒(65)密封;以及
一个或多个体积区域(60),所述体积区域分别直接地与第一浇注料(51)邻接并且用气体填充,其中第一井筒壁(63)在其朝向电路载体(20)的侧上具有下端部(631),该下端部浸入第一浇注料(51)中。
2.根据权利要求1所述的半导体模块,其中第一井筒壁(63)的下端部(631)以至少0.5mm的浸入深度(t63)浸入第一浇注料(51)中。
3.根据权利要求1或2所述的半导体模块,其中第二浇注料(52)针对水蒸气具有扩散系数,该扩散系数在40℃的温度时小于5*10-9m2/s,小于1*10-11m2/s,或者小于1*10-12m2/s。
4.根据上述权利要求之一所述的半导体模块,其中在处于壳体(6)中的全部用气体填充的体积区域(60)正交地投影到电路载体(20)的上侧(201)上时形成的总投影面对应于所述上侧(201)的面积的至少70%。
5.根据上述权利要求之一所述的半导体模块,其中第一浇注料(51)所具有的渗透(根据DIN ISO 2137)大于第二浇注料(52)的渗透(根据DIN ISO 2137),并且其中第二浇注料(52)所具有的渗透(根据DIN ISO 2137)大于壳体(6)的渗透(根据DIN ISO 2137)。
6.根据上述权利要求之一所述的半导体模块,其中第一浇注料(51)根据DIN ISO 2137具有至少20的渗透和/或第二浇注料(52)根据DIN ISO 2137具有最高20的渗透。
7.根据上述权利要求之一所述的半导体模块,其中第一浇注料(51)根据DIN ISO 2137具有在30至90范围中的渗透。
8.根据上述权利要求之一所述的半导体模块,其中第二浇注料(52)根据DIN ISO 2137具有10至20的渗透。
9.根据上述权利要求之一所述的半导体模块,其中第一浇注料(51)根据DIN ISO 2137所具有的渗透大于第二浇注料(52)的渗透。
10.根据上述权利要求之一所述的半导体模块,其中第一浇注料(51)从电路载体(20)出发延伸直至至少在半导体芯片(8)之上并且半导体芯片(8)与第二浇注料(52)间隔开。
11.根据上述权利要求之一所述的半导体模块,其中
盖(62)具有朝向电路载体(20)的下侧(622);并且
第二浇注料(52)与下侧(622)间隔开。
12.根据权利要求1至10之一所述的半导体模块,其中
盖(62)具有朝向电路载体(20)的下侧(622);并且
第二浇注料(52)与下侧(622)接触。
13.根据上述权利要求之一所述的半导体模块,其中壳体(6)一件式地被构造并且由统一的、均匀材料制成。
14.根据上述权利要求之一所述的半导体模块,其中壳体(6)由与第一浇注料(51)的材料和/或第二浇注料(52)的材料不同的材料制成。
15.根据上述权利要求之一所述的半导体模块,其中所述至少一个体积区域(60)中的一个、多个或每个在垂直于电路载体(20)的上侧(201)的竖直方向(v)上延伸经过至少1mm或延伸经过至少5mm。
16.根据上述权利要求之一所述的半导体模块,其中
第二浇注料(52)具有总量并且该总量与电路载体(20)的上侧(201)的面积(A20)之比小于或等于1克每平方厘米。
17.根据上述权利要求之一所述的半导体模块,其中壳体(6)具有布置在两个外壁区段(61)之间的第二井筒壁(63),该第二井筒壁限定第二井筒(65)的边界并且该第二井筒壁在其朝向电路载体(20)的侧上具有下端部(631),该下端部浸入第一浇注料(51)中,其中
导电的第二连接端元件(91,92)延伸通过该第二井筒(65)并且从壳体(6)中伸出;
壳体(8)具有连接通道(66),该连接通道将第一井筒(65)和第二井筒(65)彼此连接。
18.根据权利要求17所述的半导体模块,其中该连接通道(66)完全或者部分地被第二浇注料(52)填充。
19.根据上述权利要求之一所述的半导体模块,其中第二浇注料(52)在第一井筒(65)中伸展经过至少1mm的填充高度(t65)。
20.根据上述权利要求之一所述的半导体模块,其中湿气能够通过其从壳体(6)的外侧进入壳体(6)的内部空间中的、构造在壳体(6)中的全部开口借助第一浇注料(51)和/或第二浇注料(52)被密封,使得比较模块(101)中,该比较模块的结构与半导体模块(100)的结构的不同之处在于,在与第一浇注料(51)邻接的用空气填充的空腔(35)中相对壳体(6)密封地置入了带有用于检测相对空气湿度的传感器元件的传感器(30),使得在空腔(35)中保留用空气填充的测量体积(33),该测量体积达到直至传感器元件,并且使得从将具有20℃恒定温度的该比较模块(101)引入具有恒定相对环境湿度(rHEXT)、20℃恒定温度(TEXT)和1013.25hPa的恒定压力(pEXT)的环境中的第一时刻(t0)起,在测量体积(33)中在第一时刻(t0)时存在的、小于环境空气湿度(rHEXT)的起始相对空气湿度(rH35(t=t0))在至少24小时或至少48小时或至少168小时或者至少400小时的持续时间之后升高了在相对环境空气湿度(rHEXT)和起始相对空气湿度(rH35(t=t0))之间的差的0.6倍。
21.一种用于制造半导体模块的方法,具有步骤:
提供一件式或多件式的壳体(6),该壳体具有两个外部区段(61)、盖(62)和第一井筒壁(63);
提供带有表面(201)的电路载体(20);
提供半导体芯片(8);
提供导电的第一连接端元件(91,92);
将半导体芯片(8)、电路载体(20)、壳体(6)和第一连接端元件(91,92)相对彼此地布置为,使得
-该盖(62)从所述外壁区段(61)中的一个伸展到所述外壁区段(61)中的另一个,
-第一井筒壁(63)与外壁区段(61)间隔开地布置在所述外壁区段(61)之间并且限定第一井筒(65)的边界;
-半导体芯片(8)布置在壳体(6)中并且布置在电路载体(20)的表面(201)上;
-第一连接端元件(91,92)延伸通过第一井筒(65)并且从壳体(6)伸出;
在壳体(6)的内部空间中填入第一浇注料(51)并且随后第一浇注料(51)交联为,使得交联的第一浇注料(51)布置在电路载体(20)和盖(62)之间以及部分地布置在第一连接端元件(91,92)和第一井筒壁(63)之间并且与第一连接端元件(91,92)共同作用地密封第一井筒(65),其中第一井筒壁(63)在其朝向电路载体(20)的侧上具有下端部(631),该下端部浸入第一浇注料(51)中;并且
在第一浇注料(51)交联之后将第二浇注料(52)填入壳体(6)的内部空间中,使得第二浇注料(52)布置在第一浇注料(51)和盖(62)之间以及部分布置在第一连接端元件(91,92)和第一井筒壁(63)之间并且与第一连接端元件(91,92)共同作用地密封第一井筒(65),并且在壳体(6)中保留一个或多个分别直接与第一浇注料(51)邻接并且用气体填充的体积区域(60)。
22.根据权利要求21所述的方法,其中第二浇注料(52)在其被填充到壳体(6)的内部空间中之后被硬化,并且然后根据权利要求1至20之一来构造。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107689364A (zh) * | 2016-08-05 | 2018-02-13 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN108496256A (zh) * | 2016-01-20 | 2018-09-04 | 罗伯特·博世有限公司 | 声换能器组件和用于制造声换能器组件的方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5576543B1 (ja) * | 2013-09-12 | 2014-08-20 | 太陽誘電株式会社 | 回路モジュール |
US10825748B2 (en) * | 2015-12-15 | 2020-11-03 | Semiconductor Components Industries, Llc | Semiconductor package system and related methods |
US11342237B2 (en) * | 2015-12-15 | 2022-05-24 | Semiconductor Components Industries, Llc | Semiconductor package system and related methods |
US10347549B2 (en) * | 2016-04-30 | 2019-07-09 | Littelfuse, Inc. | Power semiconductor device module having mechanical corner press-fit anchors |
US10062621B2 (en) * | 2016-04-30 | 2018-08-28 | Ixys, Llc | Power semiconductor device module having mechanical corner press-fit anchors |
EP3451804B1 (en) * | 2017-08-28 | 2020-04-01 | Goodrich Actuation Systems Limited | Potting method |
US10283447B1 (en) * | 2017-10-26 | 2019-05-07 | Infineon Technologies Ag | Power semiconductor module with partially coated power terminals and method of manufacturing thereof |
DE102018114691B4 (de) * | 2018-06-19 | 2021-02-18 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitereinrichtung mit einem Gehäuse, Leistungshalbleiteranordnung und Verfahren zur Herstellung einer Leistungshalbleitereinrichtung |
DE102018116429B4 (de) * | 2018-07-06 | 2020-03-05 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitereinrichtung mit einem Leistungshalbleiterbauelement und einem Gehäuse |
DE102020115066B3 (de) | 2020-06-05 | 2021-10-14 | Pollmann International Gmbh | Vibrationsrobuste Elektronikkomponente |
DE102020132679B3 (de) | 2020-12-08 | 2021-08-12 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitereinrichtung und ein Verfahren zur Herstellung einer Leistungshalbleitereinrichtung |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020070439A1 (en) * | 2000-12-13 | 2002-06-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
CN1901211A (zh) * | 2005-07-19 | 2007-01-24 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
CN101355061A (zh) * | 2007-07-26 | 2009-01-28 | 塞米克朗电子有限及两合公司 | 包括用于基片载体的密封装置的功率半导体模块及其制造方法 |
DE102008045721A1 (de) * | 2008-02-18 | 2009-09-10 | Mitsubishi Electric Corp. | Halbleitervorrichtung |
CN101616864A (zh) * | 2006-12-21 | 2009-12-30 | 大陆-特韦斯贸易合伙股份公司及两合公司 | 封装模块、该封装模块的制造方法及应用 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59198740A (ja) * | 1983-04-25 | 1984-11-10 | Mitsubishi Electric Corp | 樹脂封止形半導体複合素子 |
DE3521572A1 (de) * | 1985-06-15 | 1986-12-18 | Brown, Boveri & Cie Ag, 6800 Mannheim | Leistungshalbleitermodul mit keramiksubstrat |
US6011302A (en) * | 1997-05-29 | 2000-01-04 | Fuji Electric Co., Ltd. | Semiconductor device with reduced amount of sealing resin |
WO2004010499A1 (ja) * | 2002-07-19 | 2004-01-29 | Matsushita Electric Industrial Co., Ltd. | モジュール部品 |
DE102010053809A1 (de) * | 2010-12-08 | 2012-06-14 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement, Verfahren zu dessen Herstellung und Verwendung eines derartigen Bauelements |
DE102011105374B4 (de) * | 2011-06-22 | 2021-12-23 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zum Herstellen einer Mehrzahl von optoelektronischen Halbleiterbauelementen im Verbund |
-
2012
- 2012-11-30 DE DE102012222015.1A patent/DE102012222015B4/de active Active
-
2013
- 2013-11-27 US US14/091,807 patent/US8922030B2/en active Active
- 2013-11-29 CN CN201310624507.XA patent/CN103855104B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020070439A1 (en) * | 2000-12-13 | 2002-06-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
CN1901211A (zh) * | 2005-07-19 | 2007-01-24 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
CN101616864A (zh) * | 2006-12-21 | 2009-12-30 | 大陆-特韦斯贸易合伙股份公司及两合公司 | 封装模块、该封装模块的制造方法及应用 |
CN101355061A (zh) * | 2007-07-26 | 2009-01-28 | 塞米克朗电子有限及两合公司 | 包括用于基片载体的密封装置的功率半导体模块及其制造方法 |
DE102008045721A1 (de) * | 2008-02-18 | 2009-09-10 | Mitsubishi Electric Corp. | Halbleitervorrichtung |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108496256A (zh) * | 2016-01-20 | 2018-09-04 | 罗伯特·博世有限公司 | 声换能器组件和用于制造声换能器组件的方法 |
CN108496256B (zh) * | 2016-01-20 | 2022-09-23 | 罗伯特·博世有限公司 | 声换能器组件和用于制造声换能器组件的方法 |
CN107689364A (zh) * | 2016-08-05 | 2018-02-13 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
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