CN103855035A - Equipment for preparing gate dielectric layer - Google Patents
Equipment for preparing gate dielectric layer Download PDFInfo
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- CN103855035A CN103855035A CN201410118214.9A CN201410118214A CN103855035A CN 103855035 A CN103855035 A CN 103855035A CN 201410118214 A CN201410118214 A CN 201410118214A CN 103855035 A CN103855035 A CN 103855035A
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- 238000000034 method Methods 0.000 claims abstract description 219
- 230000008569 process Effects 0.000 claims abstract description 156
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910007991 Si-N Inorganic materials 0.000 claims abstract description 17
- 229910006294 Si—N Inorganic materials 0.000 claims abstract description 17
- 238000005121 nitriding Methods 0.000 claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims abstract description 9
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 40
- 238000007254 oxidation reaction Methods 0.000 claims description 40
- 238000012545 processing Methods 0.000 claims description 28
- 238000005516 engineering process Methods 0.000 claims description 27
- 238000005915 ammonolysis reaction Methods 0.000 claims description 23
- 238000010438 heat treatment Methods 0.000 claims description 16
- 230000035755 proliferation Effects 0.000 claims description 6
- 230000032258 transport Effects 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 15
- 230000001590 oxidative effect Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 15
- 239000011261 inert gas Substances 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 238000000137 annealing Methods 0.000 description 8
- 230000008439 repair process Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- 230000008034 disappearance Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- 230000035515 penetration Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
Abstract
The invention provides equipment for preparing a gate dielectric layer. The equipment comprises a thermal treatment process cavity used for growing a SiO2 gate dielectric layer, a plasma nitriding process cavity used for performing plasma nitrogen injection on the gate dielectric layer to form a Si-N bond, a high-temperature nitriding cavity used for repairing lattice damage in the gate dielectric layer and stabilizing the Si-N bond, a low-temperature oxidizing cavity used for repairing a gate dielectric layer/channel interface, a control unit used for controlling conversion of a semiconductor substrate among all the process cavities and opening/closing of all the process cavities, and a conveying device used for conveying the semiconductor substrate among all the process cavities. By adopting a process for preparing the gate dielectric layer in the equipment provided by the invention, the Si-N bond tends to be stable to prevent the volatilization of N atoms, the N concentration in a SiON gate dielectric is stabilized, the dielectric constant of the SiON gate dielectric is increased, reduction of a carrier mobility caused by interface defect is avoided, and the interface quality and the performance of a device are improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of equipment of preparing gate dielectric layer.
Background technology
The fast development of very lagre scale integrated circuit (VLSIC) (VLSI) and ultra large scale integrated circuit (ULSI), device fabrication technology is proposed to more particular/special requirement, and wherein to enter nanometer era be exactly a significantly challenge to the requirement of gate oxide to MOS device feature size.The preparation technology of gate dielectric layer is the key technology in semiconductor fabrication process, directly affects and determined electrology characteristic and the reliability of device.
The Key Performance Indicator of MOSFET device is drive current, and the size of drive current depends on grid capacitance.Grid capacitance is directly proportional to gate surface is long-pending, is inversely proportional to the thickness of gate dielectric layer.Therefore, amass and reduce gate dielectric layer thickness and all can improve grid capacitance by increasing gate surface, and the thickness of reduction gate dielectric layer just becomes the primary means that advance MOSFET device performance to improve.
But since semiconductor technology enters 45 nanometer era, the simple method that reduces gate dielectric layer thickness of tradition has run into unprecedented challenge.Because in the time of the very thin thickness of gate dielectric layer (<20A), the penetration tunnel mechanism in grid leakage current has played leading role.On the one hand, along with the further reduction of gate dielectric layer thickness, grid leakage current also can increase with exponential form, wherein, the every reduction of gate dielectric layer thickness 2A, grid leakage current will increase by 10 times.On the other hand, between grid, gate dielectric layer and silicon substrate, there is impurity concentration gradient, along with the continuous reduction of gate dielectric layer thickness, the impurity such as the boron mixing in grid can be diffused in silicon substrate or be fixed in gate dielectric layer from grid, this can affect the threshold voltage of device, thereby affects the performance of device.Although increase the effectively diffusion of impurity in suppressor grid leakage current and grid of gate dielectric layer thickness, but transistor drive current, the key performances such as time of delay that overturn also can be had a greatly reduced quality, this drive current and electric leakage of the grid, to the contradiction on gate dielectric layer thickness requirement, cannot be avoided for traditional gate dielectric layer.
The computing formula of grid capacitance is: C=e
0kA/t
Wherein, C=grid capacitance; e
0=aerial permittivity; The dielectric constant of K=material; A=gate surface is long-pending; T=gate dielectric layer thickness
From the computing formula of grid capacitance, we can find out, grid capacitance not only depends on the long-pending and gate dielectric layer thickness of gate surface, also depend on the dielectric constant of gate dielectric layer, and therefore reducing gate dielectric layer thickness is not the unique method that improves grid capacitance.Even if gate dielectric layer thickness remains unchanged, the dielectric coefficient K that improves gate dielectric layer also can reach and reduce equivalent gate medium oxidated layer thickness, and increases the effect of grid capacitance.Therefore the dielectric coefficient K that, how to improve gate dielectric layer becomes the focus of present research.
In present stage, the method that improves the dielectric coefficient of gate dielectric layer roughly has two large classes:
One class is to adopt the material of brand-new high-dielectric coefficient as gate medium, as nitrogen hafnium silicon oxide (HfSiON) etc.But adopt brand-new material to relate to the selection of grid material, the series of process integration problems such as the coupling of lattice constant and exposure etching, the technology development cycle is relatively long, can not meet immediately the active demand of 45 nanometer technologies.Simultaneously brand-new material had larger difference with former technique, the high cost of technology innovation technically.
Another large class is still continued to use SiO
2film is as gate dielectric layer, by SiO
2in film, mix the dielectric coefficient that nitrogen makes it to become fine and close SiON and improve gate dielectric layer.Because traditional Si O
2the K value of gate dielectric layer is 3.9, and pure Si
3n
4k value can reach 7, by doping nitrogen number can realize to SiON gate medium dielectric coefficient regulate, mixing of nitrogen-atoms can also effectively be suppressed the diffusion of the grid doping atoms such as boron in gate medium in addition.Because the method still adopts SiO
2film is as the main body of gate medium, therefore with early stage technology have good continuity and compatibility.
Industry has three kinds of main methods can realize SiO conventionally at present
2nitrogen in film adulterates to form SiON:
First method is at SiO
2in the growth course of film, pass into the nitrogenous gas such as NO, thereby directly mix nitrogen in growth course.But the nitrogen uniformity of this method doping is difficult to control, and can not adapt to the requirement of semiconductor production.
Second method is at SiO
2after film has been grown, adopt at NO/N
2the way doping nitrogen of further annealing in the nitrogenous gas environment such as O.The nitrogen-atoms that this method is mixed easily accumulates in SiO
2the interface of film and raceway groove, thus the migration velocity of charge carrier in raceway groove is had a negative impact.
The third method is at SiO
2after film growth finishes, carry out nitrogen doping by plasma injection technique.The nitrogen atom concentration that the method is mixed is high, in the degree of depth, be mainly distributed in gate dielectric layer upper surface and away from SiO
2/ channel interface is the method for the raising gate dielectric layer dielectric coefficient accepted extensively of current semiconductor industry.Refer to Fig. 1 and Fig. 2, the calcspar of the equipment that Fig. 1 adopts for the existing technique of preparing gate dielectric layer, Fig. 2 is the existing process chart of preparing gate dielectric layer, its concrete technology is made up of three steps:
Step L01: adopt original position steam oxidation technique (ISSG, In-Situ Steam Generation) growth SiO in Technology for Heating Processing chamber
2gate dielectric layer;
Step L02: adopt decoupled plasma nitridation technique (DPN, Decoupled Plasma Nitridation) to SiO in plasma nitridation process chamber
2nitrogen adulterates in gate dielectric layer;
Step L03: adopt high-temperature annealing process (PNA, Post Nitridation Anneal) to stablize Si-N key in high-temperature heat treatment chamber and repair the plasma damage in medium.
In above-mentioned preparation technology, because the nitrogen atom concentration mixing in gate dielectric layer is high and be mainly distributed in the upper surface of gate dielectric layer, therefore the temperature to follow-up PNA technique, atmosphere and the time interval must strict be controlled, to prevent native oxide layer in gate dielectric layer and organic absorption on the nitrogen impact causing of adulterating; In addition, the high-temperature annealing process of PNA (Post Nitridation Anneal) had both easily caused the volatilization of surface nitrogen atom, caused again nitrogen-atoms to obtain energy and continued diffusion, caused part nitrogen-atoms to accumulate in SiO
2/ Si interface, thus the migration velocity of charge carrier in raceway groove is had a negative impact.
Therefore, urgent need will be improved existing gate dielectric layer technique and equipment thereof, thereby prepares the gate dielectric layer with high-k.
Summary of the invention
In order to overcome the problems referred to above, the present invention aims to provide a kind of equipment of preparing gate dielectric layer, thereby avoids causing in preparation technology the loss of the nitrogen-atoms of gate dielectric layer, improves the nitrogen content of gate dielectric layer and the dielectric constant of gate dielectric layer.
The invention provides a kind of equipment of preparing gate dielectric layer, it comprises:
Technology for Heating Processing chamber, for the SiO that grows
2gate dielectric layer;
Plasma nitridation process chamber, thus Si-N key formed for carry out plasma nitrogen injection to gate dielectric layer;
High-temperature ammonolysis process chamber, for repairing lattice damage and the stable Si-N key of gate dielectric layer;
Low-temperature oxidation process chamber, for repairing gate dielectric layer/channel interface;
Control unit, for controlling described the Semiconductor substrate conversion between process cavity and keying of process cavity described in each described in each;
Feeding device, for carrying described Semiconductor substrate described in each between process cavity.
Preferably, described control unit comprises and transports control unit and process cavity control unit
Preferably, described feeding device has trigger equipment, and described trigger equipment sends and carries complete signal to described control unit while arriving in described process cavity for receiving described control unit sends start the signal of carrying and respond to described Semiconductor substrate.
Preferably, described Technology for Heating Processing chamber is rapid thermal anneal process chamber and/or vertical furnace tube process cavity.
Preferably, described rapid thermal anneal process chamber is original position steam oxidation process cavity and/or rapid thermal oxidation process chamber.
Preferably, described pecvd nitride chamber is the nitriding process chamber of decoupled plasma nitridation process chamber and/or remote plasma nitridation process cavity and/or vertical proliferation equipment.
Preferably, high-temperature ammonolysis process chamber is rapid thermal anneal process chamber.
Preferably, described low-temperature oxidation process chamber is rapid thermal anneal process chamber.
The invention provides a kind of equipment of preparing gate dielectric layer, than the existing equipment of preparing gate dielectric layer, improve high-temperature annealing process, high-temperature ammonolysis process chamber and low-temperature oxidation process chamber are increased, by carry out the high-temperature ammonolysis treatment process under pure inert gas in high-temperature ammonolysis treatment chamber, repair lattice damage and stable Si-N key in gate dielectric layer, avoided the disappearance of the nitrogen-atoms in gate dielectric layer; By carry out the low-temperature oxidation treatment process under oxidizing gas in low-temperature oxidation process chamber, can repair gate dielectric layer/channel interface, reduce boundary defect, improve carrier mobility, further improve the dielectric constant of gate dielectric layer.
Brief description of the drawings
The calcspar of the equipment that Fig. 1 adopts for the existing technique of preparing gate dielectric layer
Fig. 2 is the existing process chart of preparing gate dielectric layer
Fig. 3 is the calcspar of the equipment of preparing gate dielectric layer of a preferred embodiment of the present invention
Fig. 4 is the process chart of preparing gate dielectric layer of a preferred embodiment of the present invention
Embodiment
The embodiment that embodies feature & benefits of the present invention will describe in detail in the explanation of back segment.Be understood that the present invention can have various variations in different examples, it neither departs from the scope of the present invention, and explanation wherein and be shown in the use that ought explain in essence, but not in order to limit the present invention.
Below in conjunction with accompanying drawing 3-4, the equipment of the present invention being prepared to gate dielectric layer by specific embodiment is described in further detail.It should be noted that, accompanying drawing all adopts very the form simplified, uses non-ratio accurately, and only in order to object convenient, that reach lucidly the aid illustration embodiment of the present invention.
As previously mentioned, traditional equipment of preparing gate dielectric layer comprises the Technology for Heating Processing chamber that adopts ISSG technique growth gate medium, the plasma nitridation process chamber that adopts DPN technique to carry out nitrogen doping, and adopt high-temperature annealing process to stablize the high-temperature heat treatment chamber of Si-N key, because can causing the volatilization of nitrogen-atoms and the nitrogen of gate dielectric layer/channel interface, high-temperature thermal annealing technique gathers, the dielectric constant of gate dielectric layer and the electrical property of device are seriously reduced, therefore, the present invention has improved employing high-temperature heat treatment chamber and has carried out this processing step of high-temperature annealing process, be divided into two technical processs, first under pure inert gas, carry out high-temperature ammonolysis treatment process for the stable Si-N key forming, thereby make in SiON gate medium, to there is stable nitrogen content, improve the dielectric constant of SiON gate medium, under oxidizing gas, carry out again low-temperature oxidation processing, for repairing SiON gate medium and channel interface, reduced nitrogen-atoms the gathering of this interface, thereby reduced the negative effect to carrier mobility speed in raceway groove.Thus, the present invention, aspect the nitrogen content of stablizing in gate dielectric layer, has introduced high-temperature ammonolysis process chamber and low-temperature oxidation process chamber, guarantees the realization of above-mentioned technique.
Refer to Fig. 3, Fig. 3 is the calcspar of the equipment of preparing gate dielectric layer of a preferred embodiment of the present invention.The equipment of preparing gate dielectric layer of the present embodiment of the present invention comprises:
Technology for Heating Processing chamber, for the SiO that grows
2gate dielectric layer;
Plasma nitridation process chamber, thus Si-N key formed for carry out plasma nitrogen injection to described gate dielectric layer;
High-temperature ammonolysis process chamber, for repairing the lattice damage of described gate dielectric layer and stablizing described Si-N key;
Low-temperature oxidation process chamber, for repairing gate dielectric layer/channel interface.
Concrete, in the present embodiment, gate medium growth chamber can be rapid thermal annealing (RTP, Rapid Thermal Process) process cavity and/or vertical furnace tube (Furnace) process cavity, the growth that is to say gate medium can adopt RTP technique to grow in RTP process cavity, also can in Furnace process cavity, adopt Furnace technique to grow, can also in RTP and these two process cavity of Furnace, adopt respectively RTP and these two techniques of Furnace to grow.Preferably, RTP process cavity is original position steam oxidation (ISSG, In-Situ Steam Generation) process cavity and/or rapid thermal oxidation (RTO, Rapid Thermal Oxidation) process cavity, like this, can in ISSG process cavity, adopt the ISSG technique gate medium of growing, also can in RTO process cavity, adopt the RTO technique gate medium of growing, can also in ISSG and these two process cavity of RTO, adopt respectively ISSG and RTO technique to grow.
In the present embodiment, plasma nitridation process chamber can be decoupled plasma nitridation (DPN, Decoupled Plasma Nitridation) the nitriding process chamber of process cavity and/or remote plasma nitridation (RPN, Remote Plasma Nitridation) process cavity and/or vertical proliferation equipment.These three process cavity can be used separately, also can use together between two, can also three uses together.
High-temperature ammonolysis process chamber in the present embodiment is rapid thermal anneal process chamber, can in rapid thermal anneal process chamber, adopt pure inert gas, and gate medium is carried out to high-temperature ammonolysis treatment process;
Low-temperature oxidation process chamber in the present embodiment is rapid thermal anneal process chamber, can in rapid thermal anneal process chamber, adopt oxidizing gas, and gate medium is carried out to low-temperature oxidation treatment process.
Also there is in the present embodiment control unit, can control the conversion of Semiconductor substrate between each process cavity and the keying of each process cavity by control program.Specifically, in the present embodiment, control unit can comprise and transports control unit and process cavity control unit.Process cavity control unit can be controlled the time of each technical process, after the reaction in a process cavity completes, process cavity control unit is opened this process cavity, and transporting control unit sends and starts to carry signal to the device that transports Semiconductor substrate, feeding device takes out Semiconductor substrate after receiving signal from this process cavity, then process cavity control unit sends shutdown signal to this process cavity, simultaneously, feeding device is transported in next process cavity, process cavity control unit sends start signal to the process cavity of next technique, next process cavity is opened, when Semiconductor substrate enters after next process cavity, feeding device sends the complete signal of conveying to transporting control unit, the next process cavity of process cavity control unit control is started working, so go down to complete the technical process of four process cavity.
Certainly, the feeding device here can have the trigger equipment that sends signal and reception signal to control unit, trigger equipment can sense that Semiconductor substrate arrives the relevant position in process cavity, send and carry complete signal to control unit simultaneously, making control unit open the process cavity power supply that will react starts working, such as the semiconductor in Semiconductor substrate arrives process cavity sinks to the bottom after brace table, trigger equipment sends and carries complete signal to control unit.And after reaction finishes, the signal that the conveying that trigger equipment is sent for reception control unit is opened, trigger equipment control feeding device starts to transport Semiconductor substrate.
The feeding device here can be that four process cavity are total, also can each process cavity all have feeding device separately, and the present invention is not restricted this.
Certainly,, in the present invention, also can, by manually realizing the conversion of Semiconductor substrate between each process cavity and the keying of each process cavity, like this, in other preferred embodiment, also can not contain control unit, conveying device and trigger equipment.
Next, in order further to annotate the present invention, to the method that adopt equipment of the present invention to prepare gate dielectric layer be explained by an embodiment, refer to Fig. 4, Fig. 4 is the process chart of preparing gate dielectric layer of a preferred embodiment of the present invention, in the present embodiment, adopt the above-mentioned equipment of preparing gate dielectric layer to carry out the preparation of gate dielectric layer, comprise the following steps:
Step S01: in Technology for Heating Processing chamber, adopt thermal oxidation and Technology for Heating Processing to form SiO at semiconductor substrate surface
2gate medium;
Concrete, in the present embodiment, thermal oxidation and Technology for Heating Processing can be, but not limited to adopt rapid thermal anneal process and/or vertical furnace tube technique, for example, can only adopt rapid thermal anneal process (RTP, Rapid Thermal Process), can also only adopt vertical furnace tube technique (Furnace), can also adopt these two techniques of RTP and Furnace.
In the present embodiment, RTP technique can be, but not limited to as original position steam oxidation technique (ISSG, In-Situ Steam Generation) and/or rapid thermal oxidation process (RTO, Rapid Thermal Oxidation), for example, can only adopt ISSG technique, can also only adopt RTO technique, can also adopt these two techniques of ISSG and RTO.
In the present embodiment, ISSG technique can be, but not limited to as N
2o ISSG technique and/or O
2iSSG technique, wherein, N
2o ISSG process using N
2o and H
2as reacting gas, O
2iSSG process using O
2and H
2as reacting gas.For example, can only adopt N
2o original position steam oxidation technique, also can only adopt O
2original position steam oxidation technique, can also adopt N
2o original position steam oxidation technique and O
2these two techniques of original position steam oxidation technique.
It should be noted that, in the present invention, thermal oxidation and Technology for Heating Processing can complete in a technical process, for example, in single RTP or Furnace technique, complete; Also can first carry out thermal oxidation technology, then heat-treat technique, for example, first adopt RTP technique to complete thermal oxidation technology, then adopt Furnace technique to complete Technology for Heating Processing.
Thermal oxidation in the present invention and the technological parameter of Technology for Heating Processing are such as temperature, reacting gas, reaction pressure, power etc. can be set according to actual technological requirement, and the present invention does not impose any restrictions this.
In the present embodiment, the SiO that adopts above-mentioned technical process to form in Semiconductor substrate
2the stable chemical nature of gate medium, and even thickness, the size of this thickness can require to set according to actual process.
Step S02: in plasma nitridation process chamber, using plasma nitriding process is to SiO
2gate medium carries out the doping of nitrogen, thereby makes SiO
2gate medium becomes SiON gate medium;
Concrete, in the present embodiment, nitriding process can be, but not limited to as decoupled plasma nitridation process (DPN, Decoupled Plasma Nitridation), remote plasma nitridation technique (RPN, RemotePlasma Nitridation) and/or the nitriding process of vertical proliferation equipment, for example, can only adopt DPN technique, also RPN technique can be only adopted, the nitriding process of vertical proliferation equipment can also be only adopted.
In the present embodiment, the gas that the nitriding process of vertical proliferation equipment adopts can be, but not limited to comprise NO, N
2o or NH
3.
The technological parameter of the plasma nitridation process in the present invention is such as temperature, reacting gas, reaction pressure, power etc. can be set according to actual technological requirement, and the present invention does not impose any restrictions this.
In plasma nitridation process, the part O atom in SiO2 is replaced and forms Si-N key by N atom, thereby makes SiO2 gate medium become SiN gate medium; After nitriding process finishes, SiN gate medium has certain nitrogen concentration, and the size of nitrogen concentration can be required to set by actual process.
Step S03: in high-temperature ammonolysis process chamber, adopt pure inert gas, SiON gate medium is carried out to high-temperature ammonolysis processing, the temperature adopting is not less than 1000 DEG C;
Concrete, in the present embodiment, the temperature of high-temperature ammonolysis processing can be, but not limited to as 1000-1100 DEG C, the high-temperature ammonolysis processing time can be, but not limited to the second into 5-120, pure inert gas can only have a kind of inert gas, also can be mixed inert gas, in the present embodiment, pure inert gas can be, but not limited to as N
2, Ar a kind of or its mixture.
Here, under the environment of pure inert gas, carry out in the process of high-temperature ammonolysis processing, pure inert gas can avoid the N atom in Si-N key to be substituted by O atom, under the condition of pure inert gas and high-temperature-phase combination, can repair the lattice damage that above-mentioned plasma nitrogen doping process causes gate medium, Si-N key is tended towards stability, thereby can stablize the nitrogen concentration in the SiN gate medium forming in above-mentioned steps S02, avoid at high temperature N volatilization and cause reducing of nitrogen concentration, like this, with respect to the technique of not carrying out high-temperature ammonolysis processing in pure inert gas of routine, high-temperature ammonolysis treatment process of the present invention can be avoided the loss of nitrogen, thereby improve the dielectric constant of the SiN gate medium forming.
Certainly, in this high-temperature ammonolysis processing procedure, nitrogen-atoms inevitably can move to the interface of gate medium and raceway groove, and produce and gather in this interface, interface nitrogen-atoms gather the decline that can cause channel carrier mobility, therefore, in subsequent technique process of the present invention, need carry out repair process to this interface, to reduce gathering of nitrogen-atoms.
Step S04: in low-temperature oxidation process chamber, adopt oxidizing gas, SiON gate medium is carried out to low-temperature oxidation processing, the temperature adopting is not higher than 800 DEG C.
Concrete, in the present embodiment, it is 500 DEG C-800 DEG C that the temperature of low-temperature oxidation processing can be, but not limited to, and the processing time can be, but not limited to the second into 5-120, and the oxidizing gas adopting can be, but not limited to as O
2, or N
2o and H
2mist, or H
2with O
2mist
Here, in low-temperature oxidation processing procedure, in low temperature environment, oxidizing gas does not have enough energy that the N in gate medium is cemented out, and oxidizing gas can be replaced the nitrogen-atoms at gate medium and channel interface place, thereby the defect of reparation interface improves interface quality, like this, can further improve the dielectric constant of gate medium.
In sum, the equipment and process of preparing gate dielectric layer of the present invention, improve traditional high-temperature annealing process, being divided into two technical processs is high-temperature ammonolysis processing procedure and low-temperature oxidation processing procedure, adopt high-temperature ammonolysis process chamber and low temperature nitrogenize process chamber to carry out high-temperature ammonolysis treatment process and low-temperature oxidation treatment process, by pure inert gas and hot environment are combined, the SiON gate medium forming is carried out to nitrogen treatment, Si-N key is tended towards stability, avoid the volatilization of N atom, stablize the N concentration in SiON gate medium, improve the dielectric constant of SiON gate medium, again by low-temperature oxidation processing procedure, at low temperatures, utilize oxidizing gas to repair the defect at gate medium and channel interface place, avoided the decline of the carrier mobility that boundary defect causes, improve interface quality, further improved the dielectric constant of SiON gate medium, and method of the present invention, with respect to conventional high-temperature process, has reduced complex operation degree, has improved process efficiency.
Above-described is only embodiments of the invention; described embodiment is not in order to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (8)
1. an equipment of preparing gate dielectric layer, is characterized in that, comprising:
Technology for Heating Processing chamber, for the SiO that grows
2gate dielectric layer;
Plasma nitridation process chamber, thus Si-N key formed for carry out plasma nitrogen injection to described gate dielectric layer;
High-temperature ammonolysis process chamber, for repairing the lattice damage of described gate dielectric layer and stablizing described Si-N key;
Low-temperature oxidation process chamber, for repairing gate dielectric layer/channel interface;
Control unit, for controlling described the Semiconductor substrate conversion between process cavity and keying of process cavity described in each described in each;
Feeding device, for carrying described Semiconductor substrate described in each between process cavity.
2. the equipment of preparing gate dielectric layer according to claim 1, is characterized in that, described control unit comprises and transports control unit and process cavity control unit.
3. the equipment of preparing gate dielectric layer according to claim 1, it is characterized in that, described feeding device has trigger equipment, and described trigger equipment sends and carries complete signal to described control unit while arriving in described process cavity for receiving described control unit sends start the signal of carrying and respond to described Semiconductor substrate.
4. the equipment of preparing gate dielectric layer according to claim 1, is characterized in that, described Technology for Heating Processing chamber is rapid thermal anneal process chamber and/or vertical furnace tube process cavity.
5. the equipment of preparing gate dielectric layer according to claim 4, is characterized in that, described rapid thermal anneal process chamber is original position steam oxidation process cavity and/or rapid thermal oxidation process chamber.
6. the equipment of preparing gate dielectric layer according to claim 1, is characterized in that, described pecvd nitride chamber is the nitriding process chamber of decoupled plasma nitridation process chamber and/or remote plasma nitridation process cavity and/or vertical proliferation equipment.
7. the equipment of preparing gate dielectric layer according to claim 1, is characterized in that, high-temperature ammonolysis process chamber is rapid thermal anneal process chamber.
8. the equipment of preparing gate dielectric layer according to claim 1, is characterized in that, described low-temperature oxidation process chamber is rapid thermal anneal process chamber.
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| CN110047755A (en) * | 2018-01-17 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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