CN103853642A - Injection type simulation system for infrared digital image based on USB3.0 and method thereof - Google Patents

Abstract

The invention discloses an injection type simulation system for an infrared digital image based on USB3.0 and a method thereof. The injection type simulation system is mainly used for supplying a simulation environment to a real-time signal processing platform for an infrared image. The injection type simulation system comprises a host computer with a USB3.0 interface and an injection type simulator for the infrared digital image, wherein the injection type simulator further comprises a USB3.0 controller chip, an FPGA (Field Programmable Gate Array), a DDR2SDRAM and a peripheral equipment interface. An injection type simulation method for the system comprises the following steps: 1) configuring the USB3.0 controller chip into a Slave FIFO mode and establishing a DMA (Direct Memory Access) transmission channel; 2) utilizing an image data receiving module established in the FPGA to read data from the Slave FIFO; 3) utilizing an image data caching module established in the FPGA to read and write DDR2SDRAM, so as to realize the caching of the data; 4) utilizing three different interface modes to send the data to a rear-stage platform. The injection type simulation system provided by the invention has the advantages that the latest USB3.0 protocol is adopted, the data transfer rate is high, the instantaneity is excellent and the portability is strong.

Description

Infrared digital image injected simulation system and method based on USB3.0

Technical field:

The present invention relates to infrared digital image injected simulation technology, is a kind of infrared injected simulation system and method for the high speed data transfer based on USB3.0 specifically, and it is mainly used in providing simulated environment for infrared image real time signal processing platform.

Background technology:

Infrared electro imaging detection equipment is normally made up of infrared imaging sensor and realtime graphic signal processing platform two parts.The main task of realtime graphic signal processing platform is that the picture signal that infrared imaging sensor is sended over is carried out analyzing and processing, utilizes corresponding algorithm from complex background, to detect specific objective, and target is followed the tracks of or identified.The performance quality of infrared electro imaging detection equipment depends on the situation that realizes of target detection and track algorithm to a great extent, needs repeatedly to verify in development process.Just because of this, the design of various l-G simulation tests and analogue system has just been arisen at the historic moment.

L-G simulation test mainly contains two types, the emulation of digital signal injection formula and hardware-in-the-loop simulation.The former spends low and dirigibility is high.Traditional infrared injected simulation system is generally based on USB2.0 interface or pci bus.The bus transfer rate that USB2.0 is the highest can reach 60MByte/s, but considers that protocol overhead, data send the factors such as process priority, find to reach the average transmission rate of 20MByte/s in actual use procedure.A frame infrared simulation image that is 320x256 for image resolution ratio, if data precision is 14-bit, is subject to the restriction of USB2.0 message transmission rate so, and frame frequency can only reach the level of 100 frames/s; More seriously, if the infrared electro imaging detection equipment that coordinates some large battle arrays, multiband to survey, its each frame panoramic picture size of data has just reached about 21.75MByte, and after requiring in conjunction with actual frame frequency, average data transfer rate is not less than 30MByte/s.Therefore, the transmission bandwidth of USB2.0 bus is to meet infrared digital image injected simulation system at a high speed.

PCI is the one-level local bus standard between CPU and system bus, and its transfer rate is higher than USB2.0.Up-to-date PCI-E bus standard is advanced by leaps and bounds especially in transfer rate, adopt point-to-point mode connected in series, regulation bus can have the plurality of specifications of 1～32 passage, and the one-way transmission speed of each passage can reach 2.5Gbit/s, can meet the requirement of high-speed transfer.But pci bus is not supported hot plug, be also unfavorable for making portable set, application popularization degree is so extensive far away from USB interface.

Therefore designing one, can to realize the infrared digital image injected simulation system that high speed data transfer, volume are small and exquisite, portable strong very necessary.Within 2008, new USB3.0 agreement is formulated and is issued, and supports the commercial controller of this agreement and interface chip also to release the second half year in 2009.New Deal regulation computing machine can be communicated by letter with the transfer rate of 5Gbit/s under hypervelocity pattern with peripherals, is 10 times under USB2.0 fast mode, is applicable to very much the high-speed transfer requirement of infrared injected simulation system.Meanwhile, utilize the design of FPGA as interface controller and sdram controller, the feature that can give full play to FPGA can repeated configuration, real-time control performance is good, reasonably dividing data Switching Module and sequential logic control module in the time of programming.

Summary of the invention:

The object of the present invention is to provide a kind of infrared digital image injected simulation system and method based on USB3.0, solve the problem that infrared injected simulation message transmission rate is low, real-time is poor.

For achieving the above object, hardware platform of the present invention mainly comprises main frame and infrared digital image injected simulation device.

Each hardware composition part need to meet: described main frame has USB3.0 interface.Described infrared digital image injected simulation device comprises a slice USB3.0 controller chip, a slice FPGA, a slice DDR2SDRAM and peripheral interface.Described USB3.0 controller chip has the USB3.0 interface of a connection main frame, is connected the GPIF II interface of external unit with one.Described FPGA has Memory Controller module (MCB).Described DDR2SDRAM has 1Gbit memory capacity and 16 bit data bus.Described peripheral interface has the interface matching with the infrared image real time signal processing platform of rear class.

The annexation of each hardware composition part is: between main frame and infrared digital image injected simulation device, connect by USB3.0 transmission cable; Between injected simulation device and infrared image real time signal processing platform, connect by peripheral interface.

The flow process of the infrared injected simulation of specific implementation of the present invention is as follows:

Step 1: by Design of Firmware, USB3.0 controller chip is configured to the pattern from device FIFO (Slave FIFO), sets up a DMA transmission channel;

Step 2: main frame by USB3.0 interface by infrared simulation view data send to USB3.0 controller chip from device FIFO (Slave FIFO);

Step 3: utilize the view data receiver module in FPGA to read incessantly the data that main frame sends over from device FIFO (Slave FIFO), and carry out buffer memory in input FIFO buffer cell;

Step 4: the data that receive in input FIFO buffer cell are write in DDR2SDRAM by the SDRAM control module in the built-in view data cache module of FPGA;

Step 5:SDRAM control module reads back the infrared simulation view data being buffered in DDR2SDRAM write in output FIFO buffer cell;

Step 6: by the reading out data from output FIFO buffer cell of the view data sending module in FPGA, send data by the peripheral interface matching with rear class infrared image real time signal processing platform.

Distinguishing feature of the present invention be following some:

(1) message transmission rate is high, and real-time is good.USB3.0 supports the transfer rate of 5Gbit/s under hypervelocity pattern, can meet the simulation requirements of infrared image real time signal processing platform in most cases.Utilize inner abundant block storage (Block RAM) resource of FPGA to generate input, output FIFO buffer cell, coordinate the DDR2SDRAM of high-speed high capacity, can tackle continuous batch read-write and the burst read-write of big data quantity, for high-speed transfer provides data buffer storage guarantee, realize the continuous free of discontinuities of output infrared simulation image.

(2) Programmable Design, dirigibility is high.As the core component of infrared digital image injected simulation device, utilize FPGA to come design data Switching Module and sequential logic control module, give full play to FPGA able to programme can repeated configuration, feature that capability of sequential control is strong.Meanwhile, selected USB3.0 controller chip, based on ARM9 kernel, provides a high performance universal programmable interface GPIF II, has 256 kinds of firmware programmable state, can flexible configuration become different patterns.

(3) scheme of employing Module Division, according to data flow direction, FPGA Programming is divided into view data receiver module, cache module and sending module etc., relatively independently between modules connect each other again, can realize by sub-module substep in the specific implementation, orderliness is clear, be convenient to programming, and the reusability of module is good.

(4) provide abundant interface resource, can, according to the desired interface mode of infrared image real time signal processing platform of rear class by the output of infrared simulation view data, match with existing equipment platform.

(5) volume is small and exquisite, portable strong.Whole infrared digital image injected simulation device concentrates on a board, has greatly reduced the volume and weight of system, is easy to carry, and is conducive to carry out ambulant site test.

Accompanying drawing explanation

Fig. 1 is the system chart of the infrared digital image injected simulation system based on USB3.0.

Fig. 2 is that USB3.0 controller chip is at the DMA transmission channel structural drawing building from device FIFO (Slave FIFO) pattern.

Fig. 3 is the process flow diagram of the infrared digital image injected simulation based on USB3.0.

Embodiment:

With reference to the accompanying drawings the specific embodiment of the present invention is described in further detail below.

Fig. 1 is the system chart of the infrared digital image injected simulation system based on USB3.0.

Hardware platform of the present invention is: a main frame, a slice USB3.0 controller chip, a slice FPGA, a slice DDR2SDRAM and peripheral interface.

Described main frame has USB3.0 interface, and host memory contains the infrared picture data that actual field trial obtains, and infrared digital image injected simulation device driver is installed.

Described USB3.0 controller chip has been selected the CYUSB3014 chip of Cypress company.This chip meets USB3.0 standard, and the usb protocol of backward compatible lowest version.Its inner integrated 32 ARM926EJ-S processor cores, core work frequency is 200MHz, data-handling capacity is very powerful.CYUSB3014 has the GPIF II interface that can realize 5Gbit/s transfer rate, can be connected with any processor, ASIC or FPGA by this interface, the high workload clock of interface can reach 100MHz, supports 8,16,32 bit parallel data buss.The SRAM of the embedded 512KByte capacity of CYUSB3014 comes storage code and data, mainly configures and manage the data transmission between USB3.0 interface and GPIF II interface by firmware program and inner DMA passage.

Described FPGA has selected the XC6SLX45FGG484 of the Spartan-6 of Xilinx company series.This model FPGA has abundant logical resource, uses SPI mode to configure, and maximum user I/O mouth reaches 358.The block storage (Block RAM) of inner total 2088Kbit, can be used for building FIFO buffer cell, and also have 2 Memory Controller modules (MCB), can control easily outside DDR2SDRAM, utilize these resources to realize the buffer memory of data, guarantee high speed data transfer.

Described DDR2SDRAM chip has been selected the MT47H64M16HR of Micron company, and this model DDR2SDRAM total volume is 1Gbit, and speed is the highest can reach 12.8Gbit/s in read-write.Consider that data input and output are to share bandwidth, the one direction read-write speed after reducing by half has still exceeded the transfer rate of USB3.0, can provide buffer memory for high speed data transfer, can not cause bottleneck.

Described peripheral interface comprises Camera Link interface, optical fiber interface and LVDS interface.

Described Camera Link interface selects DS90CR287MTD to realize output function, and whole transmission information comprises 14 bit data signals and 4 digital video control signals.Wherein video control signal comprises frame synchronizing signal (FVAL), line synchronizing signal (LVAL), data useful signal (DVAL) and pixel clock signal (CLOCK).

Described optical fiber interface comprises an optical fiber connector HFBR-5208 and a slice parallel-serial conversion chip MAX9217.FPGA sends fiber data by inner optical fiber interface control module control MAX9217.

Described LVDS interface direct connects in succession 3 pairs of difference I/O pins of FPGA and exports as difference.Select pin type DB9 socket as connector.

The maximum data transfer rate that three kinds of interfaces of described this are supported, all lower than 5Gbit/s, is utilized USB3.0 can meet infrared simulation view data as data transmission interface and is injected into the requirement in rear class equipment by above-mentioned three kinds of interfaces.

Fig. 2 is that USB3.0 controller chip is at the DMA transmission channel structural drawing building from device FIFO (Slave FIFO) pattern.

USB3.0 controller chip is to have USB3.0 interface and GPIF II interface simultaneously.Wherein, USB3.0 interface is responsible for connecting main frame, and GPIF II interface is responsible for connecting FPGA.From device FIFO (Slave FIFO) pattern, endpoint is only present in this side of USB3.0 interface, from the angle of main frame, according to the difference of data transfer direction, can be divided into producer endpoint and consumer endpoint.Specifically be applied in the present invention, use be producer endpoint.

Set up a DMA transmission channel, also need two socket that are positioned at passage two ends realize data inflow and flow out.According to the difference of data transfer direction, these two socket are also divided into producer socket and consumer socket.Finally, the 2-bit address wire being connected with FPGA by change USB3.0 controller chip is selected a specific thread, the DMA transmission channel that will set up is mapped to this thread upper, this whole piece is positioned at the data transmission link of chip and has just successfully set up.For a DMA transmission channel that success is set up, realize endpoint, socket and the corresponding mapping relations of thread thereby be connected with external hardware by user-defined Design of Firmware.

Fig. 3 is the process flow diagram of the infrared digital image injected simulation based on USB3.0.

DMA transmission channel set up after, main frame just can by the control of upper computer software by infrared simulation view data send to USB3.0 controller chip from device FIFO (Slave FIFO).Then utilize the view data receiver module in FPGA to read incessantly the data that main frame sends over from device FIFO (Slave FIFO), and carry out buffer memory in input FIFO buffer cell.FPGA adopts 16-bit data bus to be connected with GPIF II interface, according to the sequential requirement from the synchronous read operation of device FIFO (Slave FIFO), the efficient clock that the level height of the control signal such as SLRD, SLOE in GPIF II interface must be unified in PCLK is along variation.Therefore the present invention is by the global clock signal output of FPGA, as the PCLK clock signal of USB3.0 controller chip.

FPGA is to be also connected by 16-bit data bus with DDR2SDRAM.Can utilize embedded Memory Controller module (MCB) resource of FPGA to realize the function of SDRAM control module.Memory Controller module (MCB) is configured to 2 subscriber channels, and one of them is for writing the data of input FIFO buffer cell in DDR2SDRAM, and another is for reading data from DDR2SDRAM.Control module is also exported sky/full signal of DDR2SDRAM, shows wherein to have or not data, so that peripheral routine control.And view data cache module is introduced arbitration mechanism, in judgement in the time only having there is the transformation task of single small data quantity, and output FIFO buffer cell can directly obtain data from input FIFO buffer cell, and idle DDR2SDRAM is empty, fully optimizes resource.In the time facing the high speed data transfer of continuous batch, then reactivate DDR2SDRAM and serve as buffer memory.

View data sending module is reading out data from output FIFO buffer cell, sends to rear class infrared image real time signal processing platform, and requires to be configured according to the distinct interface of rear class platform.LVDS interface direct connects in succession 3 pairs of difference I/O pins of FPGA and exports as difference, and wherein a pair of transmission is differential clock signal.Camera Link interface and optical fiber interface common data bus.Use the pixel clock signal (CLOCK) of Camera Link interface as the clock signal of optical fiber interface, line synchronizing signal (LVAL) is as the data inputs enable signals (DE_IN) of optical fiber interface, and by frame synchronizing signal (FVAL) and data useful signal (DVAL) be connected to optical fiber interface data line the highest 2 with minimum 2 of control line.Therefore, view data sending module can be according to the different requirements of rear class platform in practical application, select the one output infrared simulation image in Camera Link interface, optical fiber interface or LVDS interface, or in using the output of Camera Link interface, by the infrared simulation image of optical fiber interface output same number of frames form.

Claims (2)

1. the infrared digital image injected simulation system based on USB3.0, it comprises main frame and infrared digital image injected simulation device, it is characterized in that:

Described main frame is the computing machine with USB3.0 interface;

Described infrared digital image injected simulation device comprises a slice USB3.0 controller chip, a slice FPGA, a slice DDR2SDRAM and peripheral interface; Wherein, described USB3.0 controller chip has the USB3.0 interface of a connection main frame, is connected the GPIF II interface of external unit with one; Described FPGA has Memory Controller module; Described DDR2SDRAM has 1Gbit memory capacity and 16 bit data bus; Described peripheral interface has the interface matching with the infrared image real time signal processing platform of rear class;

Between main frame and infrared digital image injected simulation device, connect by USB3.0 transmission cable; Between injected simulation device and infrared image real time signal processing platform, connect by peripheral interface.

2. the infrared digital image injected simulation method based on system described in claim 1, is characterized in that comprising the following steps:

Step 1: by Design of Firmware, USB3.0 controller chip is configured to from device fifo mode, sets up a DMA transmission channel;

Step 2: main frame by USB3.0 interface by infrared simulation view data send to USB3.0 controller chip from device FIFO;

Step 3: utilize the view data receiver module in FPGA to read incessantly the data that main frame sends over from device FIFO, and carry out buffer memory in input FIFO buffer cell;

Step 4: the data that receive in input FIFO buffer cell are write in DDR2SDRAM by the SDRAM control module in the built-in view data cache module of FPGA;

Step 5:SDRAM control module reads back the infrared simulation view data being buffered in DDR2SDRAM write in output FIFO buffer cell;

Step 6: by the reading out data from output FIFO buffer cell of the view data sending module in FPGA, send data by the peripheral interface matching with rear class infrared image real time signal processing platform.

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