CN103841633B

CN103841633B - A kind of TD LTE auto gain control methods and equipment

Info

Publication number: CN103841633B
Application number: CN201210490955.0A
Authority: CN
Inventors: 唐凯; 谢宁; 谢一宁; 李焱
Original assignee: ZTE Corp
Current assignee: Sanechips Technology Co Ltd
Priority date: 2012-11-27
Filing date: 2012-11-27
Publication date: 2017-08-08
Anticipated expiration: 2032-11-27
Also published as: CN103841633A; WO2014082504A1

Abstract

The invention provides a kind of TD LTE auto gain control methods, respectively frequency point scanning and main synchronizing symbol SS detection-phases in units of frame length, auxiliary synchronizing symbol SSS detection and PBCH read the stage in units of field length, downlink traffic channel receive the stage in units of subframe length, the mean power to respective symbol in each TD LTE frames is calculated；Respectively by the mean power and the upper limit of the power and/or the lower limit of the power, first object performance number, the second target power value comparison, draw the most reasonable power gain control value in each stage；Present invention also offers a kind of TD LTE automatic gain control apparatus；The present invention has distinguished the environmental quality of three phases, improves the flexibility of Power Control.

Description

TD-LTE automatic gain control method and device

Technical Field

The invention relates to a Long Term Evolution (LTE) wireless communication technology, in particular to an Automatic Gain Control (AGC) method and equipment for Time Division Long Term Evolution (TD-LTE).

Background

LTE is an evolution of the Third Generation (3G) mobile communication system, and core technologies such as Orthogonal Frequency Division Multiplexing (OFDM) technology and Multiple-Input Multiple-output (MIMO) technology are used as quasi 4G technologies. The LTE system can provide the peak rates of 100Mbps downlink and 50Mbps uplink under the frequency spectrum bandwidth of 20MHz, can improve the performance of cell edge users, and can improve the cell capacity.

Currently, the LTE system includes TD-LTE and frequency division duplex Long Term evolution (FDD-LTE), and TD-LTE can use the same frequency point for data transmission in uplink and downlink, so that frequency band resources can be saved, and is more favored by researchers.

In the TD-LTE system, one TD-LTE frame is 10ms, and can be divided into two half-frames of 5ms, each half-frame of 5ms can be composed of 5 subframes of 1ms, and each subframe of 1ms has a uniquely identified frame number.

In the prior art, the TD-LTE downlink signal processing process includes the following three stages: a frequency point scanning and Primary Synchronization Signal (PSS) detection stage, a Secondary Synchronization Signal (SSS) detection and Physical Broadcast Channel (PBCH) reading stage, and a downlink traffic Channel receiving stage; the frequency point scanning is mainly used for scanning the signal power average value, the power maximum value and the power minimum value in the main diversity antenna and checking interference signals, the PSS detects and determines the position of a PSS symbol in the TD-LTE half frame length through checking the interference signals, and at the moment, the UE can know 5ms synchronization information; SSS detection is used for determining the position of an SSS symbol in a frame length, at the moment, the UE can know 10ms synchronization information, and meanwhile, the PBCH can read TD-LTE frame number synchronization information; the 5ms synchronization information, the 10ms synchronization information and the frame number synchronization information are integrated into TD-LTE downlink synchronization information, and the frame synchronization information enables User Equipment (UE) to smoothly receive a signal issued by a base station through a downlink traffic channel.

In the three stages, the signals transmitted by the base station are processed layer by layer, so that the interference can be inevitably added, the strength of the signals is further weakened, and a certain power control method is introduced in the three stages for ensuring that the signals transmitted by the base station can successfully reach the UE. In the prior art, the conventional means is to introduce the same power control method into each stage respectively to ensure the stability of the signal strength, but neglects the characteristics of the environment where the signals of the three stages are located, so that it is not flexible to apply the same power control method to the three different stages, and thus a power control method which can be flexibly applied to the three stages is urgently needed.

Disclosure of Invention

In view of the above, the present invention provides a TD-LTE automatic gain control method and device, which can solve the problem of inflexible power control method in the prior art.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

the invention provides a TD-LTE automatic gain control method, which comprises the following steps:

calculating the average power of corresponding symbols in each TD-LTE frame by taking the frame length as a unit in a frequency point scanning and primary synchronization symbol PSS detection stage, taking the half frame length as a unit in an auxiliary synchronization symbol SSS detection and physical broadcast channel PBCH reading stage and taking the subframe length as a unit in a downlink service channel receiving stage respectively; and respectively comparing the average power with the upper power limit and/or the lower power limit, the first target power value and the second target power value to obtain the most reasonable power gain control value of each stage.

In the above scheme, in the stage of the frequency point scanning and the PSS detection, the method includes:

calculating the average power value of each symbol of the current TD-LTE frame by taking the length of the 10ms frame as a unit, determining the maximum average power value, comparing the maximum average power value with the upper power limit and/or the lower power limit, and outputting the power gain control value of the current TD-LTE frame at the current stage to an SSS detection and PBCH reading stage or processing the next TD-LTE frame according to the comparison result.

In the foregoing solution, in the SSS detection and PBCH reading phase, the method includes:

receiving a power gain control value, calculating the average power values of a PSS symbol and a SSS symbol of the current half frame by taking the 5ms half frame length of the TD-LTE frame as a unit, comparing the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with a first target power value, updating and outputting the power gain control value of the current half frame at the current stage to a downlink service channel receiving stage according to the comparison result, and simultaneously processing the next half frame or processing the next half frame.

In the above scheme, in the downlink traffic channel receiving stage, the method includes:

and receiving the power gain control value, calculating the RS symbol average power value of the current subframe by taking the 1ms subframe length of the TD-LTE frame as a unit, comparing the calculated RS symbol average power value of the current subframe with a second target power value, updating the power gain control value of the current subframe at the current stage according to the comparison result, and notifying the current User Equipment (UE) or processing the next subframe.

In the above scheme, the method includes:

receiving a power gain range indicated by a radio frequency chip, and averagely dividing the power gain range into a plurality of subsections to obtain an average power gain variation;

updating the initial power gain value of a first frame received by the current UE to be the value of the minimum gain value, calculating the average power value of each symbol within the length of the first frame by using an average power calculation method, comparing and finding out the maximum average power value as the maximum average power value of the first frame;

when the maximum average power value of the first frame is larger than the upper power limit, updating the initial power gain value of the first frame to be used as the initial power gain value of the second frame;

when the maximum average power value of the first frame is smaller than the upper power limit and smaller than the lower power limit, updating the initial power gain value of the first frame to be used as the initial power gain value of the second frame;

when the maximum average power value of the first frame is smaller than the upper power limit and simultaneously larger than the lower power limit, updating the initial power gain value of the first frame to be used as the initial power gain value of the second frame;

outputting the maximum average power value of the first frame as a power gain control value of a second frame to the PSS detection and PBCH reading stage;

calculating the average power value of each symbol within the length of the second frame by using an average power calculation method, comparing and finding out the maximum average power value as the maximum average power value of the second frame,

when the maximum average power value of the second frame is larger than the upper power limit, updating the initial power gain value of the second frame to be used as the initial power gain value of the third frame;

when the maximum average power value of the second frame is smaller than the upper power limit and smaller than the lower power limit, updating the initial power gain value of the second frame to be used as the initial power gain value of a third frame;

when the maximum average power value of the second frame is smaller than the upper power limit and simultaneously larger than the lower power limit, updating the initial power gain value of the second frame to be used as the initial power gain value of a third frame;

outputting the maximum average power value of the second frame as a power gain control value of the second frame to the PSS detection and PBCH reading stage;

and so on until all frames received by the UE are completed.

In the above scheme, the method includes:

receiving a power output control value sent by the current frame in the frequency point scanning and PSS detection stage, and taking the power output control value as a first half frame initial power gain value of the current frame;

calculating the average power of the PSS symbol and the SSS symbol of the first half frame in the frequency domain according to an average power calculation method, and filtering through a loop filter circuit, wherein the average power value is taken as the average power value of the first half frame of the current frame;

judging whether the first half frame average power value is equal to the first target power value or not, and entering the second half frame processing of the current frame when the first half frame average power value is equal to the first target power value; when the first half frame average power value is not equal to the first target power value, updating the first half frame average power gain value as a current half frame power gain control value, outputting the current half frame average power gain control value to the downlink service channel receiving stage, and simultaneously entering the step of processing a current frame second half frame;

the step of processing the second half frame of the current frame comprises the following steps:

calculating the average power of the PSS symbol and the SSS symbol of the second field in the frequency domain according to an average power calculation method, and filtering through a loop filter circuit, wherein the average power value is taken as the average power value of the second field;

judging whether the second field average power value is equal to the first target power value or not, and entering the third field processing of the current frame when the second field average power value is equal to the first target power value; when the average power value of the second half frame is not equal to the first target power value, updating the average power gain value of the second half frame as the power gain control value of the current half frame, outputting the value to the receiving stage of the downlink service channel, and simultaneously entering the third half frame of the current frame for processing;

and so on until all the half frames received by the UE are completed.

In the above scheme, the method includes:

the downlink service channel receiving stage receives the current half-frame power gain control value sent by the PSS detection and PBCH reading stage, performs variable bandwidth processing on the current half-frame power gain control value, and takes the processed current half-frame power gain control value as the initial power gain value of the first subframe of the current half-frame;

calculating the average power of the RS symbols of the first subframe in the frequency domain according to an average power calculation method, and filtering the RS symbols by a loop filter circuit, wherein the average power value is the average power value of the first subframe of the current field;

comparing whether the first subframe average power value is equal to the second target power value or not, and entering the second subframe processing of the current half frame when the first subframe average power value is equal to the second target power value; when the first subframe average power value is not equal to the second target power value, updating the first subframe average power gain value as a current subframe power gain control value and informing the current UE; meanwhile, processing a second subframe of the current field;

the entering process for the second subframe of the current half frame comprises the following steps:

calculating the average power of the RS symbol of the second subframe in the frequency domain according to the average power calculation method, and filtering the RS symbol by a loop filter circuit, wherein the average power value is the average power value of the second subframe of the current field;

comparing whether the average power value of the second subframe is equal to the second target power value or not, and entering the third subframe processing of the current half frame when the average power value of the second subframe is equal to the second target power value; when the second subframe average power value is not equal to the second target power value, updating the second subframe average power gain value as a current subframe power gain control value and informing the current UE; meanwhile, processing a third subframe of the current field;

and the rest is done until all the subframes received by the current UE are finished.

The invention also provides a TD-LTE automatic gain control device, which comprises: the power gain control module comprises a first-stage power gain control module, a second-stage power gain control module, a third-stage power gain control module and a loop filter circuit; wherein,

the first-stage power gain control module is used for calculating the average power value of each symbol of the current TD-LTE frame and determining the maximum average power value by taking the length of the 10ms frame as a unit, and comparing the maximum average power value with the upper power limit and/or the lower power limit to obtain the most reasonable power gain control value at the stage;

the second-stage power gain control module is used for calculating the average power values of the PSS symbol and the SSS symbol of the current half frame by taking the 5ms half frame length of the TD-LTE frame as a unit, and comparing the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with the first target power value to obtain the most reasonable power gain control value at the stage;

the third-stage power gain control module is used for calculating the average power value of the RS symbol of the current subframe by taking the 1ms subframe length of the TD-LTE frame as a unit, and comparing the calculated average power value of the RS symbol of the current subframe with a second target power value to obtain the most reasonable power gain control value at the stage;

and the loop filter circuit is used for filtering the average power value calculated by the second-stage power gain control module and the third-stage power gain control module.

In the foregoing solution, the first-stage power gain control module includes: the first processing submodule and the first updating output submodule; wherein,

the first processing sub-module is used for calculating the average power value of each symbol of the current TD-LTE frame by taking the length of the 10ms frame as a unit, comparing the average power values of each symbol of the current TD-LTE frame, determining the maximum average power value of the current frame, and comparing the maximum average power value of the current frame with the upper power limit and/or the lower power limit;

the first update output sub-module is configured to update the power gain control value of the current TD-LTE frame according to the comparison result, and send the updated power gain control value to the first processing sub-module as the initial power gain value of the next frame, or output the power gain control value of the current TD-LTE frame to the second-stage power gain control module as the power gain control value of the current frame in the first-stage power gain control module;

the first processing sub-module is further configured to start processing a next frame after receiving the initial power gain value of the next frame from the first update output sub-module.

In the foregoing solution, the second-stage power gain control module includes: the second processing submodule and the second updating output submodule;

the second processing submodule is used for calculating the average power value of the PSS symbol and the SSS symbol of the current half frame by taking the frame length of 5ms as a unit; comparing the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with the first target power value;

the second update output sub-module is configured to update the current half-frame power gain value according to the comparison result, output the current half-frame power gain value to the third-stage power gain control module, and simultaneously notify the second processing sub-module to perform next half-frame processing or notify the second processing sub-module to perform next half-frame processing;

and the second processing submodule is also used for starting to process the next half frame after receiving the notification sent by the second updating output submodule.

In the foregoing solution, the third-stage power gain control module includes: a third processing submodule and a third update output submodule; wherein,

the third processing sub-module is used for calculating the average power value of the RS symbol of the reference signal of the current subframe and comparing the calculated average power value of the RS symbol of the current subframe with a second target power value;

the third update output sub-module is configured to update the power gain control value of the current subframe according to the comparison result, notify the current UE of the update, and notify the third processing sub-module of next subframe processing or notify the third processing sub-module of next subframe processing;

and the third processing submodule is further configured to start processing a next subframe after receiving the notification sent by the third update output submodule.

Aiming at the environmental characteristics of three stages in the TD-LTE downlink signal processing process, the TD-LTE automatic gain control method and the TD-LTE automatic gain control equipment respectively take the frame length, the half frame length and the subframe length as units, calculate the average power of corresponding symbols in each TD-LTE frame, and respectively obtain the most reasonable power gain control value of each stage by comparing the average power with the upper power limit and/or the lower power limit, the first target power value and the second target power value; the invention distinguishes the environmental characteristics of three stages in the TD-LTE downlink signal processing process and increases the flexibility of power control.

Drawings

FIG. 1 is a schematic diagram of an implementation process of the TD-LTE automatic gain control method of the present invention;

FIG. 2 is a schematic diagram of the implementation process of the TD-LTE automatic gain control method of the present invention during the stages of frequency point scanning and PSS detection;

fig. 3 is a schematic diagram of a flow of implementing the TD-LTE automatic gain control method of the present invention during SSS detection and PBCH reading phases;

FIG. 4 is a schematic diagram of a flow chart of an implementation of the TD-LTE automatic gain control method of the present invention at the lower traffic channel receiving stage;

fig. 5 is a schematic diagram of a structure of the TD-LTE automatic gain control device according to the present invention.

Detailed Description

calculating the average power of corresponding symbols in each TD-LTE frame by taking the frame length as a unit in a frequency point scanning stage and a PSS detection stage, taking the half frame length as a unit in a SSS detection stage and a PBCH reading stage and taking the subframe length as a unit in a downlink service channel receiving stage respectively; and respectively comparing the average power with the upper power limit and/or the lower power limit, the first target power value and the second target power value to obtain the most reasonable power gain control value of each stage.

Here, the frequency point scanning and PSS detection stage calculates the average power of each symbol of each TD-LTE frame; the SSS detection and PBCH reading stage calculates the average power of a PSS symbol and an SSS symbol in each TD-LTE half frame; the average power of RS symbols in each TD-LTE subframe is calculated in the downlink traffic channel receiving phase.

As shown in fig. 1, the method specifically includes step 10, step 20, and step 30:

step 10: calculating the average power value of each symbol of the current TD-LTE frame by taking the length of the 10ms frame as a unit, determining the maximum average power value, comparing the calculated maximum average power value with the upper power limit and/or the lower power limit, and outputting the power gain control value of the current TD-LTE frame at the current stage to an SSS detection stage and a PBCH reading stage or processing the next TD-LTE frame according to the comparison result;

here, the frame length of 10ms is taken as a unit aiming at the environmental characteristics of the frequency point scanning and PSS detection stages;

specifically, for the frequency point scanning and PSS detection stages, the current UE does not acquire any synchronization information, so that the uplink and downlink signals in the whole cell may be used as average power estimation by the current UE within a TD-LTE frame length, i.e., 10 ms. Then, a statistical AGC method is used to obtain better power gain control for the environmental characteristics of this stage.

Currently, a UE receives a radio frequency circuit signal, where the radio frequency circuit includes a power amplifier, an Analog Digital Converter (ADC), a radio frequency chip, and the like; wherein, the radio frequency chip manufacturer already marks the applicable power gain range of the radio frequency chip when the radio frequency chip leaves the factory: from the minimum gain value G _ min to the maximum gain value G _ max; the power gain range is different according to different models of radio frequency chips and different according to different manufacturers.

As shown in fig. 2, the specific processing procedure of step 10 may be:

averagely dividing a power gain range M marked by a radio frequency chip into N subsections, wherein the average power gain of each subsection is M/N (db), and M/N (db) is taken as the variation of the average power gain, wherein N is a positive integer;

here, assuming that the number of all TD-LTE frames currently received by the UE is i, where i is a positive integer, all the received TD-LTE frames may be arranged as a first frame, a second frame.. an ith frame;

processing a first frame, and updating an initial power gain value A _ G (1) of the first frame to be a value of a minimum gain value G _ min;

substituting a first frame power gain initial value A _ G (1) into an average power value calculation method in the prior art, and calculating the average power value of each symbol within the length of a first frame;

comparing the average power value of each symbol within the length of the first frame, and finding out the maximum average power value as the maximum average power value of the first frame;

comparing the maximum average power value of the first frame with the upper power limit P_maxlimWhen the maximum average power value of the first frame is larger than the upper power limit P_maxlimWhen the frame is processed, updating the first frame initial power gain value a _ G (2) to a _ G (1) + M/N as a second frame initial power gain value, and entering the second frame processing; when the maximum average power value of the first frame is less than the upper power limit P_maxlimThen, the maximum average power value of the first frame is compared with the lower power limit P_minlimThe size of (d);

when the maximum average power value of the first frame is less than the lower power limit P_minlimWhen the frame is processed, updating the first frame initial power gain value A _ G (2) to A _ G (1) -M/N as a second frame initial power gain value, and entering the second frame processing; when the maximum average power value of the first frame is larger than the lower power limit P_minlimOutputting a first frame initial power gain value A _ G (1) to an SSS detection and PBCH reading stage as a power gain control value result1 output by the first frame in a frequency point scanning and PSS detection stage;

the entering processing the second frame may specifically be:

substituting a second frame power gain initial value A _ G (2) into an average power value calculation method in the prior art to calculate the average power value of each symbol within the length of a second frame;

comparing the average power value of each symbol in the length of the second frame and finding out the maximum average power value as the maximum average power value of the second frame;

comparing the maximum average power value of the second frame with the upper power limit P_maxlimWhen the maximum average power value of the second frame is larger than the upper power limit P_maxlimWhen the frame is processed, updating the second frame initial power gain value a _ G (3) to a _ G (2) + M/N as a third frame initial power gain value, and entering into processing a third frame; when the maximum average power value of the second frame is less than the upper power limit P_maxlimThen, the maximum average power value of the second frame is compared with the lower power limit P_minlimThe size of (d);

when the maximum average power value of the second frame is less than the lower power limit P_minlimWhen the frame is processed, updating the second frame initial power gain value A _ G (3) to A _ G (2) -M/N as a third frame initial power gain value, and entering into the third frame processing; when the maximum average power value of the second frame is larger than the lower power limit P_minlimThen, outputting a second frame initial power gain value A _ G (2) as a power gain control value result1 output by the second frame in the frequency point scanning and PSS detection stages;

the specific process of entering the third frame processing is similar to the implementation process of entering the second frame processing, and so on, until all frames received by the current UE are processed.

In step 10, the upper power limit P_maxlimLower power limit P_minlimPresetting; the upper power limit P for different frames_maxlimLower power limit P_minlimThe same value or different values can be adopted;

wherein the upper power limit P_maxlimHas a value range of 10log10 (2)^m) +15(db), workLower limit of rate P_minlimThe value range is 10log10 (2)^m) -15(db), m being the bit width of the ADC device; the bit width of the ADC device has been indicated as a bit width range when the ADC device was shipped.

In addition, the value range of the parameter N is 3-6, and the parameter N can be flexibly adjusted according to the actual environment (such as an external field test); when the actual environment requires faster convergence and the requirement on the gain precision range is not high, N can be taken as a smaller value; on the contrary, N can be taken as a relatively large value; because the frame is processed in the stage, the filtering processing is not required to be performed by a loop filter circuit after the average power value of each symbol in each frame length is calculated in the stage.

It has been described above that, after the frequency point scanning and PSS detection phases are finished, the position of the PSS symbol in the TD-LTE half-frame length is determined, that is, the half-frame synchronization is determined, that is, the UE knows the 5ms synchronization information at this time, and in the SSS detection and PBCH reading phases, the 5ms synchronization information is fully utilized to perform the automatic gain control in the SSS detection and PBCH reading phases.

Step 20: receiving a power gain control value, calculating the average power values of a PSS symbol and a SSS symbol of a current half frame by taking the 5ms half frame length of a TD-LTE frame as a unit, comparing the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with a first target power value, updating and outputting the power gain control value of the current half frame at the current stage to a downlink service channel receiving stage according to the comparison result, and simultaneously processing the next half frame or processing the next half frame;

here, regarding the environmental characteristics of the PSS detection and PBCH reading stage, the 5ms half frame length of the TD-LTE frame is taken as a unit;

it can be seen from the above scheme that the frequency point scanning and PSS detection stage is performed for 10ms of a TD-LTE frame, and after the frequency point scanning and PSS detection stage is finished, the current UE already knows 5ms of synchronization information, i.e. half frame synchronization information, and determines the signal time window of the PSS symbol; then, in SSS detection, the signal time window of the SSS symbol can be determined;

here, the signal time window of the PSS symbol and the SSS symbol can be seen as two points on the time axis, namely: the positions of the PSS symbol and the SSS symbol in the TD-LTE half frame length are determined, and the PSS symbol and the SSS symbol in the half frame length can be extracted; therefore, the processing is mainly performed according to the TD-LTE half frame length in the stage; here, the current 10ms TD-LTE frame is divided into a first field and a second field, both of which are 5ms long.

As shown in fig. 3, the specific processing procedure of step 20 may be:

receiving result1 output in the frequency point scanning and PSS detection stages as an initial power gain value in the stage;

for a TD-LTE system, firstly, result1 is used as an initial power gain value of a first subframe at the stage, after a PSS symbol and an SSS symbol of a first half frame of a current TD-LTE frame of 10ms are extracted, the average power of the PSS symbol and the SSS symbol of the first half frame in a frequency domain is calculated by using the prior art, and is accumulated and averaged for a plurality of times, and is filtered by a loop filter circuit so as to filter noise, wherein the obtained result is a first half frame average power value p 1;

judging whether the first half frame average power value p1 is equal to the first Target power value Target, and when p1 is equal to Target, taking result1 as a second half frame initial power gain value to enter the processing of the second half frame of the TD-LTE frame of the current t0 ms; when p1 is not equal to Target, updating a power gain control value result2 of the first field at the stage to result1+ (Target-p1), outputting result2 to a downlink traffic channel receiving stage, and entering the process of the second field of the current TD-LTE frame of 10ms by taking result2 as the initial power gain value of the second field;

the entering of the processing of the second half frame of the current TD-LTE frame of 10ms specifically comprises: extracting a PSS symbol and a SSS symbol of a second half frame of the current TD-LTE frame of 10ms, and calculating a second half frame average power value p2 by utilizing the prior art; then, judging whether the second field average power value p2 is equal to the Target power value Target, and entering a first field of a next TD-LTE frame when p2 is equal to the Target; when p2 is not equal to Target, updating the power gain control value result2 of the second field at this stage (p _ old + (Target-p2) and outputting result2 to the downlink traffic channel receiving stage;

here, when the condition from "when p1 is not equal to Target" is satisfied and executed until this time, then p _ old is assumed to be result 2; when the condition from "when p1 equals Target" is satisfied, then p _ old is taken to result 1;

and repeating the steps until all the half frames received by the current UE are processed.

Here, the value of the first Target power value Target is designed according to the bit width m of the ADC device actually selected in the TD-LTE system and the risk of saturation in the case of large noise/interference, and usually the Target is 2^m。

Meanwhile, as the phase is processed aiming at the TD-LTE field, the field time is short, and a relatively large loop filter coefficient needs to be preset in a loop filter circuit to ensure the quick convergence of field symbols.

In this description, in the technical solution of the present invention, all values related to the loop filter coefficient are in a range of 0.04 to 0.5.

In addition, when the description of step 20 is performed, mainly taking the TD-LTE system with the bandwidth of 1.4M as an example, the technical solution of the present invention includes, but is not limited to, the TD-LTE system with the bandwidth of 1.4M, and may also be applied to TD-LTE systems with other bandwidths, such as TD-LTE systems with bandwidths of 10M, 15M, and 20M, and the like.

Step 30: receiving a power gain control value, calculating the RS symbol average power value of the current subframe by taking the 1ms subframe length of the TD-LTE frame as a unit, comparing the calculated RS symbol average power value of the current subframe with a second target power value, updating the power gain control value of the current subframe at the current stage according to the comparison result, and informing the current UE or processing the next subframe;

here, for the environmental characteristics of the downlink traffic channel receiving stage, the 1ms subframe length of the TD-LTE frame is taken as a unit;

for the downlink service channel receiving stage, the current UE already knows the TD-LTE downlink synchronization information such as 5ms synchronization information, 10ms synchronization information, and frame number synchronization information, that is, the current UE can determine the position of a reference Signal (RS, Referenc Signal) symbol in each 1ms subframe in each subframe through downlink synchronization, and then the RS in each subframe can be extracted; therefore, the processing is mainly performed on each 1ms subframe of the TD-LTE in the phase;

here, the current 5ms TD-LTE half frame is divided into a first subframe, a second subframe, a third subframe, a fourth subframe, and a fifth subframe, each of which is 1ms long.

Since the SSS detection and PBCH reading phase are different from the bandwidth of the current phase, the current phase is exemplified by a TD-LTE system with 20M bandwidth, because the power and the bandwidth are in a direct proportion relationship, that is, as the bandwidth increases, the power is correspondingly increased. In order to achieve better connection between the SSS detection and PBCH reading phases and this phase, the power gain control value result2 sent from the SSS detection and PBCH reading phases needs to be processed with variable bandwidth first.

As shown in fig. 4, the specific processing procedure of step 30 may be:

the bandwidth-variable processing is performed on the power gain control value result2 sent in the SSS detection and PBCH reading phases as shown in formula (1):

result2_new＝result2-10*log10(B_new/B_old)(1)

wherein, the variable B_oldTD-LTE system bandwidth adopted in SSS detection and PBCH reading stages; b is_newThe TD-LTE system bandwidth is adopted at this stage.

Reading result2_ new as the initial power gain value of the first sub-frame in the current stage;

after the RS symbol of the first subframe of the current 5ms TD-LTE field frame is extracted, calculating the average power of the RS symbol of the first subframe of the current field frame in a frequency domain by using the prior art, and performing loop filtering by using a loop filtering circuit so as to filter noise, wherein the obtained result is a first subframe average power value M _ p 1;

judging whether the first sub-frame average power value M _ p1 is equal to the second target power value Tar, and when M _ p1 is equal to Tar, processing the second sub-frame by taking result2_ new as the initial power gain value of the second sub-frame; when the M _ p1 is not equal to Tar, updating a power gain control value result3 of the first subframe at this stage to result2_ new + (Tar-M _ p1), notifying the current UE of a result3 value, and processing the second subframe by taking result3 as an initial power gain value of the second subframe;

wherein, the processing of the second subframe may specifically be: extracting the RS symbol of a second subframe of the current 5ms TD-LTE field, calculating the average power of the RS symbol of the second subframe in a frequency domain by using the prior art, and performing loop filtering by using a loop filtering circuit so as to filter noise, wherein the obtained result is the average power value M _ p2 of the second subframe;

judging whether the average power value M _ p2 of the second subframe is equal to the second target power value Tar, and when M _ p2 is equal to Tar, processing a third subframe by taking result2_ new as the initial power gain value of the second subframe; when the M _ p2 is not equal to Tar, updating the power gain control value result3 ═ Y + (Tar-M _ p2) of the second subframe at this stage, notifying the current UE of the value of result3, and processing the third subframe by taking result3 as the initial power gain value of the third subframe;

here, when the condition of "M _ p1 being equal to Tar" is satisfied until this time, Y ═ result2_ new; when the condition from "M _ p1 not equal to Tar" holds true until this time, Y ═ result 3;

and repeating the steps until each subframe received by the current UE is processed.

In step 30, the second Target power value Tar is designed according to a bit width m of an ADC device actually selected in the TD-LTE system, and usually, the Target is 2m, where the bit width m of the ADC device is already indicated when the ADC device leaves a factory.

Considering that the control frequency required at this stage is high, a small loop filter coefficient needs to be selected in the loop filter circuit to ensure the stability of the downlink.

The TD-LTE automatic gain control method is based on the TD-LTE automatic gain control method. The present invention also provides a TD-LTE automatic gain control device, as shown in fig. 5, the device includes: a first stage power gain control module 50, a second stage power gain control module 51, a third stage power gain control module 52 and a loop filter circuit 53; wherein,

the first-stage power gain control module 50 is configured to calculate an average power value of each symbol of a current TD-LTE frame and determine a maximum average power value, and compare the maximum average power value with an upper power limit and/or a lower power limit to obtain a most reasonable power gain control value at this stage, with the 10ms frame length as a unit;

the second-stage power gain control module 51 is configured to calculate average power values of a PSS symbol and a SSS symbol of a current half frame by using a half frame length of 5ms of a TD-LTE frame as a unit, and compare the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with a first target power value to obtain a most reasonable power gain control value at this stage;

the third-stage power gain control module 52 is configured to calculate an average power value of an RS symbol of the current subframe by using a 1ms subframe length of the TD-LTE frame as a unit, and compare the calculated average power value of the RS symbol of the current subframe with a second target power value to obtain a most reasonable power gain control value at this stage;

the loop filter circuit 53 is configured to filter the average power values calculated by the second-stage power gain control module 51 and the third-stage power gain control module 52.

Here, the first phase is a frequency point scanning and PSS detection phase, the second phase is an SSS detection and PBCH reading phase, and the third phase is a downlink traffic channel receiving phase.

Specifically, the first-stage power gain control module 50 receives a power gain range M indicated by the rf chip, averagely divides M into N subsections, and takes M/N (db) as an average power gain variation; then updating the initial power gain value of the first frame received by the current UE to be the value of the minimum gain value, calculating the average power value of each symbol within the length of the first frame by using the average power calculation method in the prior art, comparing and finding out the maximum average power value as the maximum average power value of the first frame;

when the maximum average power value of the first frame is smaller than the upper power limit and simultaneously larger than the lower power limit, updating the initial power gain value of the first frame to be used as the initial power gain value of the second frame; meanwhile, the initial power gain value of the first frame is used as the power gain control value of the current frame and is output to the second-stage power gain control module 51;

according to the above technical solution, the first-stage power gain control module 50 processes the second frame received by the current UE until all the received frames are completed.

Here, the power gain range and the minimum gain value are already indicated as values when the radio frequency chip is shipped from a factory.

The second-stage power gain control module 51 receives the current frame power output control value sent by the first-stage power gain control module 50 as the current frame first half-frame initial power gain value;

according to the average power calculation method in the prior art, the second-stage power gain control module 51 may calculate the average power of the PSS symbol and the SSS symbol of the first half frame of the current frame in the frequency domain, and then the second-stage power gain control module 51 sends the calculated average power to the loop filter circuit 53, and the average power is filtered by the loop filter circuit 53 and then returned to the second-stage power gain control module 51, where the returned average power value is the first-half frame average power value;

the second-stage power gain control module 51 receives and determines whether the first half-frame average power value is equal to the first target power value;

when the first half frame average power value is equal to the first target power value, the second power gain control module 51 starts to process the second half frame of the current frame according to the above technical solution by using the current frame power output control value sent by the first stage power gain control module 50 as the second half frame initial power gain value;

when the first half frame average power value is not equal to the first target power value, the second-stage power gain control module 51 updates the first half frame average power gain value as a current half frame power gain control value, and outputs the current half frame average power gain value to the third-stage power control module 52; meanwhile, the updated average power gain value of the first half frame is used as the initial power gain value of the second half frame, and the second half frame of the current frame is processed according to the technical scheme;

according to the above technical solution, the second-stage power gain control module 51 processes the second field of the current frame until all fields received by the current UE are processed.

The third-stage power gain control module 52 receives the current field power gain control value sent by the second-stage power gain control module 51, performs bandwidth-variable processing on the current field power gain control value by using a formula (1), and takes the processed current field power gain control value as the initial power gain value of the first subframe of the current field;

according to the average power calculation method in the prior art, the third-stage power gain control module 52 calculates the average power of the RS symbol of the first subframe in the frequency domain, sends the calculated average power to the loop filter circuit 53, and returns the average power to the third-stage power gain control module 52 after being filtered by the loop filter circuit 53, where the returned average power value is the average power value of the first subframe;

comparing whether the first sub-frame average power value is equal to the second target power value;

when the average power value of the first subframe is equal to the second target power value, the initial power gain value of the first subframe is used as the initial power gain value of the second frame, and the third-stage power gain control module 52 starts to process the second subframe of the current field according to the above technical solution;

when the first sub-frame average power value is not equal to the second target power value, the third-stage power gain control module 52 updates the first sub-frame average power gain value as a current sub-frame power gain control value and notifies the current UE of the current sub-frame power gain control value; meanwhile, the updated average power gain value of the first subframe is used as the initial power gain value of the second frame, and the second subframe of the current half frame is processed according to the technical scheme;

according to the above technical solution, the third-stage power gain control module 52 processes the second subframe of the current field until all subframes received by the current UE are processed.

The first stage power gain control module 50 further comprises a first processing sub-module 500 and a first update output sub-module 501; wherein,

the first processing sub-module 500 is configured to calculate an average power value of each symbol of a current TD-LTE frame by taking a 10ms frame length as a unit, compare the average power values of each symbol of the current TD-LTE frame, determine a maximum average power value of the current frame, and compare the maximum average power value of the current frame with an upper power limit and/or a lower power limit;

the first update output sub-module 501 is configured to update the power gain control value of the current TD-LTE frame according to the comparison result, and send the updated value to the first processing sub-module 500 as the initial power gain value of the next frame, or output the initial power gain value of the current TD-LTE frame to the second stage power gain control module 51 as the current power gain control value of the TD-LTE frame;

the first processing sub-module 500 is further configured to start processing a next frame after receiving an initial power gain value of the next frame from the first update output sub-module 501;

the second stage power gain control module 51 further comprises a second processing sub-module 510 and a second updated output sub-module 511;

the second processing sub-module 510 is configured to calculate an average power value of a PSS symbol and an SSS symbol of a current half frame by taking a 5ms frame length as a unit; comparing the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with the first target power value;

the second update output sub-module 511 is configured to update and output the current half-frame power gain value to the third-stage power gain control module 52 according to the comparison result, and notify the second processing sub-module 510 to perform the next half-frame processing; or only inform the second processing sub-module 510 to perform the next half frame processing;

the second processing sub-module 510 is further configured to start processing the next half frame after receiving the notification sent by the second update output sub-module 511.

The third stage power gain control module 52 further comprises a third processing sub-module 520 and a third update output sub-module 521; wherein,

the third processing sub-module 520 is configured to calculate an RS symbol average power value of the current subframe after calculating the variable bandwidth, and compare the calculated RS symbol average power value of the current subframe with a second target power value;

the third update output sub-module 521 is configured to update the power gain control value of the current subframe according to the comparison result, notify the current UE of the updated power gain control value, and notify the third processing sub-module 520 of performing the next subframe processing; or only notify the third processing sub-module 520 to process the next sub-frame;

the third processing sub-module 520 is further configured to start processing a next sub-frame after receiving the notification sent by the third update output sub-module 521.

Specifically, when the current UE is in the frequency point scanning and PSS detection stage, first, the first processing sub-module 500 receives the power gain range M indicated by the radio frequency chip, and averagely divides M into N sub-segments, so that M/N (db) is the average power gain of each sub-segment;

here, M/N (db) is taken as the average power gain variation amount, where N is a positive integer; when the radio frequency chip leaves a factory, marking a minimum gain value G _ min and a maximum gain value G _ max;

sequentially numbering all frames received by the current UE, wherein the frames are a first frame and a second frame.

The first processing sub-module 500 firstly processes the first frame, and updates the initial power gain value a _ G (1) of the first frame to the value of the minimum gain value G _ min;

by using the average power calculation method in the prior art, the first processing sub-module 500 calculates the average power value of each symbol within the length of the first frame; comparing the average power value of each symbol within the length of the first frame and finding out the maximum average power value as the maximum average power value of the first frame;

when the maximum average power value of the first frame is larger than the upper power limit P_maxlimThen, the first update output sub-module 501 updates the first frame initial power gain value a _ G (2) ═ a _ G (1) + M/N as the second frame initial power gain value, and the first update output sub-module501 outputs a _ G (2) at this time to the first processing sub-module 500;

when the maximum average power value of the first frame is less than the upper power limit P_maxlimThen, the first processing sub-module 500 compares the maximum average power value of the first frame with the lower power limit P_minlimThe size of (a) is (b),

when the maximum average power value of the first frame is less than the lower power limit P_minlimIf so, the first update output sub-module 501 updates the first frame initial power gain value a _ G (2) ═ a _ G (1) -M/N as the second frame initial power gain value, and the first update output sub-module 501 outputs a _ G (2) at this time to the first processing sub-module 500;

when the maximum average power value of the first frame is larger than the lower power limit P_minlimMeanwhile, the first update output sub-module 501 outputs an a _ G (1) value to the second stage power gain control module 51, and specifically to the second processing sub-module 510, as a power gain control value result1 output by the first frame in the frequency point scanning and PSS detection stages;

after the first processing sub-module 500 receives the a _ G (2), the first processing sub-module 500 calculates an average power value of each symbol within the second frame length by using an average power calculation method in the prior art; comparing the average power value of each symbol within the length of the second frame and finding out the maximum average power value as the maximum average power value of the second frame;

when the maximum average power value of the second frame is larger than the upper power limit P_maxlimIf so, the first update output sub-module 501 updates the second frame initial power gain value a _ G (3) to a _ G (2) + M/N as the third frame initial power gain value, and the first update output sub-module 501 outputs a _ G (3) at this time to the first processing sub-module 500;

when the maximum average power value of the second frame is less than the upper power limit P_maxlimThen, the first processing sub-module 500 compares the maximum average power value of the second frame with the lower power limit P_minlimThe size of (a) is (b),

when the maximum average power value of the second frame is less than the lower power limit P_minlimIf so, the first update output sub-module 501 updates the second frame initial power gain value a _ G (3) ═ a _ G (2) -M/N as the third frame initial power gain value, and the first update output sub-module 501 outputs a _ G (3) at this time to the first processing sub-module 500;

when the maximum average power value of the first frame is larger than the lower power limit P_minlimMeanwhile, the first update output sub-module 501 outputs an a _ G (2) value to the second-stage power gain control module 51, and specifically to the second processing sub-module 510, as a power gain control value result1 output by the first-stage power gain control module 50 for the second frame;

according to the above technical solution, after receiving the a _ G (3), the first processing sub-module 500 completes processing of the third frame in combination with the first update output sub-module 501, and so on until completing processing of all frames received by the current UE.

Here, the upper power limit P_maxlimLower power limit P_minlimPreset in the first-stage power gain control module 50, specifically, in the first processing sub-module 500; the upper power limit P for different frames_maxlimLower power limit P_minlimCan take the same value or different values;

wherein the upper power limit P_maxlimHas a value range of 10log10 (2)^m) +15(db), lower power limit P_minlimThe value range is 10log10 (2)^m) -15(db), m being the bit width of the ADC device in the radio frequency circuit; the signal sent by the radio frequency circuit is received by the current UE;

in addition, the value range of the parameter N is 3 to 6, which is preset in the first-stage power gain control module 50, specifically, in the first processing sub-module 500; since this stage is processing the frame, after the first processing sub-module 500 calculates the average power value of each symbol within each frame length, it is not necessary to send the calculated average power value of each symbol to the loop filter circuit 53 for filtering.

When the current UE is in the PSS detection and PBCH reading phase, the second processing sub-module 510 receives result1 sent by the first-phase power gain control module 50 as an initial power gain value;

at this stage, the current UE can obtain 5ms synchronization information, so the second stage power gain control module 51 can determine the positions of the PSS symbol and the SSS symbol in each field, and further can extract and calculate the average power values of the PSS symbol and the SSS symbol in each field;

taking a TD-LTE frame received by the current UE as an example, the TD-LTE frame may be divided into a first half frame and a second half frame;

the second processing sub-module 510 receives result1 sent by the first-stage power gain control module 50 as a first half-frame initial power gain value, calculates average power of PSS symbol and SSS symbol of the first half-frame in the frequency domain according to the average power calculation method of the prior art by substituting result1, then the second processing sub-module 510 sends the calculated average power to the loop filter circuit 53, the average power is returned to the second processing sub-module 510 after being filtered by the loop filter circuit 53, and the returned average power value is the first half-frame average power value p 1;

the second processing submodule 510 determines whether the first half-frame average power value p1 is equal to the first Target power value Target,

when p1 equals Target, the second processing sub-module 510 starts the processing of the second field with result1 as the initial power gain value of the second field;

when p1 is not equal to Target, the second update output sub-module 511 updates the first half-frame power gain control value result2, and outputs result2 to the third stage power control module 52, specifically to the third processing sub-module 520; with result2 as the initial power gain value of the second field, the second update output sub-module 511 notifies the second processing sub-module 510 to enter the second field processing;

wherein, result2 ═ result1+ (Target-p 1);

after the second processing sub-module 510 receives the notification (result2 is used as the second field initial power gain value) or identifies itself (result1 is used as the second field initial power gain value) that the next field needs to be processed, it starts to process the second field: substituting the second field initial power gain value into the average power calculation method in the prior art to calculate the average power of the PSS symbol and the SSS symbol of the second field in the frequency domain, then sending the calculated average power to the loop filter circuit 53 by the second processing sub-module 510, and returning the average power to the second processing sub-module 510 after filtering by the loop filter circuit 53, where the returned average power value is the second field average power value p 2;

said second processing submodule 510 determines whether the second field average power value p1 is equal to the first Target power value Target,

when p2 is equal to Target, taking the initial power gain value of the second field as the initial power gain value of the third field, the second processing sub-module 510 starts to process the third field;

when p2 is not equal to Target, the second update output sub-module 511 updates the first half-frame power gain control value result2, result2 ═ p _ old + (Target-p1), and outputs result2 to the third stage power gain control module 52, specifically to the third processing sub-module 520; the second update output sub-module 511 notifies the second processing sub-module 510 to enter the processing of the first half frame of the next frame;

when the condition of "when p1 is not equal to Target" is satisfied and executed, then, p _ old is set to result 2; when the condition from "when p1 equals Target" is satisfied, execute until this time, take p _ old to result 1;

according to the above technical solution, after receiving the notification or after identifying that the first half frame of the next frame needs to be performed, the second processing sub-module 510 is combined with the second update output sub-module 511 to complete the processing of the first half frame of the next frame; until all the half frames received by the current UE are processed.

Here, the first Target power value Target is preset in the second stage power gain control module 51, specifically in the second processing sub-module 510.

When the current UE is in the downlink traffic channel receiving stage, the current UE can obtain 5ms synchronization information, 10ms synchronization information, and frame number synchronization information, so that the third-stage power gain control module 52 can determine the RS symbol position in each subframe, and can extract and calculate the RS symbol average power value of each subframe;

taking one TD-LTE field received by the current UE as an example, the TD-LTE field can be divided into a first subframe, a second subframe, a third subframe, a fourth subframe and a fifth subframe;

because the working bandwidths of the second-stage power gain control module 51 and the third-stage power gain control module 52 are different, after receiving the power gain control value result2 of the second-stage power gain control module 51, the third processing sub-module 520 performs variable bandwidth processing according to the formula (1), and then reads the result2_ new after the variable bandwidth processing is performed as the initial power gain value of the first subframe;

the third processing sub-module 520 substitutes result2_ new into the average power calculation method in the prior art to calculate the average power of the RS symbol of the first subframe in the frequency domain, and then the third processing sub-module 520 sends the calculated average power to the loop filter circuit 53, and after filtering by the loop filter circuit 53, returns the average power to the third processing sub-module 520, where the returned average power value is the average power value M _ p1 of the first subframe;

next, the third sub-module 520 determines whether the first sub-frame average power value M _ p1 is equal to the second target power value Tar,

when M _ p1 is equal to Tar, the third processing submodule 520 starts to process the second subframe with result2_ new as the initial power gain value of the second subframe;

when M _ p1 is not equal to Tar, the third update output sub-module 521 updates the first subframe power gain control value result3 ═ result2_ new + (Tar-M _ p1) and informs the current UE of result 3; with result3 as the initial power gain value of the second field, the third update output sub-module 521 notifies the third processing sub-module 520 to enter into the second sub-frame processing;

after the third processing sub-module 520 receives the notification (with result3 as the second field initial power gain value) or identifies itself (with result2_ new as the second field initial power gain value) that the next subframe processing is required, the third processing sub-module starts to process the second subframe in combination with the third update output sub-module 521:

the third processing sub-module 520 calculates the average power of the RS symbol of the second subframe in the frequency domain according to the average power calculation method in the prior art, and then the third processing sub-module 520 sends the calculated average power to the loop filter circuit 53, and after filtering by the loop filter circuit 53, returns the average power to the third processing sub-module 520, where the returned average power value is the average power value M _ p1 of the second subframe;

next, the third sub-module 520 determines whether the second sub-frame average power value M _ p2 is equal to the second target power value Tar,

when M _ p2 is equal to Tar, the third processing sub-module 520 starts to process the third sub-frame with result2_ new as the initial power gain value of the third sub-frame;

when M _ p2 is not equal to Tar, the third update output sub-module 521 updates the second subframe power gain control value result3 ═ Y + (Tar-M _ p2) and informs the current UE of result 3; the third update output sub-module 521 notifies the third processing sub-module 520 to enter into processing of a third sub-frame;

here, when the condition of "M _ p1 being equal to Tar" is satisfied until this time, Y ═ result2_ new; when the condition from "M _ p1 not equal to Tar" holds true until this time 1, Y ═ result 3;

according to the above technical solution, after receiving the notification, the third processing submodule 520 is combined with the second update output submodule 521 to complete the processing of the next subframe; until all subframes received by the current UE are processed.

Here, the second target power value Tar is preset in the third stage power gain control module 52, specifically in the third processing sub-module 520;

at this stage, the current UE already knows the TD-LTE downlink synchronization information such as the 5ms synchronization information, the 10ms synchronization information, the frame number synchronization information, etc., that is, through downlink synchronization, the third processing sub-module 520 can determine the position of the reference signal RS (referenc signal) symbol in each 1ms subframe in each subframe, and then the RS in each subframe can be extracted.

The automatic gain control method and the automatic gain control equipment for the TD-LTE terminal provided by the invention are suitable for TD-LTE systems with bandwidths of 1.4M, 3M, 5M, 10M, 15M and 20M.

The TD-LTE automatic gain control method provided by the invention is used for calculating the average power of corresponding symbols by respectively taking the frame length as a unit, taking the half frame length as a unit and taking the subframe length as a unit according to the environmental characteristics of three stages, and obtaining the most reasonable power gain control value in the frequency point scanning and PSS detection stages by comparing the maximum average power value of a frame length symbol with the upper power limit and/or the lower power limit; comparing the average power values of the RSS symbol and the SSS symbol in the half frame with the first target power value to obtain the most reasonable power gain control value in the SSS detection and PBCH reading stages; the most reasonable power gain control value at the receiving stage of the downlink service channel can be obtained by comparing the average power value of the RS symbols of the subframe with the second target power value; the invention distinguishes the environmental characteristics of the three stages, and adopts different power gain control methods in each stage, thereby improving the flexibility of power control.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A TD-LTE automatic gain control method, the method comprising:

calculating the average power of corresponding symbols in each TD-LTE frame by taking the frame length as a unit in a frequency point scanning and primary synchronization symbol PSS detection stage, taking the half frame length as a unit in an auxiliary synchronization symbol SSS detection and physical broadcast channel PBCH reading stage and taking the subframe length as a unit in a downlink service channel receiving stage respectively; and respectively comparing the average power with the upper power limit and/or the lower power limit, the first target power value and the second target power value to obtain a power gain control value of each stage.

2. The TD-LTE automatic gain control method according to claim 1, wherein in the frequency point scanning and PSS detection stage, the method comprises:

3. The TD-LTE automatic gain control method according to claim 1, wherein during the SSS detection and PBCH reading phase, the method comprises:

4. The TD-LTE automatic gain control method according to claim 1, wherein in the downlink traffic channel receiving phase, the method comprises:

5. The TD-LTE automatic gain control method according to claim 2, wherein the method comprises:

and so on until all frames received by the UE are completed.

6. The TD-LTE automatic gain control method according to claim 3, wherein the method comprises:

and so on until all the half frames received by the UE are completed.

7. The TD-LTE automatic gain control method according to claim 4, wherein the method comprises:

8. A TD-LTE automatic gain control device, the device comprising: the power gain control module comprises a first-stage power gain control module, a second-stage power gain control module, a third-stage power gain control module and a loop filter circuit; wherein,

the first-stage power gain control module is used for calculating the average power value of each symbol of the current TD-LTE frame and determining the maximum average power value by taking the length of the 10ms frame as a unit, and comparing the maximum average power value with the upper power limit and/or the lower power limit to obtain the power gain control value of the stage;

the second-stage power gain control module is used for calculating the average power values of the PSS symbol and the SSS symbol of the current half frame by taking the 5ms half frame length of the TD-LTE frame as a unit, and comparing the calculated average power values of the PSS symbol and the SSS symbol of the current half frame with the first target power value to obtain a power gain control value of the stage;

the third-stage power gain control module is used for calculating the average power value of the RS symbol of the current subframe by taking the 1ms subframe length of the TD-LTE frame as a unit, and comparing the calculated average power value of the RS symbol of the current subframe with a second target power value to obtain a power gain control value of the stage;

9. The TD-LTE automatic gain control device of claim 8, wherein the first stage power gain control module comprises: the first processing submodule and the first updating output submodule; wherein,

10. The TD-LTE automatic gain control device of claim 8, wherein the second stage power gain control module comprises: the second processing submodule and the second updating output submodule;

11. The TD-LTE automatic gain control device of claim 8, wherein the third stage power gain control module comprises: a third processing submodule and a third update output submodule; wherein,