CN103839891A - Semiconductor structure and method for manufacturing semiconductor structure - Google Patents

Semiconductor structure and method for manufacturing semiconductor structure Download PDF

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Publication number
CN103839891A
CN103839891A CN201210489362.2A CN201210489362A CN103839891A CN 103839891 A CN103839891 A CN 103839891A CN 201210489362 A CN201210489362 A CN 201210489362A CN 103839891 A CN103839891 A CN 103839891A
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polycrystalline
layer
source
soi substrate
semiconductor structure
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尹海洲
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210489362.2A priority Critical patent/CN103839891A/en
Priority to PCT/CN2013/085532 priority patent/WO2014079296A1/en
Publication of CN103839891A publication Critical patent/CN103839891A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

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Abstract

The invention provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure comprises the steps that an SOI substrate is provided, grid accumulation is formed on the SOI substrate, and a side wall is formed in a side wall formed by the grid accumulation; a polycrystal Sil-xGex layer is formed on the SOI substrate; annealing is conducted, and a source/drain area is formed. Correspondingly, the invention further provides a semiconductor structure. According to the semiconductor structure and the method for manufacturing the semiconductor structure, the source/drain area of polycrystal Sil-xGex is formed at lower temperature, influence on doping distribution of channels and source/drain extension areas is reduced, and the performance and reliability of devices are improved.

Description

A kind of semiconductor structure and manufacture method thereof
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of semiconductor structure and manufacture method thereof.
Background technology
In order to improve performance and the integrated level of integrated circuit (IC) chip, device feature size constantly dwindles according to Moore's Law, has entered at present nanoscale.Along with dwindling of device volume, power consumption and leakage current become the problem of paying close attention to most.Adopt the cmos device prepared of silicon-on-insulator SOI (Silicon on Insulator) to there is high speed, low-power consumption, high integration, anti-irradiation and without many advantages such as self-locking effects, become the preferred structure of deep-submicron and Nano-MOS transistors.In order further to improve the performance of cmos device, often require the soi structure of very thin si membrane (≤100nm), make device channel in full spent condition, can improve short-channel effect, the Sub-Threshold Characteristic that improves device, the quiescent dissipation that reduces circuit, the elimination kink effects etc. such as DIBL (Drain Induced Barrier Lowering leaks and causes potential barrier reduction) with cmos circuit prepared by this ultra-thin SOI (UTSOI) structure.
But, because the top silicon surface (≤100nm) of ultra-thin SOI is very thin, larger source/drain region series resistance and contact resistance are caused, metal silicide may consume whole silicon fiml, but still be difficult to reduce the impact of source/drain region series resistance and contact resistance, also may cause larger leakage current simultaneously.By forming lifting source/leakage (Raised Source/Drain, RSD), can further reduce the contact resistance of source/drain region, increase the drive current of device, improve device performance.In prior art, forming lifting source/leak conventional method is selective epitaxial monocrystalline silicon, germanium etc., technological temperature is generally more than 650 DEG C, in technical process, easily make the dopant in the source/leakage expansion area, the channel doping district etc. that have formed distribute again, may cause threshold voltage too low, or the problem such as channel punchthrough short circuit.The technological temperature that reduces lifting source/leakage, reduces its impact on dopant profiles, becomes a significant challenge of lifting source/leakage technology.
Summary of the invention
The present invention is intended at least solve above-mentioned technological deficiency, and a kind of manufacture method and structure thereof of semiconductor device is provided, and reduces the technological temperature of lifting source/leakage growth, reduces its impact on semiconductor structure dopant profiles, improves the Performance And Reliability of semiconductor device.
For reaching above-mentioned purpose, the invention provides a kind of manufacture method of semiconductor structure, the method comprises the following steps:
(a) provide SOI substrate, on described SOI substrate, form gate stack, form side wall at the sidewall of described gate stack;
(b) on the SOI substrate exposing, form polycrystalline Si 1-xge xlayer;
(c) annealing, the polycrystalline Si on SOI substrate 1-xge xin layer, form source/drain region.
Wherein, form side wall in step (a) before or after, also comprise step:
Taking described gate stack as mask, formation source/drain extension region.
The present invention also proposes a kind of semiconductor structure on the other hand, comprises SOI substrate, gate stack, side wall, source/drain region, wherein:
Described SOI substrate comprises basalis, is positioned at the insulating barrier on described basalis and is positioned at the device layer on described insulating barrier;
Described gate stack is positioned on described SOI substrate;
Described side wall is positioned on the sidewall of described gate stack;
Described source/drain region is formed on described SOI substrate, is positioned at the both sides of described gate stack, and its material is polycrystalline Si 1-xge x.
According to semiconductor structure provided by the invention and manufacture method thereof, can form at a lower temperature source/drain region, reduce its impact on semiconductor structure dopant profiles, series resistance and the contact resistance of source/drain region are reduced, avoid the problems such as the reduction of threshold of appearance threshold voltage, channel punchthrough short circuit, improve the Performance And Reliability of semiconductor device.
Brief description of the drawings
The present invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments obviously and easily and understand, wherein:
Fig. 1 is the flow chart of an embodiment of the manufacture method of semiconductor structure, in accordance with the present invention;
Fig. 2 to Fig. 8 is in the cross-sectional view of each fabrication stage according to this semiconductor structure in the method manufacture semiconductor structure process shown in Fig. 1.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts to specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skill in the art can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
Fig. 1 is the flow chart of semiconductor structure, in accordance with the present invention manufacture method, and Fig. 2 to Fig. 8 is according to one embodiment of present invention according to the generalized section in each stage of the semiconductor structure of flow manufacturing shown in Fig. 1.Below in conjunction with Fig. 2 to Fig. 8, the method that forms semiconductor structure in Fig. 1 is described particularly.It should be noted that, the accompanying drawing of the embodiment of the present invention is only the object in order to illustrate, is therefore not necessarily to scale.
Referring to figs. 2 to Fig. 6, in step S101, provide SOI substrate 100, on described SOI substrate 100, form gate stack, form side wall 230 at the sidewall of described gate stack.As shown in Figure 2, described SOI substrate 100 comprises basalis 101, is positioned at the insulating barrier 102 on described basalis 101 and is positioned at the device layer 103 on described insulating barrier 102.
In the present embodiment, described basalis 101 is monocrystalline silicon.In other embodiments, described basalis 101 can also comprise such as germanium of other basic semiconductors, or other compound semiconductors, for example, and carborundum, GaAs, indium arsenide or indium phosphide.Typically, the thickness of described basalis 101 can be about but be not limited to hundreds of micron, the thickness range of for example 0.2mm-1mm.
Described insulating barrier 102 can be SiO 2, silicon nitride, Al 2o 3or other any suitable insulating material, typically, the thickness range of described insulating barrier 102 is 10nm～300nm.
Any in the semiconductor that described device layer 103 can comprise for described basalis 101.In the present embodiment, described device layer 103 is monocrystalline silicon.In other embodiments, described device layer 103 can also comprise other basic semiconductor or compound semiconductors.Typically, the thickness range of described device layer 103 is 10nm～100nm.In the present embodiment, described SOI substrate 100 is ultra-thin SOI (Ultra-Thin SOI, UTSOI) substrate, has device layer as thin as a wafer, and thickness is less than 10nm conventionally, is conducive to control the source/drain region degree of depth, forms super shallow junction, thereby reduces short-channel effect.
Especially, in described SOI substrate 100, form isolated area, for example shallow trench isolation is from (STI) structure 120, so that the continuous semiconductor device of electricity isolation.
Described grid are stacking to be formed on described SOI substrate 100, and it comprises gate dielectric layer 210, grid 220, as shown in Figure 3.Alternatively; described gate stack can also comprise the cover layer (not illustrating in the drawings) covering on described grid; for example, by deposited silicon nitride, silica, silicon oxynitride, carborundum and be combined to form; in order to protect the top area of grid 220, prevent that it is damaged in follow-up technique.Described gate dielectric layer 210 is positioned on SOI substrate 100, can be high K dielectric, for example, and HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2o 3, La 2o 3, ZrO 2, a kind of or its combination in LaAlO.In another embodiment, can also be thermal oxide layer, comprise silica, silicon oxynitride; The thickness of described gate dielectric layer 210 can be 1nm～10nm, as 5nm or 8nm.Then on described gate dielectric layer 210, form grid 220, described grid 220 can be the heavily doped polysilicon forming by deposition, or first form workfunction layers (for NMOS, for example TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x, NiTa xdeng, for PMOS, for example MoN x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x, Ni 3si, Pt, Ru, Ir, Mo, HfRu, RuO x), its thickness can be 1nm-20nm, as 3nm, 5nm, 8nm, 10nm, 12nm or 15nm, then in described workfunction layers, forms heavily doped polysilicon, Ti, Co, Ni, Al, W or its alloy etc. and formation grid 220.
As shown in Figure 4, described side wall 230 is formed on the stacking sidewall of grid, for separating stacking grid.Side wall 230 can and combine by silicon nitride, silica, silicon oxynitride, carborundum, and/or other suitable materials form.Side wall 230 can have sandwich construction.Side wall 230 can be by comprising that depositing-etching technique forms, and its thickness range can be 10nm～100nm, as 30nm, 50nm or 80nm.
Alternatively, in step S101, after being also included in the described gate stack of formation or after forming described side wall 230, formation source/drain extension region 300.The mode of injecting by low energy forms more shallow source/drain extension region 300 at substrate 100, can in substrate 100, inject P type or N-type alloy or impurity, and for example, for PMOS, source/drain extension region 300 can be the Si of P type doping; For NMOS, source/drain extension region 300 can be the Si of N-type doping.Alternatively, described semiconductor structure is annealed, with the doping in activation of source/drain extension region 300, annealing can adopt and comprise that other suitable methods such as short annealing, spike annealing form thereupon.In some other embodiment of the present invention, annealing operation carries out after also can being placed on and forming source/drain region.Because the thickness of source/drain extension region 300 is more shallow, can effectively suppress short-channel effect.Figure 5 shows that after forming described gate stack, inject taking described gate stack as mask, form the section of structure after described source/drain extension region 300, Figure 6 shows that after forming described side wall 230, form the section of structure after described source/drain extension region 300.
With reference to figure 1 and Fig. 7, execution step S102, on described SOI substrate 100, forms polycrystalline Si 1-xge xlayer 310.Form described polycrystalline Si 1-xge xthe method of layer 310 comprises plasma-reinforced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD), rapid heat chemical vapour deposition (RTCVD), by gas flow, air pressure, plant capacity etc. are adjusted, can control formation polycrystalline Si 1-xge xthe technological temperature of layer 310 is below 450 DEG C, and typical technological temperature is 425 DEG C, 400 DEG C.Than selective epitaxial single crystalline Si, Ge (technological temperature>=650 DEG C), chemical vapor deposition forms polycrystalline Si 1-xge xthe method of layer, less on the existing dopant profiles impact of semiconductor structure, be beneficial to the Performance And Reliability that improves semiconductor device.Typically, generate polycrystalline Si 1-xge xthe reacting gas of layer 310 is SiH 4, GeH 4, by controlling SiH 4or the gas flow of GeH4 or gas percentage, adjust Si 1-xge xthe ratio of component of middle Si and Ge.In the present embodiment, the value of x is 0.2～0.7.Described polycrystalline Si 1-xge xthe thickness of layer 310 can not be higher than the height of described gate stack, and its thickness range is 50nm～200nm.In the present embodiment, by forming described polycrystalline Si 1-xge xlayer carries out in-situ doped at 310 o'clock, realizes described polycrystalline Si 1-xge xthe doping of layer 310; In some other embodiment of the present invention, described polycrystalline Si can formed 1-xge xafter layer 310, then carry out Implantation, realize described polycrystalline Si 1-xge xthe doping of layer 310.Wherein said polycrystalline Si 1-xge xdoping content be 10 18～2x10 20cm -3, for NMOS, Si 1-xge xthe doping type of layer is N-type; For PMOS, described polycrystalline Si 1-xge xthe doping type of layer is P type.
With reference to figure 1 and Fig. 8, in step S103, anneal, and graphical described polycrystalline Si 1-xge xlayer, forms source/drain region 310.Annealing can adopt and comprise other suitable methods such as short annealing, spike annealing, and technological temperature is 450 DEG C～550 DEG C.In step S102, the Si that utilizes the methods such as plasma-reinforced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD), rapid heat chemical vapour deposition (RTCVD) to form 1-xge xlayer is likely amorphous, recovers its crystal structure by annealing, eliminates defect, thereby obtains polycrystalline Si 1-xge xlayer.On the other hand, activate donor and acceptor's impurity by annealing.Subsequently, by the suitable method such as dry etching RIE to described polycrystalline Si 1-xge xlayer carries out graphical, at the Si of etching 1-xge xon layer, form source/drain region 310.
Complete subsequently the manufacture of this semiconductor structure according to the step of conventional semiconductor fabrication process, for example, on source/drain region, form metal silicide; Deposition interlayer dielectric layer is to cover described source/drain region and gate stack; Described in etching, interlayer dielectric layer exposes source/drain region to form contact hole, in described contact hole, fills metal; And the processing step such as follow-up multiple layer metal interconnection.
The present invention also provides a kind of semiconductor structure, and as shown in Figure 8, described semiconductor structure comprises SOI substrate 100, gate stack, side wall 230, source/drain region 310.Wherein said SOI substrate 100 comprises basalis 101, is positioned at the insulating barrier 102 on described basalis 101 and is positioned at the device layer 103 on described insulating barrier 102; Described gate stack is positioned on described SOI substrate 100; Described side wall 230 is positioned on the sidewall of described gate stack; Described source/drain region 310 is formed on described SOI substrate 100, is positioned at the both sides of described gate stack, and its material is polycrystalline Si 1-xge x.Described polycrystalline Si 1-xge xthe thickness of source/drain region is 50nm～200nm, and the value of x is 0.2～0.7.Described polycrystalline Si 1-xge xdoping content be 10 18～2x10 20cm -3, for NMOS, described polycrystalline Si 1-xge xthe doping type of layer is N-type; For PMOS, described polycrystalline Si 1-xge xthe doping type of layer is P type.Described source/drain region 310 is lifting source/drain structure, and the top of source/drain region 310, higher than the bottom of described gate stack, is conducive to reduce series resistance and the contact resistance of source/drain region, polycrystalline Si 1-xge xthan polysilicon, there is less contact resistance, further improve the current driving ability of semiconductor device.
Alternatively, this semiconductor structure also comprises source/drain extension region 300, and described source/drain extension region 300 is embedded in described device layer 103, is sandwiched between described source/drain region 310 and insulating barrier 102.
Although describe in detail about example embodiment and advantage thereof, be to be understood that the protection range in the case of not departing from spirit of the present invention and claims restriction, can carry out various variations, substitutions and modifications to these embodiment.For other examples, those of ordinary skill in the art should easily understand in keeping in protection range of the present invention, and the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for had or be about at present technique, mechanism, manufacture, material composition, means, method or the step developed later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, can apply them according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.

Claims (10)

1. a manufacture method for semiconductor structure, the method comprises the following steps:
(a) provide SOI substrate, on described SOI substrate, form gate stack, form side wall at the sidewall of described gate stack;
(b) on the SOI substrate exposing, form polycrystalline Si 1-xge xlayer;
(c) annealing, the polycrystalline Si on SOI substrate 1-xge xin layer, form source/drain region.
2. method according to claim 1, in step (b), forms described polycrystalline Si 1-xge xthe method of layer is plasma-reinforced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD), rapid heat chemical vapour deposition (RTCVD).
3. method according to claim 2, wherein said polycrystalline Si 1-xge xthe thickness of layer is 50nm～200nm, and the value of x is 0.2～0.7.
4. method according to claim 1, wherein in step (b), by the method for in-situ doped or follow-up Implantation, to described polycrystalline Si 1-xge xlayer adulterates.
5. method according to claim 4, wherein said polycrystalline Si 1-xge xdoping content be 10 18～2x10 20cm -3, for NMOS, described polycrystalline Si 1-xge xthe doping type of layer is N-type; For PMOS, described polycrystalline Si 1-xge xthe doping type of layer is P type.
6. method according to claim 1, wherein, in step (a), before or after forming side wall, also comprises step:
Taking described gate stack as mask, formation source/drain extension region.
7. a semiconductor structure, this structure comprises SOI substrate, gate stack, side wall, source/drain region, wherein:
Described SOI substrate comprises basalis, is positioned at the insulating barrier on described basalis and is positioned at the device layer on described insulating barrier;
Described gate stack is positioned on described SOI substrate;
Described side wall is positioned on the sidewall of described gate stack;
Described source/drain region is formed on described SOI substrate, is positioned at the both sides of described gate stack, and its material is polycrystalline Si 1-xge x.
8. semiconductor structure according to claim 7, wherein, described polycrystalline Si 1-xge xthe thickness of source/drain region is 50nm～200nm, and the value of x is 0.2～0.7.
9. semiconductor structure according to claim 7, wherein, described polycrystalline Si 1-xge xdoping content be 10 18～2x10 20cm -3, for NMOS, described polycrystalline Si 1-xge xthe doping type of layer is N-type; For PMOS, described polycrystalline Si 1-xge xthe doping type of layer is P type.
10. semiconductor structure according to claim 7, wherein, also comprises source/drain extension region, and described source/drain extension region is embedded in the device layer of described SOI substrate, is sandwiched between described source/drain region and insulating barrier.
CN201210489362.2A 2012-11-26 2012-11-26 Semiconductor structure and method for manufacturing semiconductor structure Pending CN103839891A (en)

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