CN103838638A - Calibration method and device for FPGA plug-in storage - Google Patents
Calibration method and device for FPGA plug-in storage Download PDFInfo
- Publication number
- CN103838638A CN103838638A CN201410105880.9A CN201410105880A CN103838638A CN 103838638 A CN103838638 A CN 103838638A CN 201410105880 A CN201410105880 A CN 201410105880A CN 103838638 A CN103838638 A CN 103838638A
- Authority
- CN
- China
- Prior art keywords
- address
- data
- fpga
- test value
- proof test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Logic Circuits (AREA)
- Stored Programmes (AREA)
Abstract
The embodiment of the invention provides a calibration method and device for a FPGA plug-in storage. The method includes the following steps that an FPGA obtains first data and a first address corresponding to the first data, wherein the first data and the first address are written into the FPGA plug-in storage; a first address to be calibrated with the same digit with the first data is obtained according to the first address; XOR is performed on the first data and the first address to be calibrated, and a first XOR result is obtained; XOR is performed on the first XOR result and an initial calibration value, and a first calibration value is obtained. According to the calibration method and device for the FPGA plug-in storage, XOR is performed on the first data and the first address to be verified, XOR is performed on the XOR result and the initial calibration value, the calibration value is obtained, mixed calibration of the address and the data written into the FPGA plug-in storage is achieved, calibration of the data is finished, calibration of the address is also finished, and errors of the address can be found in time.
Description
Technical field
The present invention relates to the communication technology, relate in particular to the plug-in storer method of calibration of a kind of FPGA and device.
Background technology
The capacity of current field programmable gate array (Field Programmable Gate Array is called for short FPGA) chip is increasing, and the function completing is more and more stronger.In addition, along with the scale of plug-in storer is increasing, plug-in out of memory probability is also increasing, the inefficacy of plug-in storer is more and more serious to the function effect of above-mentioned FPGA, along with the development of large-scale F PGA, increasing application starts the application reliability of the plug-in storer of paying close attention to FPGA.
In prior art, the method of calibration of the plug-in storer to FPGA is mainly that the data of this plug-in storer are carried out to verification, particularly, can be according to the start address in check command, end address and startup mark, the data in storer to be read and verification, after verification completes, check results be preserved.
But, adopt prior art, if when mistake appears in address wire, cannot carry out verification.
Summary of the invention
The embodiment of the present invention provides the plug-in storer method of calibration of a kind of FPGA and device, while makeing mistakes for solving prior art address wire, and problem that cannot verification.
Embodiment of the present invention first aspect provides the plug-in storer method of calibration of a kind of FPGA, comprising:
A, on-site programmable gate array FPGA obtain the first data and first address corresponding to described the first data of the plug-in storer that writes described FPGA;
The first address to be verified that B, described FPGA are identical with the figure place of described the first data according to described the first address acquisition;
Described the first data and described the first address to be verified are carried out XOR by C, described FPGA, obtains the first XOR result;
Described the first XOR result and initial proof test value are carried out XOR by D, described FPGA, obtains the first proof test value;
E, described FPGA, using described the first proof test value as described initial proof test value, carry out A-D, until verification finishes.
In conjunction with first aspect, in the possible embodiment of the first of first aspect, arrange according to number order described the first data and described the first address to be verified, and described initial proof test value and described the first proof test value are arranged according to numbering backward.
In conjunction with first aspect, in the possible embodiment of the second of first aspect, the first address to be verified that described FPGA is identical with the figure place of described the first data according to described the first address acquisition, comprising:
Described FPGA judges that whether the figure place of described the first address is identical with the figure place of described the first data;
If the figure place of described the first address is identical with the figure place of described the first data, using described the first address as the first address to be verified;
If the figure place of described the first address is less than the figure place of described the first data, polishing is carried out in described address, obtain the first to be verified address identical with the figure place of described the first data.
In conjunction with first aspect, in the third possible embodiment of first aspect, described FPGA also comprises before obtaining the first data of the plug-in storer that writes described FPGA and the first address corresponding to described the first data:
Described FPGA obtains primary data and the initial address corresponding to described primary data of the plug-in storer that writes described FPGA;
Described FPGA obtains the initial to be verified address identical with the figure place of described primary data according to described initial address;
Described primary data and described initial address to be verified are carried out XOR by described FPGA, obtains initial XOR result;
Described FPGA is using described initial XOR result as initial proof test value.
In conjunction with first aspect, in the 4th kind of possible embodiment of first aspect, after described verification finishes, also comprise:
Described FPGA generates and reads address;
Described in described FPGA basis, read address reading out data and proof test value corresponding to described data from the plug-in storer of described FPGA;
Described FPGA separates exclusive or check according to described proof test value, judges in the plug-in storer of described FPGA whether fault of address and/or data according to described solution exclusive or check result.
In conjunction with the 4th kind of possible embodiment of first aspect, in the 5th kind of possible embodiment of first aspect, if described proof test value according to numbering backward arrange,
Described FPGA also comprises before separating exclusive or check according to described proof test value:
Described FPGA, according to the order that reads described proof test value, carries out backward by the proof test value of reading.
Embodiment of the present invention second aspect provides the plug-in storer calibration equipment of a kind of FPGA, comprising:
Acquisition module, for obtaining the first data and first address corresponding to described the first data of the plug-in storer that writes on-site programmable gate array FPGA; The first to be verified address identical with the figure place of described the first data according to described the first address acquisition;
Correction verification module, for described the first data and described the first address to be verified are carried out to XOR, obtains the first XOR result; Described the first XOR result and initial proof test value are carried out to XOR, obtain the first proof test value; Using described the first proof test value as described initial proof test value.
In conjunction with second aspect, in the possible embodiment of the first of second aspect, arrange according to number order described the first data and described the first address to be verified, and described initial proof test value and described the first proof test value are arranged according to numbering backward.
In conjunction with second aspect, in the possible embodiment of the second of second aspect, whether described acquisition module is identical with the figure place of described the first data specifically for judging the figure place of described the first address; If the figure place of described the first address is identical with the figure place of described the first data, using described the first address as the first address to be verified; If the figure place of described the first address is less than the figure place of described the first data, polishing is carried out in described address, obtain the first to be verified address identical with the figure place of described the first data.
In conjunction with second aspect, in the third possible embodiment of second aspect, described acquisition module, also for obtaining primary data and the initial address corresponding to described primary data of the plug-in storer that writes described FPGA; Obtain the initial to be verified address identical with the figure place of described primary data according to described initial address;
Described correction verification module, also, for described primary data and described initial address to be verified are carried out to XOR, obtains initial XOR result; Using described initial XOR result as initial proof test value.
In conjunction with second aspect, in the 4th kind of possible embodiment of second aspect, described device also comprises:
Separate correction verification module, read address for generating; According to described address reading out data and proof test value corresponding to described data from the plug-in storer of described FPGA read; Separate exclusive or check according to described proof test value, judge in the plug-in storer of described FPGA whether fault of address and/or data according to described solution exclusive or check result.
In conjunction with the 4th kind of possible embodiment of second aspect, in the 5th kind of possible embodiment of second aspect, described solution correction verification module, for in the time that described proof test value is arranged according to numbering backward, before separating exclusive or check according to described proof test value, according to the order that reads described proof test value, the proof test value of reading is carried out to backward.
In the embodiment of the present invention, XOR is carried out in the first data and the first address to be verified, and XOR result and initial proof test value are carried out to XOR, obtain proof test value, address that the plug-in storer of FPGA is write and the mixing verification of data are realized, not only complete the verification to data, also completed the verification to address, can find in time the mistake of address.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the application scenarios schematic diagram of the plug-in storer method of calibration of FPGA provided by the invention embodiment mono-;
Fig. 2 is the schematic flow sheet of the plug-in storer method of calibration of FPGA provided by the invention embodiment bis-;
Fig. 3 is the schematic flow sheet of the plug-in storer method of calibration of FPGA provided by the invention embodiment tri-;
Fig. 4 is the schematic flow sheet of the plug-in storer method of calibration of FPGA provided by the invention embodiment tri-;
Fig. 5 is the structural representation of the plug-in storer calibration equipment of FPGA provided by the invention embodiment mono-;
Fig. 6 is the structural representation of the plug-in storer calibration equipment of FPGA provided by the invention embodiment bis-;
Fig. 7 is the structural representation of the plug-in storer calibration equipment of FPGA provided by the invention embodiment tri-.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the application scenarios schematic diagram of the plug-in storer method of calibration of FPGA provided by the invention embodiment mono-, in the method application and FPGA, as shown in Figure 1, this FPGA comprises: FPGA user-side device 01, controller 02 and plug-in storer 03, wherein: FPGA user-side device 01 is connected with plug-in storer 03 by controller 02.
In the embodiment of the present invention, particularly, when FPGA user-side device 01 is carried out write access to plug-in storer 03, FPGA in Preset Time section write data and write address carries out exclusive or check.This Preset Time can be a computer clock, one claps.
Fig. 2 is the schematic flow sheet of the plug-in storer method of calibration of FPGA provided by the invention embodiment bis-, and as shown in Figure 2, the method comprises:
S201, FPGA obtain the first data and first address corresponding to this first data of the plug-in storer that writes this FPGA.
Usually, FPGA can obtain the first data and first address corresponding to these first data of the plug-in storer that writes this FPGA in Preset Time, and this Preset Time can be a computer clock, one claps.It should be noted that, in the plug-in storer of FPGA, there are many data lines, suppose that the plug-in memory data bus bit wide of FPGA is 16 bits (bit), there are 16 data lines, a bat writes 16 (16bit) data, be that every data lines writes data in each bat, so above-mentioned the first data are exactly 16.
The first address to be verified that S202, FPGA are identical with the figure place of these the first data according to this first address acquisition.
In specific implementation process, can be that FPGA judges that whether the figure place of the first address is identical with the figure place of above-mentioned the first data; If the figure place of the first address is identical with the figure place of above-mentioned the first data, using above-mentioned the first address as the first address to be verified; If the figure place of the first address is less than the figure place of above-mentioned the first data, address above mentioned is carried out to polishing, obtain the first to be verified address identical with the figure place of above-mentioned the first data.
Above-mentioned the first data and the first address to be verified corresponding to above-mentioned the first data are carried out XOR by S203, FPGA, obtains the first XOR result.
Because the first data are identical with the figure place of the first address to be verified, just correspondence is carried out XOR one by one, first of for example first of the first data and the first address to be verified is carried out XOR, and the second of the second of the first data and the first address to be verified carries out XOR, by that analogy.The XOR result of obtaining is like this also identical with the figure place of the first data.
Above-mentioned the first XOR result and initial proof test value are carried out XOR by S204, FPGA, obtains the first proof test value.
S205, FPGA, using above-mentioned the first proof test value as initial proof test value, carry out above-mentioned S201～S204, until verification finishes.Abovementioned steps is carried out in i.e. circulation, and the first proof test value at every turn newly obtaining is brought into next time and carried out verification in circulation as initial proof test value, constantly totally carries out exclusive or check.Usually, take the data of the complete packet of verification as end.
Wherein, the proof test value obtaining is also stored in the plug-in storer of this FPGA.
In the present embodiment, XOR is carried out in the first data and the first address to be verified, and XOR result and initial proof test value are carried out to XOR, obtain proof test value, address that the plug-in storer of FPGA is write and the mixing verification of data are realized, not only complete the verification to data, also completed the verification to address, can find in time the mistake of address.
Fig. 3 is the schematic flow sheet of the plug-in storer method of calibration of FPGA provided by the invention embodiment tri-, it should be noted that, above-mentioned initial verification address is also that FPGA obtains according to the data and the corresponding address that write the plug-in storer of FPGA.Particularly, as shown in Figure 3, above-mentioned FPGA also comprises before obtaining the first data of the plug-in storer that writes this FPGA and the first address corresponding to these first data:
S301, FPGA obtain primary data and the initial address corresponding to this primary data of the plug-in storer that writes this FPGA.
S302, FPGA obtain the initial to be verified address identical with the figure place of this primary data according to this initial address.
Particularly, can be referring to preceding method embodiment, if the figure place of initial address is identical with the figure place of above-mentioned primary data, using above-mentioned initial address as initial address to be verified; If the figure place of initial address is less than the figure place of above-mentioned primary data, address above mentioned is carried out to polishing, obtain the initial to be verified address identical with the figure place of above-mentioned primary data.
Primary data and this initial address to be verified are carried out XOR by S303, FPGA, obtains initial XOR result.
S304, FPGA are using this initial XOR result as initial proof test value.
This initial proof test value is to obtain according to the data and the corresponding address that write at first the plug-in storer of FPGA.
Illustrate, write the data of 16bit with (in a bat) in Preset Time to plug-in storer, the address of a corresponding 10bit is example.As shown in table 1, wherein, D
nrepresent the data of n bit, Am
nrepresent the nbit of address m: address 1(is as initial address) 0th～9bit(A1
0～A1
9) corresponding data 1(is as primary data) and 0th～15bit(D
0～D
15), for FPGA claps the 1st the data that write the plug-in storer of FPGA that get, because address 1 only has 10 bits, so in 0 and the data bit width alignment of complementary 6bit, obtain initial address to be verified, and then, initial address to be verified and data 1 are carried out XOR, obtain initial proof test value.0th～the 9bit(A2 of address 2
0～A2
9) 16th～31bit(D of corresponding data 2
16～D
31) clap the 2nd the data that get for the controller of FPGA, equally, 0 and data bit width alignment to address at complementary 6bit, obtain address 2 to be verified, and then, XOR is carried out to data 2 in address 2 to be verified, obtain the first XOR result, again the first XOR result and initial proof test value are carried out to XOR, obtain the first proof test value, and according to preceding method accumulation verification successively.0th～the 9bit(A3 of address 3
0～A3
9) 32nd～47bit(D of corresponding data 3
32～D
47) clap the 3rd the data that get for the controller of FPGA, equally, 0 and the data bit width alignment to address at complementary 6bit, obtains address 3 to be verified, and then, data 3 are carried out XOR with address 3 to be verified, obtain the second XOR result, this second XOR result and the further XOR of aforementioned the first proof test value, obtain the second proof test value, constantly verification is carried out in accumulation, finally obtains terminal check value, so that this terminal check value is read when FPGA user-side device read data.
Particularly, be verified as example, D with a data lines wherein
0with A1
0xOR result as first P of initial proof test value
0; Then D
16with A2
0carry out XOR, obtain the first XOR result first, first and P of this first XOR result
0carry out XOR, obtain the first proof test value, the P after upgrading
0; Next D
32with A3
0carry out XOR, obtain the second XOR result first, first of this second XOR result with carry out P
0xOR, the new proof test value obtaining is as the P after upgrading
0, totally carry out by that analogy verification.
Table 1
But in above-described embodiment, participate in the data D of verification
0, D
16, D
32and proof test value P
0all, on a data line, if this data lines lost efficacy into full 0 so, cannot verification go out result.Therefore in another embodiment, arrange according to number order above-mentioned the first data and above-mentioned the first address to be verified, and above-mentioned initial proof test value and above-mentioned the first proof test value are arranged according to numbering backward.
With reference to table 2, participate in the data D of verification
0, D
16, D
32and proof test value P
0not at same data line, participate in the data of verification and the proof test value of their correspondences not on same data line, when having avoided data line to lose efficacy, cannot obtain the problem of check results.
Table 2
Fig. 4 is the schematic flow sheet of the plug-in storer method of calibration of FPGA provided by the invention embodiment tri-, and as shown in Figure 4, the method comprises:
S401, FPGA generate and read address.
S402, FPGA are according to above-mentioned address reading out data and proof test value corresponding to above-mentioned data from the plug-in storer of above-mentioned FPGA read.
S403, FPGA separate exclusive or check according to above-mentioned proof test value, judge in the plug-in storer of above-mentioned FPGA whether fault of address and/or data according to above-mentioned solution exclusive or check result.
Separating exclusive or check is the inverse process of above-mentioned checking procedure, particularly, can be that XOR is carried out in last proof test value and data and the address of input before, take the check results of table 2 for example, as example: P
0with D
0, A1
0carry out XOR, and then and D
16, A2
0carry out XOR, follow and D
32, A3
0carry out XOR.
Usually, if when storer itself, memory data line, memory address line do not break down, the result of above-mentioned solution exclusive or check is full 0.
If separating the result of exclusive or check is not full 0, memory location or data line that so non-zero bit is corresponding break down.In the time that verification makes mistake, latch data value and address value, process accordingly according to system requirements, and simultaneity factor can judge that specifically make mistakes in address or data are made mistakes according to latched value.
It should be noted that, if above-mentioned proof test value is arranged according to numbering backward, before above-mentioned FPGA separates exclusive or check according to above-mentioned proof test value, also comprise:
FPGA, according to the order that reads above-mentioned proof test value, carries out backward by the proof test value of reading.Particularly, because FPGA is when the verification, check bit is arranged according to numbering backward, so that check bit with corresponding data not on same data line, so separate before verification, be by check bit backward again, return to and corresponding data sequence consensus, to separate exclusive or check.
Fig. 5 is the structural representation of the plug-in storer calibration equipment of FPGA provided by the invention embodiment mono-, and as shown in Figure 5, this device comprises: acquisition module 501 and correction verification module 502, wherein:
This device is used for carrying out preceding method embodiment, and it realizes principle and beneficial effect is similar, does not repeat them here.
Alternatively, arrange according to number order described the first data and described the first address to be verified, and described initial proof test value and described the first proof test value are arranged according to numbering backward.
Further, whether acquisition module 501 is identical with the figure place of described the first data specifically for judging the figure place of described the first address; If the figure place of described the first address is identical with the figure place of described the first data, using described the first address as the first address to be verified; If the figure place of described the first address is less than the figure place of described the first data, polishing is carried out in described address, obtain the first to be verified address identical with the figure place of described the first data.
On the basis of above-described embodiment, acquisition module 501, also for obtaining primary data and the initial address corresponding to described primary data of the plug-in storer that writes described FPGA; Obtain the initial to be verified address identical with the figure place of described primary data according to described initial address.Correction verification module 502, also, for described primary data and described initial address to be verified are carried out to XOR, obtains initial XOR result; Using described initial XOR result as initial proof test value.
Fig. 6 is the structural representation of the plug-in storer calibration equipment of FPGA provided by the invention embodiment bis-, and on the basis of Fig. 5, as shown in Figure 6, this device also comprises: separate correction verification module 503, read address for generating; According to described address reading out data and proof test value corresponding to described data from the plug-in storer of described FPGA read; Separate exclusive or check according to described proof test value, judge in the plug-in storer of described FPGA whether fault of address and/or data according to described solution exclusive or check result.
Particularly, in the time that described proof test value is arranged according to numbering backward, before separating exclusive or check according to described proof test value, separate correction verification module 503, according to the order that reads described proof test value, the proof test value of reading is carried out to backward.
Fig. 7 is the structural representation of the plug-in storer calibration equipment of FPGA provided by the invention embodiment tri-, and as shown in Figure 7, this device comprises: storer 701 and processor 702, wherein:
Obtain the first data and first address corresponding to described the first data of the plug-in storer that writes on-site programmable gate array FPGA; The first to be verified address identical with the figure place of described the first data according to described the first address acquisition; Described the first data and described the first address to be verified are carried out to XOR, obtain the first XOR result; Described the first XOR result and initial proof test value are carried out to XOR, obtain the first proof test value; Using described the first proof test value as described initial proof test value.
Alternatively, arrange according to number order described the first data and described the first address to be verified, and described initial proof test value and described the first proof test value are arranged according to numbering backward.
Further, whether processor 702 is identical with the figure place of described the first data specifically for judging the figure place of described the first address; If the figure place of described the first address is identical with the figure place of described the first data, using described the first address as the first address to be verified; If the figure place of described the first address is less than the figure place of described the first data, polishing is carried out in described address, obtain the first to be verified address identical with the figure place of described the first data.
Particularly, processor 702, in the time that described proof test value is arranged according to numbering backward, before separating exclusive or check according to described proof test value, according to the order that reads described proof test value, carries out backward by the proof test value of reading.
This device is used for carrying out preceding method embodiment, and it realizes principle and beneficial effect is similar, does not repeat them here.
In several embodiment provided by the present invention, should be understood that disclosed apparatus and method can realize by another way.For example, device embodiment described above is only schematic, for example, the division of described unit, be only that a kind of logic function is divided, when actual realization, can have other dividing mode, for example multiple unit or assembly can in conjunction with or can be integrated into another system, or some features can ignore, or do not carry out.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, indirect coupling or the communication connection of device or unit can be electrically, machinery or other form.
The described unit as separating component explanation can or can not be also physically to separate, and the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed in multiple network element.Can select according to the actual needs some or all of unit wherein to realize the object of the present embodiment scheme.
In addition, the each functional unit in each embodiment of the present invention can be integrated in a processing unit, can be also that the independent physics of unit exists, and also can be integrated in a unit two or more unit.Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form that also can adopt hardware to add SFU software functional unit realizes.
The integrated unit that the above-mentioned form with SFU software functional unit realizes, can be stored in a computer read/write memory medium.Above-mentioned SFU software functional unit is stored in a storage medium, comprise that some instructions (can be personal computers in order to make a computer equipment, server, or the network equipment etc.) or processor (processor) carry out the part steps of method described in each embodiment of the present invention.And aforesaid storage medium comprises: various media that can be program code stored such as USB flash disk, portable hard drive, ROM (read-only memory) (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disc or CDs.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (12)
1. the plug-in storer method of calibration of FPGA, is characterized in that, comprising:
A, on-site programmable gate array FPGA obtain the first data and first address corresponding to described the first data of the plug-in storer that writes described FPGA;
The first address to be verified that B, described FPGA are identical with the figure place of described the first data according to described the first address acquisition;
Described the first data and described the first address to be verified are carried out XOR by C, described FPGA, obtains the first XOR result;
Described the first XOR result and initial proof test value are carried out XOR by D, described FPGA, obtains the first proof test value;
E, described FPGA, using described the first proof test value as described initial proof test value, carry out A-D, until verification finishes.
2. method according to claim 1, is characterized in that, arrange according to number order described the first data and described the first address to be verified, and described initial proof test value and described the first proof test value are arranged according to numbering backward.
3. method according to claim 1, is characterized in that, the first address to be verified that described FPGA is identical with the figure place of described the first data according to described the first address acquisition, comprising:
Described FPGA judges that whether the figure place of described the first address is identical with the figure place of described the first data;
If the figure place of described the first address is identical with the figure place of described the first data, using described the first address as the first address to be verified;
If the figure place of described the first address is less than the figure place of described the first data, polishing is carried out in described address, obtain the first to be verified address identical with the figure place of described the first data.
4. method according to claim 1, is characterized in that, described FPGA also comprises before obtaining the first data of the plug-in storer that writes described FPGA and the first address corresponding to described the first data:
Described FPGA obtains primary data and the initial address corresponding to described primary data of the plug-in storer that writes described FPGA;
Described FPGA obtains the initial to be verified address identical with the figure place of described primary data according to described initial address;
Described primary data and described initial address to be verified are carried out XOR by described FPGA, obtains initial XOR result;
Described FPGA is using described initial XOR result as initial proof test value.
5. method according to claim 1, is characterized in that, after described verification finishes, also comprises:
Described FPGA generates and reads address;
Described in described FPGA basis, read address reading out data and proof test value corresponding to described data from the plug-in storer of described FPGA;
Described FPGA separates exclusive or check according to described proof test value, judges in the plug-in storer of described FPGA whether fault of address and/or data according to described solution exclusive or check result.
6. method according to claim 5, is characterized in that, if described proof test value according to numbering backward arrange,
Described FPGA also comprises before separating exclusive or check according to described proof test value:
Described FPGA, according to the order that reads described proof test value, carries out backward by the proof test value of reading.
7. the plug-in storer calibration equipment of FPGA, is characterized in that, comprising:
Acquisition module, for obtaining the first data and first address corresponding to described the first data of the plug-in storer that writes on-site programmable gate array FPGA; The first to be verified address identical with the figure place of described the first data according to described the first address acquisition;
Correction verification module, for described the first data and described the first address to be verified are carried out to XOR, obtains the first XOR result; Described the first XOR result and initial proof test value are carried out to XOR, obtain the first proof test value; Using described the first proof test value as described initial proof test value.
8. device according to claim 7, is characterized in that, arrange according to number order described the first data and described the first address to be verified, and described initial proof test value and described the first proof test value are arranged according to numbering backward.
9. device according to claim 7, is characterized in that, whether described acquisition module is identical with the figure place of described the first data specifically for judging the figure place of described the first address; If the figure place of described the first address is identical with the figure place of described the first data, using described the first address as the first address to be verified; If the figure place of described the first address is less than the figure place of described the first data, polishing is carried out in described address, obtain the first to be verified address identical with the figure place of described the first data.
10. device according to claim 7, is characterized in that, described acquisition module, also for obtaining primary data and the initial address corresponding to described primary data of the plug-in storer that writes described FPGA; Obtain the initial to be verified address identical with the figure place of described primary data according to described initial address;
Described correction verification module, also, for described primary data and described initial address to be verified are carried out to XOR, obtains initial XOR result; Using described initial XOR result as initial proof test value.
11. devices according to claim 7, is characterized in that, also comprise:
Separate correction verification module, read address for generating; According to described address reading out data and proof test value corresponding to described data from the plug-in storer of described FPGA read; Separate exclusive or check according to described proof test value, judge in the plug-in storer of described FPGA whether fault of address and/or data according to described solution exclusive or check result.
12. devices according to claim 11, is characterized in that, described solution correction verification module, for in the time that described proof test value is arranged according to numbering backward, before separating exclusive or check according to described proof test value, according to the order that reads described proof test value, the proof test value of reading is carried out to backward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410105880.9A CN103838638B (en) | 2014-03-20 | 2014-03-20 | Calibration method and device for FPGA plug-in storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410105880.9A CN103838638B (en) | 2014-03-20 | 2014-03-20 | Calibration method and device for FPGA plug-in storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103838638A true CN103838638A (en) | 2014-06-04 |
| CN103838638B CN103838638B (en) | 2017-04-26 |
Family
ID=50802168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410105880.9A Active CN103838638B (en) | 2014-03-20 | 2014-03-20 | Calibration method and device for FPGA plug-in storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103838638B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373444A (en) * | 2015-11-24 | 2016-03-02 | 北京时代民芯科技有限公司 | EDAC (Error Detection And Correction) check code generation method of 8-bit-width external memory controller |
| CN106681941A (en) * | 2015-11-07 | 2017-05-17 | 上海复旦微电子集团股份有限公司 | Data write-in and data-out method of memory and device |
| CN111555841A (en) * | 2020-04-24 | 2020-08-18 | 中国船舶重工集团海装风电股份有限公司 | Communication data checking method, device, equipment and medium |
| CN114756404A (en) * | 2022-06-15 | 2022-07-15 | 上海江波龙数字技术有限公司 | Data processing method and device, electronic equipment and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908031B (en) * | 2010-07-23 | 2012-11-14 | 四川九洲电器集团有限责任公司 | FPGA-based enhanced serial port |
-
2014
- 2014-03-20 CN CN201410105880.9A patent/CN103838638B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681941A (en) * | 2015-11-07 | 2017-05-17 | 上海复旦微电子集团股份有限公司 | Data write-in and data-out method of memory and device |
| CN105373444A (en) * | 2015-11-24 | 2016-03-02 | 北京时代民芯科技有限公司 | EDAC (Error Detection And Correction) check code generation method of 8-bit-width external memory controller |
| CN105373444B (en) * | 2015-11-24 | 2018-07-06 | 北京时代民芯科技有限公司 | A kind of generation method of 8 bit wide external memory controller EDAC check codes |
| CN111555841A (en) * | 2020-04-24 | 2020-08-18 | 中国船舶重工集团海装风电股份有限公司 | Communication data checking method, device, equipment and medium |
| CN114756404A (en) * | 2022-06-15 | 2022-07-15 | 上海江波龙数字技术有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN114756404B (en) * | 2022-06-15 | 2024-04-05 | 上海江波龙数字技术有限公司 | Data processing method, device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103838638B (en) | 2017-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105706059B (en) | Error correction in nonvolatile memory | |
| US9208021B2 (en) | Data writing method, memory storage device, and memory controller | |
| TWI676991B (en) | Methods for testing a storage unit and apparatuses using the same | |
| CN103473146A (en) | Memory control method, memory controller and electronic device | |
| TW201601163A (en) | Method for controlling a memory apparatus, and associated memory apparatus thereof and associated controller thereof | |
| CN106205728B (en) | Parity check circuit and memory device including the same | |
| CN105556477B (en) | The method and system communicated with the memory module of host-processor | |
| CN103019880A (en) | Data verification method, storage device and storage system | |
| CN103532854A (en) | Storage and forwarding method and device of message | |
| CN103513937A (en) | Storage device capable of increasing its life cycle and operating method thereof | |
| CN103838638A (en) | Calibration method and device for FPGA plug-in storage | |
| CN105183579A (en) | Data check method and device and electronic equipment | |
| US10741212B2 (en) | Error correction code (ECC) encoders, ECC encoding methods capable of encoding for one clock cycle, and memory controllers including the ECC encoders | |
| CN103631670A (en) | Storage device of storage, storage controller and data processing method | |
| CN106653083A (en) | Semiconductor memory device and operating method thereof | |
| CN104182293A (en) | Data writing method, memory storage device and memory controller | |
| CN102890645A (en) | Memory storage device, memory controller and data writing method | |
| CN103544121A (en) | Method, device and system based on micro service system management slot numbers | |
| TWI536749B (en) | Decoding method, memory storage device and memory controlling circuit unit | |
| CN115203099A (en) | System including PIPE 5-to-PIPE 4 converter and method thereof | |
| CN105335679A (en) | Serial number writing-in method and device | |
| TWI732642B (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| CN103399827B (en) | The system and method for memory storage, execution accessing operation | |
| TWI514141B (en) | Memory address management method, memory controller and memory storage device | |
| CN106815088A (en) | server and its debugging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211228 Address after: 450046 Floor 9, building 1, Zhengshang Boya Plaza, Longzihu wisdom Island, Zhengdong New Area, Zhengzhou City, Henan Province Patentee after: Super fusion Digital Technology Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |