CN103832970B - A kind of low-temperature wafer bonding method - Google Patents
A kind of low-temperature wafer bonding method Download PDFInfo
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- CN103832970B CN103832970B CN201210491190.2A CN201210491190A CN103832970B CN 103832970 B CN103832970 B CN 103832970B CN 201210491190 A CN201210491190 A CN 201210491190A CN 103832970 B CN103832970 B CN 103832970B
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Abstract
The invention discloses a kind of low-temperature wafer bonding method, including: two wafers are carried out; Two crystal column surface one layer of oxides of deposition after cleaning; At least one in two wafers is carried out surface activation process; Being contacted relative to each other at non-vacuum environment lower surface and apply external force by two wafers after surface activation process makes it be bonded; And the wafer after para-linkage carries out process annealing process.
Description
Technical field
The present invention relates to wafer bond techniques field, especially a kind of low-temperature wafer bonding method, at least one in two wafers can have device that is that processed or that can process at least partly in the method. The method of this preparation is for the integrated wafer bond techniques of silicon and non-silicon-based cmos device, IC device, photoelectric device.
Background technology
Along with the development of integrated circuit, insulator silicon (SOI) technology is known as one of era of nanotechnology solution replacing existing single crystal silicon material by industry, is the big sharp weapon maintaining Moore's Law tendency.
SOI material is the basis of SOI technology development, and high-quality SOI material is always up restriction SOI technology and enters the primary factor of large-scale industrial production. In recent years, along with the continuous maturation of SOI material preparation technology, the problem of materials of restriction SOI technology development is just progressively solved. The technology of preparing of SOI material includes two kinds after all, namely with ion implanting be representative injection oxygen isolation technology (Sepration-by-oxygenimplantation, i.e. SIMOX) and wafer bond techniques.
SIMOX technology needs high temperature tension and the annealing of follow-up superhigh temperature, and SIMOX material can be had damage by this technology. Owing to the stability of quality of materials there is no guarantee that so that cost is increasing. Wafer bond techniques is the technology that same SIMOX synchronized development gets up, and both each lay particular emphasis on different application demand. Wafer bond techniques (WaferBonding) is that the crystal column surface utilizing two panels bright finished, clean combines. When adopting wafer bonding and thinning technique to form soi structure, not only have technique simple, with low cost, to advantages such as device not damageds, and the SOI material prepared still has good characteristic. Wafer current bonding techniques mainly includes anode linkage, silicon direct bonding, eutectic bonding, thermocompression bonding, metal bonding, glass solder bonding etc., above-mentioned wafer bond techniques is directed to the high temperature anneal, process time is long, MEMS performance is adversely affected by the high temperature produced in bonding process, and the temperature-sensitive circuit on wafer and micro structure are caused cause thermal damage (as CMOS aluminum circuit will be damaged by the high temperature more than 400 DEG C) by such as high temperature; High temperature is easily introduced impurity, causes the redistribution that substrate adulterates; For two wafers that thermal expansion coefficient difference is bigger, very big deformation and residual thermal stress can be caused after high-temperature process, directly influence device performance and encapsulation yield rate.
Proposing the thought of low-temperature wafer bonding in recent years, low-temperature wafer bonding mainly has solder bonding, viscose bonding, surface-activated bond etc.But owing to the bond strength of viscose bonding and solder bonding is relatively low, device uses temperature limited, and application is very limited. And although the low-temperature surface activated bond bonding technology time is long, but due to surface activation process and process annealing, so that bond strength disclosure satisfy that follow-up element manufacturing.
The development of MEMS and photoelectric technology, three-dimensionally integrated and system encapsulation are proposed new requirement, and research disclosure satisfy that the bigger homogeneity of coefficient of thermal expansion differences or two heterogeneous backing material bondings require and device becomes without the new low-temperature wafer bonding techniques damaged after bonding the certainty of technical development.
Summary of the invention
(1) to solve the technical problem that
In view of this, present invention is primarily targeted at the defect overcoming prior art, it is provided that the method for a kind of low-temperature wafer bonding, bonding backing material between smooth to meet any two so that bonding techniques is not by the impact of backing material character.
(2) technical scheme
For reaching above-mentioned purpose, the invention provides a kind of low-temperature wafer bonding method, including: two wafers are carried out; Two crystal column surface one layer of oxides of deposition after cleaning; At least one in two wafers is carried out surface activation process; Being contacted relative to each other at non-vacuum environment lower surface and apply external force by two wafers after surface activation process makes it be bonded; And the wafer after para-linkage carries out process annealing process.
In such scheme, in the described step that two wafers are carried out, adopt chemical cleaning method.
In such scheme, described two wafers are carried out after also include: two wafers are cleaned and/or are polished.
In such scheme, in the step of described two crystal column surface one layer of oxides of deposition after cleaning, described deposition adopts MOCVD, PECVD, ALD, sputtering, means of electron beam deposition or pulse laser deposition, and described oxide is the one in silicon oxide, aluminium oxide, hafnium oxide or lanthana.
In such scheme, in the described step that at least one in two wafers carries out surface activation process, described surface activation process is to adopt O2、N2、SF6A kind of surface activation process that at least one in two wafers is carried out in plasma-activated process, or adopt O2、N2、SF6Multiple in plasma-activated process successively at least one in two wafers is carried out surface activation process.
In such scheme, in the described step that at least one in two wafers carries out surface activation process, described surface activation process is to carry out in the temperature range of 16 DEG C-26 DEG C.
In such scheme, described contacting and apply in the step that external force makes it be bonded by two wafers after surface activation process relative to each other at non-vacuum environment lower surface, non-vacuum environment refers to air ambient or the environment of thousand grades of ultra-clean chambers.
In such scheme, described two wafers after surface activation process are contacted and apply in the step that external force makes it be bonded at non-vacuum environment lower surface relative to each other, the bonding pressure adopted is 100Kg-1000kg, it is preferable that described bonding pressure is 200kg-500kg.
In such scheme, the wafer after described para-linkage carries out in the step of process annealing process, and the annealing temperature of employing is 100 DEG C-400 DEG C.
(3) beneficial effect
Compared with existing wafer bond techniques, present invention have the advantage that
1, owing to bonding region is oxide, so low-temperature wafer bonding method provided by the invention can be bonded any two substrate or device.
2, low-temperature wafer bonding method provided by the invention, adopts low-temperature wafer bonding techniques, it is to avoid the destruction of temperature sensitive circuit and micro structure, and efficiency is high.
3, low-temperature wafer bonding method provided by the invention, it is not necessary to complete under vacuum or low vacuum environment, and the extruding force needed when bonding is smaller.
Accompanying drawing explanation
Fig. 1 is the method flow diagram being bonded according to the low-temperature wafer of the embodiment of the present invention;
Fig. 2 is the schematic diagram of the wafer before bonding according to the embodiment of the present invention;
Fig. 3 is the process chart before bonding according to the embodiment of the present invention, and wherein Fig. 3 (a) is flow chart of steps, and Fig. 3 (b) is the effect schematic diagram corresponding with step shown in Fig. 3 (a).
Fig. 4 is according to the structural representation after the wafer bonding of the embodiment of the present invention.
Fig. 5 is according to the ultrasonic scanning figure after the wafer bonding of the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
This low-temperature wafer bonding method provided by the invention, first two wafers are carried out, then oxide layer one layer thin is deposited at the bonding region of two plates respectively, and the oxide layer of deposition at least a part of which one wafer is carried out surface activation process, the oxide layer of handle well two wafers is sticked together relatively, finally send into bonder and apply extruding force, thus realizing the bonding of two wafers.
As it is shown in figure 1, Fig. 1 illustrates that the method comprises the following steps according to the method flow diagram that the low-temperature wafer of the embodiment of the present invention is bonded:
Step 1: two wafers are carried out; In this step, adopt chemical cleaning method that two wafers are carried out, specifically include: utilize organic solvent (isopropanol, dehydrated alcohol, methanol or acetone) to wash surface and oil contaminant, the method utilizing ultrasonic cleaning removes the adsorption particle on surface, then utilizes the method for pickling to get rid of metal ion and stains.
Additionally, also include after two wafers are carried out: two wafers are cleaned and/or polished, specifically include: (be typically larger than 2nm) when the roughness of crystal column surface is bigger, it is generally required to carry out surface chemical mechanical polishing polishing so that it is surface roughness reaches to be suitable for the demand (being typically smaller than 1nm) of bonding chip.
Step 2: two crystal column surface one layer of oxides of deposition after cleaning; At least one in two wafers is carried out surface activation process; In this step, described deposition adopts MOCVD, PECVD, ALD, sputtering, means of electron beam deposition or pulse laser deposition, and described oxide is the one in silicon oxide, aluminium oxide, hafnium oxide or lanthana; Described surface activation process is to adopt O2、N2、SF6A kind of surface activation process that at least one in two wafers is carried out in plasma-activated process, or adopt O2、N2、SF6Multiple in plasma-activated process successively at least one in two wafers is carried out surface activation process; Described surface activation process is at room temperature to carry out, it is preferred that carry out in the temperature range of 16 DEG C-26 DEG C.
Step 3: two wafers after surface activation process are contacted relative to each other at non-vacuum environment lower surface and apply external force make it be bonded; In this step, non-vacuum environment refers to air ambient or the environment of thousand grades of ultra-clean chambers, and the bonding pressure of employing is 100Kg-1000kg, it is preferable that described bonding pressure is 200kg-500kg.
Step 4: the wafer after para-linkage carries out process annealing process; In this step, the annealing temperature of employing is 100 DEG C-400 DEG C.
Fig. 2 to Fig. 4 illustrates according to the process chart that the low-temperature wafer of the embodiment of the present invention is bonded.
As in figure 2 it is shown, the former substrate 1 being used for being bonded is Silicon Wafer, former substrate 2 is gaas wafer.
As it is shown on figure 3, substrate 1 and substrate 2 before bonding through a series of process, including cleaning, deposition oxide, surface activation process. For the substrate 1 RCA cleaning method improved, substrate 2 then uses simple cleaning method. With method one layer of oxide 3 of deposition of ALD on clean substrate 1 after cleaning and substrate 2, oxide 3 is aluminium oxide. Followed by O2Plasma, carries out activation processing followed by N2 plasma on oxide 3 surface.
Manually two good crystal column surfaces handled by Fig. 3 are sticked together relatively under the environment of thousand grades of ultra-clean chambers as shown in Figure 4, be then placed in bonder and apply certain extruding force. Wafer after extruding is to needing the temperature (such as 100 DEG C-400 DEG C) being placed in annealing furnace with suitable to be annealed.
As it is shown in figure 5, the ultrasonic scanning figure after bonding shows: when the power of oxygen gas plasma activation is 100W, and the power of nitrogen gas plasma activation is 100W, effective bonding area accounts for the 98% of whole area.
Particular embodiments described above; the purpose of the present invention, technical scheme and beneficial effect have been further described; it is it should be understood that; the foregoing is only specific embodiments of the invention; it is not limited to the present invention; all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (9)
1. a low-temperature wafer bonding method, it is characterised in that including:
Two wafers are carried out;
Two crystal column surface one layer of oxides of deposition after cleaning, described oxide is the one in aluminium oxide, hafnium oxide or lanthana;
At least one in two wafers is carried out surface activation process, and described surface activation process is to adopt O2、N2、SF6At least one in two wafers is carried out surface activation process by multiple in plasma-activated process successively;
Being contacted relative to each other at non-vacuum environment lower surface and apply external force by two wafers after surface activation process makes it be bonded; And
Wafer after para-linkage carries out process annealing process.
2. low-temperature wafer bonding method according to claim 1, it is characterised in that in the described step that two wafers are carried out, adopts chemical cleaning method.
3. low-temperature wafer bonding method according to claim 1, it is characterised in that described two wafers are carried out after also include:
Two wafers are cleaned and/or polished.
4. low-temperature wafer bonding method according to claim 1, it is characterized in that, in the step of described two crystal column surface one layer of oxides of deposition after cleaning, described deposition adopts MOCVD, PECVD, ALD, sputtering, means of electron beam deposition or pulse laser deposition.
5. low-temperature wafer bonding method according to claim 1, it is characterised in that in the described step that at least one in two wafers carries out surface activation process, described surface activation process is to carry out in the temperature range of 16 DEG C-26 DEG C.
6. low-temperature wafer bonding method according to claim 1, it is characterized in that, described contacting and apply in the step that external force makes it be bonded by two wafers after surface activation process relative to each other at non-vacuum environment lower surface, non-vacuum environment refers to air ambient or the environment of thousand grades of ultra-clean chambers.
7. low-temperature wafer bonding method according to claim 1, it is characterized in that, described contacting and apply in the step that external force makes it be bonded by two wafers after surface activation process relative to each other at non-vacuum environment lower surface, the bonding pressure of employing is 100Kg-1000kg.
8. low-temperature wafer bonding method according to claim 7, it is characterised in that described bonding pressure is 200kg-500kg.
9. low-temperature wafer bonding method according to claim 1, it is characterised in that the wafer after described para-linkage carries out in the step of process annealing process, the annealing temperature of employing is 100 DEG C-400 DEG C.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105185720B (en) * | 2015-08-03 | 2018-05-08 | 武汉新芯集成电路制造有限公司 | A kind of ultra-thin thermal oxide wafer bonding technique for strengthening bond strength |
| CN105206536B (en) * | 2015-08-17 | 2018-03-09 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method and structure for strengthening bond strength |
| CN105118804B (en) * | 2015-09-29 | 2018-04-13 | 厦门大学 | The method that ultra-thin silicon thin film passivation prepares germanium on insulator |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| CN107633997B (en) | 2017-08-10 | 2019-01-29 | 长江存储科技有限责任公司 | A kind of wafer bonding method |
| CN108288582B (en) * | 2018-01-11 | 2020-12-01 | 北京华碳科技有限责任公司 | Wafer-level GaN device substrate transfer method |
| CN108365083B (en) * | 2018-02-07 | 2022-03-08 | 济南晶正电子科技有限公司 | Method for manufacturing composite piezoelectric substrate for surface acoustic wave device |
| CN109346495A (en) * | 2018-11-21 | 2019-02-15 | 德淮半导体有限公司 | Wafer bonding method |
| CN110164894A (en) * | 2019-05-28 | 2019-08-23 | 上海华力微电子有限公司 | A kind of bonding method |
| CN110148603B (en) * | 2019-05-28 | 2021-05-07 | 上海华力微电子有限公司 | Method for manufacturing back-illuminated CMOS optical sensor |
| CN110289209A (en) * | 2019-07-05 | 2019-09-27 | 长春长光圆辰微电子技术有限公司 | A kind of processing method of SOI wafer |
| CN110993607B (en) * | 2019-11-21 | 2022-12-16 | 长江存储科技有限责任公司 | Memory device with barrier structure and preparation method thereof |
| CN117174728B (en) * | 2023-11-02 | 2024-02-20 | 合肥新晶集成电路有限公司 | Wafer processing method and wafer structure |
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| DE602004013163T2 (en) * | 2004-11-19 | 2009-05-14 | S.O.I. Tec Silicon On Insulator Technologies S.A. | Method of Making a Germanium On Insulator Wafer (GeOI) |
| JP5391599B2 (en) * | 2008-07-14 | 2014-01-15 | オムロン株式会社 | Substrate bonding method and electronic component |
| JP5496598B2 (en) * | 2008-10-31 | 2014-05-21 | 信越化学工業株式会社 | Manufacturing method of silicon thin film transfer insulating wafer |
| CN101740421B (en) * | 2008-11-17 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Wafer and manufacturing method, system-level package structure and package method thereof |
| US8748885B2 (en) * | 2012-02-10 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Soft material wafer bonding and method of bonding |
| CN102610553A (en) * | 2012-03-20 | 2012-07-25 | 北京大学 | Preparation method for Ge-on-insulator substrate |
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