CN103825488B - Single-phase six switches set MMC inverter and the control methods thereof of dual output - Google Patents

Abstract

The invention discloses single-phase six switches set MMC inverter and the control methods thereof of dual output。The inverter of the present invention includes DC source, the first brachium pontis, the second brachium pontis, the first load and the second load；Described first brachium pontis and the second brachium pontis are in series by upper switches set, breaker in middle group, lower switches set and coupling inductance；The two ends of the first load are coupled with the breaker in middle group of the first brachium pontis and the upper end of the breaker in middle group of the second brachium pontis, and the two ends of the second load are coupled with the breaker in middle group of the first brachium pontis and the lower end of the breaker in middle group of the second brachium pontis。This inverter adopts phase-shifting carrier wave PWM to control, and has the exchange output of two-way 2N+1 level, and the voltage stress that in power switch unit, each switching tube bears is only the 1/N of direct current power source voltage, is suitable for the occasion of high pressure, load high-power, double; two。The former and deputy limit of the former secondary of coupling inductance of the first brachium pontis and the coupling inductance of the second brachium pontis all can be substituted by the first inductance and two separate inductors of the second inductance。

Description

Single-phase six switches set MMC inverter and the control methods thereof of dual output

Technical field

The present invention relates to block combiner many level (MMC) changer field, be specifically related to a kind of single-phase six switches set MMC inverter and control methods thereof of dual output。

Background technology

Current power inverter forward miniaturization, high reliability and low-loss direction are developed, and occur the direction of two kinds of improvement changers under this trend: reduce passive device or improve converter topology structure to reduce the active device new development as minimizing active device direction。Single-phase six switch converters decrease a switch and corresponding drive circuit relative to eight traditional switch converters, occupy certain advantage in considering the cost application with volume。But, the single-phase output of two-way of six switch converters is two level, and output AC waveform comparison is poor。Additionally, the half that voltage stress is DC bus-bar voltage that in six switches, each switch bears, and there are six voltage-sharings switched, this significantly limit the application at high pressure and large-power occasions of single-phase six switch converters。

In recent years, multilevel technology is constantly promoted, and it being successfully applied in the industrial circles such as such as D.C. high voltage transmission, Electric Drive, active power filtering, Static Synchronous compensation, voltage-type multi-level converter topology common at present is broadly divided into case bit-type and the big class of unit cascaded type two。Block combiner multi-level converter (ModularMultilevelConverter, MMC) as a kind of novel many level topology, except having the advantage of traditional multi-level changer, block combiner multi-level converter adopts Modular Structure Design, it is simple to System Expansion and redundancy of effort；Having off-center operation ability, fault traversing and recovery capability, system reliability is high；Owing to having common DC bus, block combiner multi-level converter is particularly suited for HVDC transmission system application。But, when alternating current circuit connected of two different frequencies, it is necessary to 2 MMC changers, this significantly increases engineering cost。

Summary of the invention

It is an object of the invention to overcome above-mentioned the deficiencies in the prior art, it is proposed to a kind of single-phase six switches set MMC inverter and control methods thereof of dual output。

The technical solution used in the present invention is as follows。

The single-phase six switches set MMC inverter of dual output include DC source, the first brachium pontis, the second brachium pontis, the first load and the second load；Described first brachium pontis and the second brachium pontis are in series by upper switches set, breaker in middle group, lower switches set and coupling inductance；The upper switches set of the first brachium pontis is in series by N number of power switch unit, the breaker in middle group of the first brachium pontis is in series by N number of power switch unit, the lower switches set of the first brachium pontis is in series by N number of power switch unit, the upper switches set of the second brachium pontis is in series by N number of power switch unit, the breaker in middle group of the second brachium pontis is in series by N number of power switch unit, and the lower switches set of the second brachium pontis is in series by N number of power switch unit；The two ends of the first load are coupled with the breaker in middle group of the first brachium pontis and the upper end of the breaker in middle group of the second brachium pontis, and the two ends of the second load are coupled with the breaker in middle group of the first brachium pontis and the lower end of the breaker in middle group of the second brachium pontis；The two ends of the first load export as the first via, and the two ends of the second load export as the second tunnel。The former and deputy limit of the former secondary of coupling inductance of the first brachium pontis and the coupling inductance of the second brachium pontis all can be substituted by the first inductance and two separate inductors of the second inductance。

Further, in the single-phase six switches set MMC inverter of described dual output, the positive pole of DC source and the upper end of upper switches set of the first brachium pontis, the second brachium pontis the upper end of upper switches set connect, the lower end connection of the negative pole of DC source and the lower end of lower switches set of the first brachium pontis, the lower switches set of the second brachium pontis；The lower end of the upper switches set of the first brachium pontis is connected with the Same Name of Ends on the former limit of the coupling inductance of the first brachium pontis, the upper end of the non-same polarity on the former limit of the coupling inductance of the first brachium pontis and the breaker in middle group of the first brachium pontis connects, the lower end of the breaker in middle group of the first brachium pontis is connected with the Same Name of Ends of the coupling inductance secondary of the first brachium pontis, and the upper end of the non-same polarity of the coupling inductance secondary of the first brachium pontis and the switches set of the first brachium pontis connects；The structure of the second brachium pontis is completely the same with the structure of the first brachium pontis；The negative pole of DC source and the lower end of lower switches set of the first brachium pontis, the second brachium pontis lower switches set lower end, hold connection；One end of first load is connected with the upper end of the breaker in middle group of the first brachium pontis, the upper end of the other end of the first load and the breaker in middle group of the second brachium pontis connects, one end of second load is connected with the lower end of the breaker in middle group of the first brachium pontis, and the lower end of the other end of the second load and the breaker in middle group of the second brachium pontis connects。

Further, power switch unit includes the first switching tube, second switch pipe, the first diode, the second diode and electric capacity。Wherein, the negative electrode of the positive pole of electric capacity and the colelctor electrode of the first switching tube, the first diode connects, the emitter stage of the first switching tube and the anode of the first diode, the colelctor electrode of second switch pipe, the second diode negative electrode connect, the negative pole connection of the emitter stage of second switch pipe and the anode of the second diode, electric capacity；The colelctor electrode of second switch pipe is as the first outfan, and the emitter stage of second switch pipe is as the second outfan。

Second outfan of the i-th power switch unit of each switches set is connected with the first outfan of i+1 power switch unit, and wherein the value of i is 1～N-1。

The control method of above-mentioned inverter includes: employing phase-shifting carrier wave PWM controls opening and shutoff of the switching tube of each switches set；The i-th power switch unit of the lower switches set of the i-th power switch unit of the upper switches set of the first brachium pontis, the i-th power switch unit of lower switches set of the first brachium pontis, the i-th power switch unit of upper switches set of the second brachium pontis and the second brachium pontis adopts identical triangular wave as i-th carrier wave C_i, wherein the value of i is 1～N；N number of carrier wave is 360 °/N of lagging phase angle successively；The upper switches set of the first brachium pontis adopts primary sinusoid R_a1Superposition the first direct current biasing R_doaThe first modulating wave R as the first brachium pontis_a1+R_doa, the lower switches set of the first brachium pontis adopts the second sinusoidal wave R_b1Superposition the second direct current biasing R_dobThe second modulating wave R as the first brachium pontis_b1+R_dob, the upper switches set of the second brachium pontis adopts the 3rd sinusoidal wave R_a2Superposition the first direct current biasing R_doaThe first modulating wave R as the second brachium pontis_a2+R_doa, the lower switches set of the second brachium pontis adopts the 4th sinusoidal wave R_b2Superposition the second direct current biasing R_dobThe second modulating wave R as the second brachium pontis_b2+R_dob；Primary sinusoid R_a1With the 3rd sinusoidal wave R_a2Frequency is identical and phase contrast is 180 °, the second sinusoidal wave R_b1With the 4th sinusoidal wave R_b2Frequency is identical and phase contrast is 180 °。

In above-mentioned control method, the first modulating wave R of the first brachium pontis_a1+R_doaWith i-th carrier wave C_iThe control level of the second switch pipe gate pole of the i-th power switch unit of the upper switches set of the first brachium pontis is obtained, as the first modulating wave modulating wave R of the first brachium pontis by the first comparator_a1+R_doaMore than i-th carrier wave C_iTime, the first comparator output high level, as the first modulating wave modulating wave R of the first brachium pontis_a1+R_doaLess than i-th carrier wave C_iTime, the first comparator output low level, wherein the value of i is 1～N；Second modulating wave R of the first brachium pontis_b1+R_dobWith i-th carrier wave C_iThe control level of the second switch pipe gate pole of the i-th power switch unit of the lower switches set of the first brachium pontis is obtained, as the second modulating wave R of the first brachium pontis by the second comparator_b1+R_dobLess than i-th carrier wave C_iTime, the second comparator output high level, as the second modulating wave R of the first brachium pontis_b1+R_dobMore than i-th carrier wave C_iTime, the second comparator output low level；The control level of the second switch pipe gate pole of the i-th power switch unit of the control level of the second switch pipe gate pole of the i-th power switch unit of the upper switches set of the first brachium pontis and the lower switches set of the first brachium pontis obtains the control level of second switch pipe gate pole in the i-th power switch unit of the breaker in middle group of the first brachium pontis by the first XOR gate；First modulating wave R of the second brachium pontis_a2+R_doaWith i-th carrier wave C_iObtained by the 3rd comparator the second brachium pontis upper switches set i-th power switch unit in the control level of second switch pipe gate pole, as the first modulating wave R of the second brachium pontis_a2+R_doaMore than i-th carrier wave C_iTime, the 3rd comparator output high level, as the first modulating wave R of the second brachium pontis_a2+R_doaLess than i-th carrier wave C_iTime, the 3rd comparator output low level；Second modulating wave R of the second brachium pontis_b2+R_dobWith i-th carrier wave C_iThe control level of the second switch pipe gate pole of the i-th power switch unit of switches set under the second brachium pontis is obtained, as the second modulating wave R of the second brachium pontis by the 4th comparator_b2+R_dobLess than i-th carrier wave C_iTime, the 4th comparator output high level, as the second modulating wave R of the second brachium pontis_b2+R_dobMore than i-th carrier wave C_iTime, the 4th comparator output low level；The control level of the control level of second switch pipe gate pole in the i-th power switch unit of the upper switches set of the second brachium pontis and the second switch pipe gate pole of the i-th power switch unit of switches set under the second brachium pontis obtains the control level of the second switch pipe gate pole of the i-th power switch unit of the breaker in middle group of the second brachium pontis by the second XOR gate；In each power switch unit of each switches set the control level of second switch pipe gate pole anti-phase after obtain the control level of the first switching tube gate pole in this power switch unit。

The mode of operation of the single-phase six switches set MMC inverter of dual output includes with frequency pattern (CF pattern) and alien frequencies pattern (DF pattern), and in CF pattern, first via output is identical with the electric voltage frequency of the second tunnel output, and voltage magnitude differs；In DF pattern, first via output is all different from the electric voltage frequency of the second tunnel output and amplitude。

Compared with prior art, the present invention have the advantage that for: have two-way 2N+1 level exchange output, output current wave is of high quality, the voltage stress that in power switch unit, each switching tube bears is only the 1/N of DC bus-bar voltage, can guarantee that the voltage that in changer work process, all switching tubes bear is equal simultaneously, well solve the voltage-sharing of switching tube。Compared with existing single-phase six switch converters, the two-way output of the single-phase six switches set MMC inverter of dual output provided by the present invention is the exchange output of 2N+1 level, and the quality of output AC waveform is greatly improved。In addition, the voltage stress born of each switching tube is only the 1/N of DC bus-bar voltage, and control method provided by the present invention makes the voltage that in changer work process, all switching tubes bear equal, well solving the voltage-sharing of switching tube, this will be very beneficial for the application at high pressure and large-power occasions of the dual output single-phase six switches set MMC inverter。Compared with existing MMC changer, the single-phase six switches set MMC inverter of dual output provided by the present invention have two-way exchange output, can be directly used for being connected of the alternating current circuit of two different frequencies, greatly reduce engineering cost。

Accompanying drawing explanation

Fig. 1 is the circuit structure diagram of the single-phase six switches set MMC inverter of dual output of the present invention；

Fig. 2 is the circuit structure diagram of the power switch unit of the single-phase six switches set MMC inverter of the dual output shown in Fig. 1；

Fig. 3 is the phase-shifting carrier wave PWM control structure figure of the single-phase six switches set MMC inverter of the dual output shown in Fig. 1；

Fig. 4 a, 4b are that the single-phase six switches set MMC inverter of the dual output shown in Fig. 1 work in the modulating wave under CF pattern and DF pattern respectively；

Fig. 5 a, 5b are the simulation waveform figure that the single-phase five level SS-MMC inverters of dual output work in CF pattern and DF pattern。

Detailed description of the invention

For present disclosure and feature are expanded on further, below in conjunction with accompanying drawing, the enforcement of the present invention is specifically described, but the enforcement of the present invention is not limited to this。

With reference to Fig. 1, the single-phase six switches set MMC inverter of dual output of the present invention, including DC source U_dc, the first brachium pontis, the second brachium pontis, the first load and the second load；Described first brachium pontis and the second brachium pontis are by upper switches set (H₁、H₂), breaker in middle group (M₁、M₂), lower switches set (L₁、L₂) and coupling inductance (L_H1:L_L1、L_H2:L_L2) be in series；The upper switches set H of the first brachium pontis₁By N number of power switch unit (SM_H11、SM_H12、…、SM_H1N) be in series, the breaker in middle group M of the first brachium pontis₁By N number of power switch unit (SM_M11、SM_M12、…、SM_M1N) be in series, the lower switches set L of the first brachium pontis₁By N number of power switch unit (SM_L11、SM_L12、…、SM_L1N) be in series, the upper switches set H of the second brachium pontis₂By N number of power switch unit (SM_H21、SM_H22、…、SM_H2N) be in series, the breaker in middle group M of the second brachium pontis₂By N number of power switch unit (SM_M21、SM_M22、…、SM_M2N) be in series, the lower switches set L of the second brachium pontis₂By N number of power switch unit (SM_L21、SM_L22、…、SM_L2N) be in series；The two ends of the first load are coupled with the breaker in middle group (M of the first brachium pontis₁) and the breaker in middle group M of the second brachium pontis₂Upper end o, the two ends of the second load are coupled with the breaker in middle group M of the first brachium pontis₁Breaker in middle group M with the second brachium pontis₂Lower end p；The two ends of the first load export as the first via, and the two ends of the second load export as the second tunnel。Wherein, DC source U_dcPositive pole and the upper switches set H of the first brachium pontis₁Upper end o, the second brachium pontis upper switches set H₂Upper end o connect, DC source U_dcNegative pole and the lower switches set L of the first brachium pontis₁Lower end p, the second brachium pontis lower switches set L₂Lower end p connect；The upper switches set H of the first brachium pontis₁Lower end p and the coupling inductance (L of the first brachium pontis_H1:L_L1) former limit L_H1Same Name of Ends w₁Connect, the coupling inductance (L of the first brachium pontis_H1:L_L1) former limit L_H1Non-same polarity a₁Breaker in middle group M with the first brachium pontis₁Upper end o connect, the breaker in middle group M of the first brachium pontis₁Lower end p and the coupling inductance (L of the first brachium pontis_H1:L_L1) secondary L_L1Same Name of Ends b₁Connect, the coupling inductance (L of the first brachium pontis_H1:L_L1) secondary L_L1Non-same polarity z₁Switches set L with the first brachium pontis₁Upper end o connect；The structure of the second brachium pontis is completely the same with the structure of the first brachium pontis；DC source U_dcNegative pole and the lower switches set L of the first brachium pontis₁Lower end p, the second brachium pontis lower switches set L₂Lower end p, hold n to connect；The breaker in middle group M of one end of the first load and the first brachium pontis₁Upper end o connect, the other end of the first load and the breaker in middle group M of the second brachium pontis₂Upper end o connect, the breaker in middle group M of one end of the second load and the first brachium pontis₁Lower end p connect, the other end of the second load and the breaker in middle group M of the second brachium pontis₂Lower end p connect。

Fig. 2 illustrates the circuit structure of the power switch unit of the single-phase six switches set MMC inverter of the dual output shown in Fig. 1, including the first switching tube S₁, second switch pipe S₂, the first diode D₁, the second diode D₂With electric capacity C_SM。Wherein, electric capacity C_SMPositive pole and the first switching tube S₁Colelctor electrode, the first diode D₁Negative electrode connect, the first switching tube S₁Emitter stage and the first diode D₁Anode, second switch pipe S₂Colelctor electrode, the second diode D₂Negative electrode connect, second switch pipe S₂Emitter stage and the second diode D₂Anode, electric capacity C_SMNegative pole connect；Second switch pipe S₂Colelctor electrode as the first outfan, second switch pipe S₂Emitter stage as the second outfan。

As it is shown in figure 1, the second outfan of the i-th power switch unit of each switches set is connected with the first outfan of i+1 power switch unit, wherein the value of i is 1～N-1。

As it is shown in figure 1, the voltage u at the first load two ends_aVoltage u with the second load two ends_bFor

$\left\{\begin{array}{c}{u}_a=\frac{u_{L2}+u_{M2}-u_{H2}}{2}-\frac{u_{L1}+u_{M1}-u_{H1}}{2}\\ u_b=\frac{u_{L2}-u_{M2}-u_{H2}}{2}-\frac{u_{L1}-u_{M1}-u_{H1}}{2}\end{array}\right.$

In formula, u_H1It is the upper switches set H of the first brachium pontis₁Output voltage, u_M1It is the breaker in middle group M of the first brachium pontis₁Output voltage, u_L1It is the lower switches set L of the first brachium pontis₁Output voltage, u_H2It is the upper switches set H of the second brachium pontis₂Output voltage, u_M2It is the breaker in middle group M of the second brachium pontis₂Output voltage, u_L2It is the lower switches set L of the second brachium pontis₂Output voltage。

The single-phase six switches set MMC inverter of dual output shown in Fig. 1 adopt phase-shifting carrier wave PWM to control, as shown in Figure 3。

The upper switches set H of the first brachium pontis₁I-th power switch unit SM_H1i, the first brachium pontis lower switches set L₁I-th power switch unit SM_L1i, the second brachium pontis upper switches set H₂I-th power switch unit SM_H2iLower switches set L with the second brachium pontis₂I-th power switch unit SM_L2iAdopt identical triangular wave as i-th carrier wave C_i, wherein the value of i is 1～N；N number of carrier wave C₁、C₂、…、C_N360 °/N of lagging phase angle successively；The upper switches set H of the first brachium pontis₁Adopt primary sinusoid R_a1Superposition the first direct current biasing R_doaThe first modulating wave R as the first brachium pontis_a1+R_doa, the lower switches set L of the first brachium pontis₁Adopt the second sinusoidal wave R_b1Superposition the second direct current biasing R_dobThe second modulating wave R as the first brachium pontis_b1+R_dob, the upper switches set H of the second brachium pontis₂Adopt the 3rd sinusoidal wave R_a2Superposition the first direct current biasing R_doaThe first modulating wave R as the second brachium pontis_a2+R_doa, the lower switches set L of the second brachium pontis₂Adopt the 4th sinusoidal wave R_b2Superposition the second direct current biasing R_dobThe second modulating wave R as the second brachium pontis_b2+R_dob；Primary sinusoid R_a1With the 3rd sinusoidal wave R_a2Frequency is identical and phase contrast is 180 °, the second sinusoidal wave R_b1With the 4th sinusoidal wave R_b2Frequency is identical and phase contrast is 180 °。

First modulating wave R of the first brachium pontis_a1+R_doaWith i-th carrier wave C_iThe upper switches set H of the first brachium pontis is obtained by the first comparator₁I-th power switch unit SM_H1iSecond switch pipe S₂The control level S of gate pole_H1i, as the first modulating wave modulating wave R of the first brachium pontis_a1+R_doaMore than i-th carrier wave C_iTime, the first comparator output high level, as the first modulating wave modulating wave R of the first brachium pontis_a1+R_doaLess than i-th carrier wave C_iTime, the first comparator output low level, wherein the value of i is 1～N；Second modulating wave R of the first brachium pontis_b1+R_dobWith i-th carrier wave C_iThe lower switches set L of the first brachium pontis is obtained by the second comparator₁I-th power switch unit SM_L1iSecond switch pipe S₂The control level S of gate pole_L1i, as the second modulating wave R of the first brachium pontis_b1+R_dobLess than i-th carrier wave C_iTime, the second comparator output high level, as the second modulating wave R of the first brachium pontis_b1+R_dobMore than i-th carrier wave C_iTime, the second comparator output low level；The upper switches set H of the first brachium pontis₁I-th power switch unit SM_H1iSecond switch pipe S₂The control level S of gate pole_H1iLower switches set L with the first brachium pontis₁I-th power switch unit SM_L1iSecond switch pipe S₂The control level S of gate pole_L1iThe breaker in middle group M of the first brachium pontis is obtained by the first XOR gate₁I-th power switch unit SM_M1iMiddle second switch pipe S₂The control level S of gate pole_M1i；First modulating wave R of the second brachium pontis_a2+R_doaWith i-th carrier wave C_iThe upper switches set H of the second brachium pontis is obtained by the 3rd comparator₂I-th power switch unit SM_H2iMiddle second switch pipe S₂The control level S of gate pole_H2i, as the first modulating wave R of the second brachium pontis_a2+R_doaMore than i-th carrier wave C_iTime, the 3rd comparator output high level, as the first modulating wave R of the second brachium pontis_a2+R_doaLess than i-th carrier wave C_iTime, the 3rd comparator output low level；Second modulating wave R of the second brachium pontis_b2+R_dobWith i-th carrier wave C_iSwitches set L under the second brachium pontis is obtained by the 4th comparator₂I-th power switch unit SM_L2iSecond switch pipe S₂The control level S of gate pole_L2i, as the second modulating wave R of the second brachium pontis_b2+R_dobLess than i-th carrier wave C_iTime, the 4th comparator output high level, as the second modulating wave R of the second brachium pontis_b2+R_dobMore than i-th carrier wave C_iTime, the 4th comparator output low level；The upper switches set H of the second brachium pontis₂I-th power switch unit SM_H2iMiddle second switch pipe S₂The control level S of gate pole_H2iWith switches set L under the second brachium pontis₂I-th power switch unit SM_L2iSecond switch pipe S₂The control level S of gate pole_L2iThe breaker in middle group M of the second brachium pontis is obtained by the second XOR gate₂I-th power switch unit SM_M2iSecond switch pipe S₂The control level S of gate pole_M2i；Second switch pipe S in each power switch unit of each switches set₂The first switching tube S in this power switch unit is obtained after the control level of gate pole is anti-phase₁The control level of gate pole。

Described control method can ensure that the upper switches set H of the first brachium pontis of described inverter₁, the first brachium pontis breaker in middle group M₁Lower switches set L with the first brachium pontis₁The output voltage u of N number of power switch unit is had in each moment_SM=E, the output voltage u of total 2N power switch unit_SM=0, namely meet u_H1+u_M1+u_L1=U_dc；Ensure the upper switches set H of the second brachium pontis₂, the second brachium pontis breaker in middle group M₂Lower switches set L with the second brachium pontis₂The output voltage u of N number of power switch unit is had in each moment_SM=E, the output voltage u of total 2N power switch unit_SM=0, namely meet u_H2+u_M2+u_L2=U_dc；Wherein E is the electric capacity C of each power switch unit of each switches set_SMVoltage, and E=U_dc/N。

Fig. 4 a illustrates that the single-phase six switches set MMC inverter of dual output work in the first modulating wave R of the first brachium pontis under CF pattern_a1+R_doa, the first brachium pontis the second modulating wave R_b1+R_dobWith i-th carrier wave C_iRelation。From Fig. 4 a it can be seen that the primary sinusoid is identical with the electric voltage frequency of the second sine wave, and the voltage magnitude of the primary sinusoid and the second sine wave is maximum is 1, and wherein the value of i is 1～N。Fig. 4 b illustrates that the single-phase six switches set MMC inverter of dual output work in the first modulating wave R of the first brachium pontis under DF pattern_a1+R_doa, the first brachium pontis the second modulating wave R_b1+R_dobWith i-th carrier wave C_iRelation。It is seen from fig. 4b that the electric voltage frequency of the primary sinusoid and the second sine wave differs, and the maximum of the voltage magnitude of the primary sinusoid and the second sine wave and be 1/2。First modulating wave R of the second brachium pontis_a2+R_doaThe first modulating wave R with the first brachium pontis_a1+R_doaWith i-th carrier wave C_iRelation identical, the second modulating wave R of the second brachium pontis_b2+R_dobThe second modulating wave R with the first brachium pontis_b1+R_dobWith i-th carrier wave C_iRelation identical。

Fig. 5 a is the simulation waveform figure that the single-phase five level six switches set MMC inverter of dual output work in CF pattern, it is the electric current of the voltage of the first load, the voltage of the second load, the electric current of the first load and the second load successively, identical with the power frequency of the second load from visible first load of Fig. 5 a, the current amplitude of the first load and the second load differs；Fig. 5 b is the simulation waveform figure that the single-phase five level six switches set MMC inverter of dual output work in DF pattern, it is the electric current of the voltage of the first load, the voltage of the second load, the electric current of the first load and the second load successively, all differs from power frequency and the amplitude of visible first load of Fig. 5 b and the second load。

Above-described embodiment is the present invention preferably embodiment; but embodiments of the present invention are also not restricted by the embodiments; the change made under other any spirit without departing from the present invention and principle, modification, replacement, combination, simplification; all should be the substitute mode of equivalence, be included within protection scope of the present invention。

Claims (7)

1. the single-phase six switches set MMC inverter of dual output, it is characterised in that: include DC source (U_dc), the first brachium pontis, the second brachium pontis, the first load and the second load；Described first brachium pontis and the second brachium pontis are by upper switches set (H₁、H₂), breaker in middle group (M₁、M₂), lower switches set (L₁、L₂) and coupling inductance (L_H1:L_L1、L_H2:L_L2) be in series；Upper switches set (the H of the first brachium pontis₁) by N number of power switch unit (SM_H11、SM_H12、…、SM_H1N) be in series, the breaker in middle group (M of the first brachium pontis₁) by N number of power switch unit (SM_M11、SM_M12、…、SM_M1N) be in series, the lower switches set (L of the first brachium pontis₁) by N number of power switch unit (SM_L11、SM_L12、…、SM_L1N) be in series, the upper switches set (H of the second brachium pontis₂) by N number of power switch unit (SM_H21、SM_H22、…、SM_H2N) be in series, the breaker in middle group (M of the second brachium pontis₂) by N number of power switch unit (SM_M21、SM_M22、…、SM_M2N) be in series, the lower switches set (L of the second brachium pontis₂) by N number of power switch unit (SM_L21、SM_L22、…、SM_L2N) be in series；The two ends of the first load are coupled with the breaker in middle group (M of the first brachium pontis₁) and the breaker in middle group (M of the second brachium pontis₂) upper end (o), the two ends of the second load are coupled with the breaker in middle group (M of the first brachium pontis₁) and the breaker in middle group (M of the second brachium pontis₂) lower end (p)；The two ends of the first load export as the first via, and the two ends of the second load export as the second tunnel；DC source (U_dc) positive pole and the upper switches set (H of the first brachium pontis₁) upper end, the second brachium pontis upper switches set (H₂) upper end connect, DC source (U_dc) negative pole and the lower switches set (L of the first brachium pontis₁) lower end, the second brachium pontis lower switches set (L₂) lower end connect；Upper switches set (the H of the first brachium pontis₁) the coupling inductance (L of lower end and the first brachium pontis_H1:L_L1) former limit (L_H1) Same Name of Ends (w₁) connect, the coupling inductance (L of the first brachium pontis_H1:L_L1) former limit (L_H1) non-same polarity (a₁) with the breaker in middle group (M of the first brachium pontis₁) upper end connect, the breaker in middle group (M of the first brachium pontis₁) the coupling inductance (L of lower end and the first brachium pontis_H1:L_L1) secondary (L_L1) Same Name of Ends (b₁) connect, the coupling inductance (L of the first brachium pontis_H1:L_L1) secondary (L_L1) non-same polarity (z₁) with the lower switches set (L of the first brachium pontis₁) upper end connect；The structure of the second brachium pontis is completely the same with the structure of the first brachium pontis；DC source (U_dc) negative pole and the lower switches set (L of the first brachium pontis₁) lower end, the second brachium pontis lower switches set (L₂) lower end, hold (n) to connect；Breaker in middle group (the M of one end of the first load and the first brachium pontis₁) upper end connect, the other end of the first load and the breaker in middle group (M of the second brachium pontis₂) upper end connect, the breaker in middle group (M of one end of the second load and the first brachium pontis₁) lower end connect, the other end of the second load and the breaker in middle group (M of the second brachium pontis₂) lower end connect。

2. the single-phase six switches set MMC inverter of dual output according to claim 1, it is characterised in that: the coupling inductance (L of the first brachium pontis_H1:L_L1) coupling inductance (L of former limit and secondary and the second brachium pontis_H2:L_L2) former limit and secondary by the first inductance (L_H1、L_H2) and the second inductance (L_L1、L_L2) two separate inductors substitute。

3. the single-phase six switches set MMC inverter of dual output according to claim 1, it is characterised in that: power switch unit includes the first switching tube (S₁), second switch pipe (S₂), the first diode (D₁), the second diode (D₂) and electric capacity (C_SM)；Wherein, electric capacity (C_SM) positive pole and the first switching tube (S₁) colelctor electrode, the first diode (D₁) negative electrode connect, the first switching tube (S₁) emitter stage and the first diode (D₁) anode, second switch pipe (S₂) colelctor electrode, the second diode (D₂) negative electrode connect, second switch pipe (S₂) emitter stage and the second diode (D₂) anode, electric capacity (C_SM) negative pole connect；Second switch pipe (S₂) colelctor electrode as the first outfan, second switch pipe (S₂) emitter stage as the second outfan。

4. the single-phase six switches set MMC inverter of dual output according to claim 3, it is characterised in that: the second outfan of the i-th power switch unit of each switches set is connected with the first outfan of i+1 power switch unit, and wherein the value of i is 1 ~ N-1。

5. the single-phase six switches set MMC inverter of dual output according to claim 1, it is characterised in that: mode of operation includes with frequency pattern and alien frequencies pattern, and with in frequency pattern, first via output is identical with the electric voltage frequency of the second tunnel output, and voltage magnitude differs；In alien frequencies pattern, first via output is all different from the electric voltage frequency of the second tunnel output and amplitude。

6. for the control method of the single-phase six switches set MMC inverter of dual output described in claim 1, it is characterised in that: employing phase-shifting carrier wave PWM controls opening and shutoff of the switching tube of each switches set；Upper switches set (the H of the first brachium pontis₁) i-th power switch unit (SM_H1i), the lower switches set (L of the first brachium pontis₁) i-th power switch unit (SM_L1i), the upper switches set (H of the second brachium pontis₂) i-th power switch unit (SM_H2i) and the lower switches set (L of the second brachium pontis₂) i-th power switch unit (SM_L2i) adopt identical triangular wave as i-th carrier wave C_i, wherein the value of i is 1 ~ N；N number of carrier wave (C₁、C₂、…、C_N) 360 °/N of lagging phase angle successively；Upper switches set (the H of the first brachium pontis₁) adopt the primary sinusoid (R_a1) superposition the first direct current biasing (R_doa) as the first modulating wave (R of the first brachium pontis_a1+R_doa), the lower switches set (L of the first brachium pontis₁) adopt the second sinusoidal wave (R_b1) superposition the second direct current biasing (R_dob) as the second modulating wave (R of the first brachium pontis_b1+R_dob), the upper switches set (H of the second brachium pontis₂) adopt the 3rd sinusoidal wave (R_a2) superposition the first direct current biasing (R_doa) as the first modulating wave (R of the second brachium pontis_a2+R_doa), the lower switches set (L of the second brachium pontis₂) adopt the 4th sinusoidal wave (R_b2) superposition the second direct current biasing (R_dob) as the second modulating wave (R of the second brachium pontis_b2+R_dob)；The primary sinusoid (R_a1) and the 3rd sinusoidal wave (R_a2) frequency is identical and phase contrast is 180 °, the second sinusoidal wave (R_b1) and the 4th sinusoidal wave (R_b2) frequency is identical and phase contrast is 180 °。

7. control method according to claim 6, it is characterised in that: the first modulating wave (R of the first brachium pontis_a1+R_doa) and i-th carrier wave C_iUpper switches set (the H of the first brachium pontis is obtained by the first comparator₁) i-th power switch unit (SM_H1i) second switch pipe (S₂) control level (S of gate pole_H1i), as the first modulating wave modulating wave (R of the first brachium pontis_a1+R_doa) more than i-th carrier wave C_iTime, the first comparator output high level, as the first modulating wave modulating wave (R of the first brachium pontis_a1+R_doa) less than i-th carrier wave C_iTime, the first comparator output low level, wherein the value of i is 1 ~ N；Second modulating wave (R of the first brachium pontis_b1+R_dob) and i-th carrier wave C_iLower switches set (the L of the first brachium pontis is obtained by the second comparator₁) i-th power switch unit (SM_L1i) second switch pipe (S₂) control level (S of gate pole_L1i), as the second modulating wave (R of the first brachium pontis_b1+R_dob) less than i-th carrier wave C_iTime, the second comparator output high level, as the second modulating wave (R of the first brachium pontis_b1+R_dob) more than i-th carrier wave C_iTime, the second comparator output low level；Upper switches set (the H of the first brachium pontis₁) i-th power switch unit (SM_H1i) second switch pipe (S₂) control level (S of gate pole_H1i) and the lower switches set (L of the first brachium pontis₁) i-th power switch unit (SM_L1i) second switch pipe (S₂) control level (S of gate pole_L1i) the breaker in middle group (M of the first brachium pontis is obtained by the first XOR gate₁) i-th power switch unit (SM_M1i) in second switch pipe (S₂) control level (S of gate pole_M1i)；First modulating wave (R of the second brachium pontis_a2+R_doa) and i-th carrier wave C_iUpper switches set (the H of the second brachium pontis is obtained by the 3rd comparator₂) i-th power switch unit (SM_H2i) in second switch pipe (S₂) control level (S of gate pole_H2i), as the first modulating wave (R of the second brachium pontis_a2+R_doa) more than i-th carrier wave C_iTime, the 3rd comparator output high level, as the first modulating wave (R of the second brachium pontis_a2+R_doa) less than i-th carrier wave C_iTime, the 3rd comparator output low level；Second modulating wave (R of the second brachium pontis_b2+R_dob) and i-th carrier wave C_iSwitches set (L under the second brachium pontis is obtained by the 4th comparator₂) i-th power switch unit (SM_L2i) second switch pipe (S₂) control level (S of gate pole_L2i), as the second modulating wave (R of the second brachium pontis_b2+R_dob) less than i-th carrier wave C_iTime, the 4th comparator output high level, as the second modulating wave (R of the second brachium pontis_b2+R_dob) more than i-th carrier wave C_iTime, the 4th comparator output low level；Upper switches set (the H of the second brachium pontis₂) i-th power switch unit (SM_H2i) in second switch pipe (S₂) control level (S of gate pole_H2i) and the second brachium pontis under switches set (L₂) i-th power switch unit (SM_L2i) second switch pipe (S₂) control level (S of gate pole_L2i) the breaker in middle group (M of the second brachium pontis is obtained by the second XOR gate₂) i-th power switch unit (SM_M2i) second switch pipe (S₂) control level (S of gate pole_M2i)；Second switch pipe (S in each power switch unit of each switches set₂) obtain the first switching tube (S in this power switch unit after the control level of gate pole is anti-phase₁) control level of gate pole。