CN103824769B - A kind of method of effective control power device terminal field oxide angle - Google Patents
A kind of method of effective control power device terminal field oxide angle Download PDFInfo
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- CN103824769B CN103824769B CN201210468895.2A CN201210468895A CN103824769B CN 103824769 B CN103824769 B CN 103824769B CN 201210468895 A CN201210468895 A CN 201210468895A CN 103824769 B CN103824769 B CN 103824769B
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 13
- 230000005684 electric field Effects 0.000 claims abstract description 7
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 238000009826 distribution Methods 0.000 claims abstract description 4
- 150000003376 silicon Chemical class 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims description 10
- 238000002203 pretreatment Methods 0.000 claims description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000001947 vapour-phase growth Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000012071 phase Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a kind of method of effective control power device terminal field oxide angle, comprise the steps: the 1 a piece of silicon chip of preparation, the parameter of this silicon chip is determined by device design character；After silicon chip is done surface cleaning step by 2, thermally grown or the first oxide layer that one layer of consistency of chemical vapor deposition is A1；The method of 3 employing chemical vapor depositions, in the first oxide layer, one layer of consistency of deposit is second oxide layer of A2；Consistency A2 of the second oxide layer should be less than consistency A1 of the first oxide layer；4 in the second oxide layer coating photoresist, and lithographic definition goes out the figure of field oxide；5 employing wet etchings cut through the second oxide layer, continue to use wet etching until cutting through the first oxide layer；6 removal photoresists, form final field oxide figure.The present invention, by being optimized field oxide etching technics, improves controllability and the angle value of field oxide angle, finally improves the Electric Field Distribution that field plate brings, and optimizes terminal and punctures.
Description
Technical field
The invention belongs to electronic technology field, relate to power semiconductor, be specifically related to a kind of effectively control power device terminal
The method of field oxide angle.
Background technology
The basic demand of modern power device is to be capable of withstanding high pressure and big current work.Wherein, silicon-based power MOSFET
(Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide layer-semiconductor-field effect crystal
Pipe) and IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) typically by parallel connection
Substantial amounts of device cell forms the big power device of breadth length ratio, to ensure to realize big current work.But, for high-pressure work
For silicon-based power devices, the surface voltage being positioned between each parallel units in the middle of device is roughly the same, and is positioned at border (i.e. terminal)
Device cell but differ greatly with the voltage of substrate surface, often cause surface field excessively to concentrate the edge causing device to hit
Wear.Therefore, in order to ensure that silicon-based power devices can under high pressure normally work, it usually needs take measures at device boundaries
I.e. junction termination technique technology, reduces surface field intensity, improves silicon-based power devices PN junction breakdown voltage.
Current junction termination technique technology mainly have field pull (Field Plate, FP), field limiting ring (Field Limiting Ring, FLR),
Knot termination extension (Junction Termination Extention, JTE) and variety lateral doping (Variation of Lateral
Doping, VLD) etc..Wherein, FP and FLR is applied in combination is a kind of to improve the conventional effective ways of surface breakdown characteristic.FP can
Low puncturing with effectively suppress that surface charge causes, FLR then can slow down the PN junction that planar junction curvature effect causes and puncture, and
And their simple in construction, processing compatibility is good, and the entirety that being used in combination of FP and FLR obviously can improve silicon-based power devices is resistance to
Pressure performance.
Field plate is the effectively method of one improving planar junction breakdown voltage, but its existence one inherent defect is at its edge's electricity
Field high concentration, affects the pressure of device.The peak value electric field at field plate edge is the electrostatic induction due to field plate, under field plate edge
The transverse electric field that surface charge produces is strengthened mutually, causes the peak value of a transverse field.Field plate maximum breakdown voltage to be realized, needs
Select oxidated layer thickness and the field plate gradient under suitable field plate so that the curvature at field plate edge reduces, and electric field is more gradual, from
And reach to improve silicon-based power devices breakdown voltage.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of method of effective control power device terminal field oxide angle, passes through
Field oxide etching technics is optimized, improves controllability and the angle value of field oxide angle, finally improve what field plate brought
Electric Field Distribution, optimizes terminal and punctures.
For solving above-mentioned technical problem, the present invention provides a kind of method of effective control power device terminal field oxide angle, bag
Include following steps:
Step 1, prepares a piece of silicon chip, and the parameter of this silicon chip is determined by device design character；
Step 2, after silicon chip is done surface cleaning step, thermally grown or one layer of consistency of chemical vapor deposition is A1 the first oxidation
Layer；
Step 3, uses the method for chemical vapor deposition, and in the first oxide layer, one layer of consistency of deposit is second oxide layer of A2；
Consistency A2 of described second oxide layer should be less than consistency A1 of described first oxide layer；
Step 4, coating photoresist in the second oxide layer, and lithographic definition go out the figure of field oxide；
Step 5, uses wet etching to cut through the second oxide layer, continues to use wet etching until cutting through the first oxide layer；
Step 6, removes photoresist, forms final field oxide figure.
In step 1, the parameter such as the type of described silicon chip, thickness, resistivity, pre-treatment, the device itself with final application
Relevant；The thickness of described silicon chip is between 50 microns to 800 microns；Described silicon chip is epitaxial wafer, Czochralski silicon wafer, zone melting and refining silicon
Piece or soi wafer.Described pre-treatment includes device design needs itself and the terminal done is injected, annealed, at clean surface
Reason etc..
In step 2, one layer of consistency of described thermally grown or chemical vapor deposition is first oxide-film of A1, described thermally grown
It is wet method, or dry method, or dry and wet oxidation mixing is carried out；Described chemical vapor deposition is atmospheric chemical vapor
Deposit, low-pressure chemical vapor phase deposition or plasma-reinforced chemical vapor deposition.The thickness of described first oxide layer is 0.1 micron
To 10 microns.
In step 3, the chemical gas-phase deposition method of described second oxide layer, is Films Prepared by APCVD, low pressure chemical phase
Deposit or plasma-reinforced chemical vapor deposition method.The thickness of the second described oxide layer is between 30 angstroms to 10 microns.
In step 4, described photoresist is positive photoresist, or negative photoresist；The thickness of described photoresist arrives at 0.1 micron
Between 10 microns.
In step 5, used by described wet etching, the etch rate of corrosive liquid existsArriveStep 5
After completing, the second bigger oxide layer of angulation θ 2 and less the first oxide layer of angle, θ 1.
After removing photoresist described in step 6, following steps can also be increased: use wet etching to remove the second oxide layer,
Only remain the first oxide layer, form final field oxide figure.
Compared to the prior art, the method have the advantages that present invention is generally directed to field oxide etching technics carries out excellent
Change, utilize the difference of the corrosion rate of different field oxide so that the angle of oxide layer is more controllable, and angle value can do more
Add little, thus improve the Electric Field Distribution that field plate brings, optimize terminal and puncture, optimised devices reverse blocking capability.The present invention is directed to
Apply field oxide power semiconductor in all.By improving the etching mode of field oxide, utilize deposited oxide layer and
The difference of the wet-etch rate between thermal oxide layer, produces the field oxide angle being more close to design, thus obtains more
High pressure terminal structure, reduces terminal area, and then reduces chip area.
Brief description
Fig. 1 is the generalized section after the step 1 of the inventive method completes；
Fig. 2 is the generalized section after the step 2 of the inventive method completes；
Fig. 3 is the generalized section after the step 3 of the inventive method completes；
Fig. 4 is the generalized section after the step 4 of the inventive method completes；
Fig. 5 a be the inventive method step 5 in cut through the generalized section after the second oxide layer；
Fig. 5 b is the generalized section of (after i.e. cutting through the first oxide layer) after the step 5 of the inventive method completes；
Fig. 6 a is the generalized section after the step 6 of the inventive method completes；
Fig. 6 b is the generalized section after the step 7 of the inventive method completes.
In figure, description of reference numerals is as follows:
1 is silicon chip, and 2 is the first oxide layer, and 3 is the second oxide layer, and 4 is photoresist, and θ 1 is the angle of the first oxide layer,
θ 2 is the angle of the second oxide layer.
Detailed description of the invention
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings.
As shown in Fig. 1-Fig. 6 b, the method for a kind of effective control power device terminal field oxide angle of the present invention, specifically wrap
Include following steps:
1. as it is shown in figure 1, prepare a piece of silicon chip 1, the parameter such as the type of silicon chip 1, thickness, resistivity, pre-treatment, and
The device of application itself is relevant eventually, is determined by device design character, can be any resistivity, and the thickness of silicon chip 1 can be
Between 50 microns to 800 microns, can be epitaxial wafer, Czochralski silicon wafer, fused silicon chip, can also is that soi wafer (referred to as
Silicon-on-insulator or SOI, SILICon-on-insulator, SOI)；Described pre-treatment include device itself design needs and
The terminal done is injected, annealing, clean surface process etc.；
2. silicon chip 1 as shown in Figure 1, after doing surface cleaning step, thermally grown or one layer of consistency of chemical vapor deposition is A1's
First oxide layer 2, as shown in Figure 2；Described thermally grown can be wet method, it is also possible to be dry method, can also is that dry and wet
Oxidation mixing is carried out；Described chemical vapor deposition, can be Films Prepared by APCVD, low-pressure chemical vapor phase deposition, plasma
Strengthen the methods such as chemical vapor deposition；The thickness of the first oxide layer 2 can be 0.1 micron to 10 microns；
3. on the basis of Fig. 2, then by the method for chemical vapor deposition, oxide layer 2 deposits one layer of consistency is A2 the
Dioxide layer 3, as shown in Figure 3；The chemical gas-phase deposition method of the second oxide layer 3, can be Films Prepared by APCVD,
The method such as low-pressure chemical vapor phase deposition, plasma-reinforced chemical vapor deposition；The thickness of the second oxide layer 3 can be 30 angstroms and arrive
Between 10 microns；Consistency A2 of the second oxide layer 3 need to be less than consistency A1 of the first oxide layer 2.
4. coating photoresist 4 in the second oxide layer 3, and lithographic definition goes out the figure of field oxide, as shown in Figure 4；Photoetching
Glue 4 can be positive photoresist, it is also possible to is negative photoresist, and its thickness is between 0.1 micron to 10 microns；
5. it with etch rate isCarry out wet etching, cut through the second oxide layer 3, as shown in Figure 5 a, continue to etch
Speed isCarrying out wet etching, until cutting through the first oxide layer 2, forming angle, θ 2 as shown in Figure 5 b bigger
Second oxide layer 3 and less the first oxide layer 2 of angle, θ 1；The etch rate B of corrosive liquid used by wet etching can be Arrive?；
6. use this area conventional method to remove photoresist 4, form final field oxide figure, as shown in Figure 6 a；
If 7. further demand being had to oxide layer surface, wet method can etch away the second oxide layer 3 again, only remaining angle less
First oxide layer 2, then the figure of final field oxide is as shown in Figure 6 b.According to design needs, the second oxide layer 3 can be retained
Also the second oxide layer 3 can be got rid of.
Claims (8)
1. the method for an effective control power device terminal field oxide angle, it is characterised in that comprise the steps:
Step 1, prepares a piece of silicon chip, and the parameter of this silicon chip is determined by device design character；
Step 2, after silicon chip is done surface cleaning step, thermally grown or one layer of consistency of chemical vapor deposition is A1 the first oxidation
Layer；The thickness of described first oxide layer is 0.1 micron to 10 microns；
Step 3, uses the method for chemical vapor deposition, and in the first oxide layer, one layer of consistency of deposit is second oxide layer of A2；
Consistency A2 of described second oxide layer should be less than consistency A1 of described first oxide layer；The thickness of the second described oxide layer
Between 30 angstroms to 10 microns；
Step 4, coating photoresist in the second oxide layer, and lithographic definition go out the figure of field oxide；
Step 5, uses wet etching to cut through the second oxide layer, continues to use wet etching until cutting through the first oxide layer；Utilize
The difference of the wet-etch rate of different described first oxide layer of consistency and described second oxide layer, after step 5 completes,
Bigger described second oxide layer of angulation and less described first oxide layer of angle；
Step 6, removes photoresist, forms final field oxide figure, and described field oxide figure is as power device terminal
Field plate bottom field oxide, described first oxide layer utilizing the angle in described field oxide less is improved as edge
The Electric Field Distribution of the field plate edge of described power device terminal, improves the pressure of terminal.
2. the method for claim 1, it is characterised in that in step 1, the type of described silicon chip, thickness, resistance
Rate, pre-treatment parameter, relevant with the device of final application itself；The thickness of described silicon chip is between 50 microns to 800 microns；
Described silicon chip is epitaxial wafer, Czochralski silicon wafer, fused silicon chip or soi wafer.
3. method as claimed in claim 2, it is characterised in that described pre-treatment includes that device design needs itself do
Terminal is injected, annealing, clean surface process.
4. the method for claim 1, it is characterised in that in step 2, described thermally grown or chemical vapor deposition one
Layer consistency is first oxide-film of A1, described thermally grown be wet method, or dry method, or dry and wet oxidation mixing
Carry out；Described chemical vapor deposition is Films Prepared by APCVD, low-pressure chemical vapor phase deposition or Plasma Enhanced Chemical Vapor
Deposit.
5. the method for claim 1, it is characterised in that in step 3, the chemical vapor deposition of described second oxide layer
Method, is Films Prepared by APCVD, low-pressure chemical vapor phase deposition or plasma-reinforced chemical vapor deposition method.
6. the method for claim 1, it is characterised in that in step 4, described photoresist is positive photoresist, or negative
Property photoresist；The thickness of described photoresist is between 0.1 micron to 10 microns.
7. the method for claim 1, it is characterised in that in step 5, the etching of corrosive liquid used by described wet etching
Speed existsArrive
8. the method for claim 1, it is characterised in that after removing photoresist described in step 6, also increases as follows
Step: use wet etching to remove the second oxide layer, only remain the first oxide layer, form final field oxide figure.
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| CN103824769B true CN103824769B (en) | 2016-11-09 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106057669A (en) * | 2016-06-24 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | IGBT terminal field oxide technique |
| CN109920726A (en) * | 2019-03-13 | 2019-06-21 | 深圳大学 | A method of forming field isolation |
| CN112447821A (en) * | 2019-09-02 | 2021-03-05 | 珠海零边界集成电路有限公司 | Terminal structure manufacturing method |
| CN110517957B (en) * | 2019-09-10 | 2021-07-16 | 上海华虹宏力半导体制造有限公司 | Field oxide layer and forming method thereof |
| CN111952153B (en) * | 2020-08-21 | 2023-08-22 | 浙江晶科能源有限公司 | Preparation method of tunneling oxide layer, solar cell and preparation method of solar cell |
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| CN101969027A (en) * | 2010-08-11 | 2011-02-09 | 上海宏力半导体制造有限公司 | Method for forming field oxidation layer |
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| KR20060078197A (en) * | 2004-12-30 | 2006-07-05 | 매그나칩 반도체 유한회사 | Method for forming field oxides of semiconductor devices |
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| CN101969027A (en) * | 2010-08-11 | 2011-02-09 | 上海宏力半导体制造有限公司 | Method for forming field oxidation layer |
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