CN103823505B - Clock frequency obtains system and clock frequency acquisition methods - Google Patents
Clock frequency obtains system and clock frequency acquisition methods Download PDFInfo
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- CN103823505B CN103823505B CN201410056036.1A CN201410056036A CN103823505B CN 103823505 B CN103823505 B CN 103823505B CN 201410056036 A CN201410056036 A CN 201410056036A CN 103823505 B CN103823505 B CN 103823505B
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Abstract
System and clock frequency acquisition methods are obtained the invention discloses clock frequency, its clock frequency acquisition method includes：A, it will be clock signal under in the incoming clock frequency acquisition system of source；B, clock frequency obtain that system is ascending is sequentially generated the clock signal of multi-frequency, and judge whether the clock signal of the multi-frequency can be clock signal under dividing exactly；C, when the clock signal of the multi-frequency can be clock signal under dividing exactly, preserve the clock signal, and the frequency being clock signal under is calculated according to the clock signal of preservation, realize with low frequency clock signal to obtain the frequency of high-frequency clock signal, be not limited by the influence of the factors such as hardware condition and cost.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of clock frequency obtains system and clock frequency acquisition side
Method.
Background technology
With the rapid development of mobile communication technology, the clock frequency more and more higher of chip operation, it is desirable to more and more accurate,
Therefore the clock frequency of acquisition chip is usually required, the frequency of other signals is accurately controlled according to the clock frequency.
At present, the method for the frequency of one clock of acquisition is：Sampling one is triggered with a high-frequency clock signal
Low-frequency clock signal, so as to obtain the frequency of low frequency clock signal.Therefore, needing to obtain the frequency of a clock signal
During rate, it is desirable to have the higher clock signal of a frequency.But sometimes due to being limited to the factors such as hardware, cost, need with
During frequency of the low-frequency clock signal to obtain high frequency clock signal, current frequency acquisition technology can not also be competent at, in view of this,
The present invention proposes a kind of method and system that high frequency clock signal is obtained by low-frequency clock signal.
The content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of clock frequency obtain system and
Clock frequency acquisition methods, can obtain the frequency of high-frequency clock signal with low frequency clock signal.
In order to achieve the above object, this invention takes following technical scheme：
A kind of clock frequency obtains system, and it includes：
Clock generator, for the ascending clock signal for being sequentially generated multi-frequency；
Judge module, with clock generator and being clock signal under source and being connected, the clock for judging the multi-frequency
Whether signal can be clock signal under dividing exactly；
Cache module, for store clock signal；
Frequency setting module, for when the clock signal of the multi-frequency can be clock signal under dividing exactly, by when
The frequency that clock generator is produced is stored in cache module；
Computing module, for calculating the frequency being clock signal under according to the clock signal preserved in cache module；Also use
The frequency values for the clock signal that the clock enabling signal stored in filtering cache module retains are relatively prime, and will retain in cache module
Clock frequency be multiplied obtain measured clock frequency；Specially：Frequency values in filtering cache module, make the clock signal of reservation
Frequency values it is relatively prime, when there is more than one common factor in the frequency values of the clock signal of filtering, less frequency is gone
Remove, retain maximum frequency values；And the clock frequency multiplication of reservation is obtained into measured clock frequency.
In described clock frequency acquisition system, the frequency setting module is additionally operable to set what clock generator was produced
The frequency of clock signal.
A kind of above-mentioned clock frequency obtains the clock frequency acquisition methods of system, and it includes：
A, it will be clock signal under in the incoming clock frequency acquisition system of source；
B, clock frequency obtain that system is ascending is sequentially generated the clock signal of multi-frequency, and judge a variety of frequencies
Whether the clock signal of rate can be clock signal under dividing exactly；
C, when the clock signal of the multi-frequency can be clock signal under dividing exactly, preserve the clock signal, and root
The frequency being clock signal under is calculated according to the clock signal of preservation；
The step C is specifically included：
C1, when the clock signal of the multi-frequency can be clock signal under dividing exactly, by the clock signal of the frequency
It is stored in cache module；
The frequency values for the clock signal that the clock enabling signal stored in C2, filtering cache module retains are relatively prime, are specially：Cross
The frequency values in cache module are filtered, make the frequency values of the clock signal of reservation relatively prime, in the frequency values of the clock signal of filtering
When there is more than one common factor, less frequency is removed, retains maximum frequency values；
C3, the clock frequency of reservation, which is multiplied, obtains measured clock frequency.
In described clock frequency acquisition methods, the step B also includes：The clock signal for setting clock generator to produce
Frequency.
Compared to prior art, the clock frequency that the present invention is provided obtains system and clock frequency acquisition methods, by when
The ascending clock signal for being sequentially generated multi-frequency of clock generator, judges whether the clock signal of the multi-frequency can quilt
It is clock signal under dividing exactly, and preserves and can be clock signal under clock signal；Quilt is calculated according to the clock signal of preservation afterwards
The frequency of clock signal is surveyed, realizes with low frequency clock signal to obtain the frequency of high-frequency clock signal, is not limited by
The influence of the factor such as hardware condition and cost.
Brief description of the drawings
Fig. 1 is the structured flowchart that clock frequency of the present invention obtains system.
Fig. 2 is the flow chart of clock frequency acquisition methods of the present invention.
Embodiment
The present invention provides a kind of clock frequency and obtains system and clock frequency acquisition methods, to make the purpose of the present invention, skill
Art scheme and effect are clearer, clear and definite, and the present invention is described in more detail for the embodiment that develops simultaneously referring to the drawings.It should manage
Solution, specific embodiment described herein only to explain the present invention, is not intended to limit the present invention.
The clock frequency that the present invention is provided obtains system can be with low-frequency clock signal（It may be otherwise and think to be no greater than
The frequency being clock signal under）To obtain high-frequency clock signal, make the acquisition of clock signal frequency not by hardware and cost etc.
The limitation of factor, referring to Fig. 1, it is the structured flowchart that clock frequency of the present invention obtains system.As shown in figure 1, the present invention
Clock frequency, which obtains system, to be included clock generator 10, judge module 20, cache module 30, frequency setting module 40 and calculates mould
Block 50, two inputs of the judge module 20 are respectively with clock generator 10 and being clock signal under source and being connected, and it is exported
Rate of connections setup module 40 is held, the frequency setting module 40 connects computing module 50 by cache module 30.
Wherein, clock generator 10 is used in the ascending clock signal for being sequentially generated multi-frequency, the present embodiment, when
The signal that clock generator 10 is produced is square-wave signal.The judge module 20 is used to judge that the clock signal of the multi-frequency to be
It is no to be clock signal under dividing exactly.The cache module 30 is used for store clock signal.The frequency setting module 40 is used for
When the clock signal of the multi-frequency can be clock signal under dividing exactly, the frequency that clock generator 10 is produced is stored in
In cache module 30.The computing module 50, which is used to be calculated according to the clock signal preserved in cache module 30, to be clock signal under
Frequency.
In the embodiment of the present invention, the frequency setting module 40 is additionally operable to the clock signal for setting clock generator 10 to produce
Frequency.For example, frequency setting module 40 set clock frequency for 1MHz, 2MHz, 3MHz, 4MHz, 5MHz, 6MHz, 7MHz,
16MHz ..., make clock generator 10 be sequentially generated 1MHz, 2MHz, 3MHz, 4MHz, 5MHz, 6MHz, 7MHz,
16MHz ..., clock signal.
Wherein, whether the clock signal of multi-frequency can be clock signal under dividing exactly, that is, being clock signal under can be whole
Except the clock signal for the multi-frequency that clock generator 10 is sequentially generated, for example：The clock letter that clock generator 10 is sequentially generated
Number for 1MHz, 2MHz, 3MHz, 4MHz, 5MHz, 6MHz, 7MHz, 16MHz ... the clock that can be clock signal under dividing exactly letter
Number frequency is：1MHz, 2MHz, 4MHz, 7MHz, 16MHz, then in cache module 30 preserve 1MHz, 2MHz, 4MHz, 7MHz,
16MHz。
In order to improve computational accuracy, when calculating the frequency being clock signal under, it is necessary to the frequency in cache module 30
Value filtering, therefore, described, the computing module 50 is additionally operable to what the clock enabling signal that is stored in filtering cache module 30 retained
The frequency values of clock signal are relatively prime, and the clock frequency retained in cache module 30 multiplication is obtained into measured clock frequency.
For example, can be clock signal under the frequency values that frequency divided exactly is：F1, f2, f3 ..., fi, and f1<f2<
f3<……<Fi, need to be removed in filtering f1, f2, f3 ..., some frequency values in fi make remaining frequency values relatively prime, when
Any one removed in two frequencies can make to remove less frequency values when remaining frequency values are relatively prime, retain maximum
Frequency values.Such as f1, f2, f3 ..., fi be 1MHz, 2MHz, 4MHz, 7MHz, 16MHz, then by 2MHz, 4MHz remove, retain
1MHz, 7MHz, 16MHz, the i.e. frequency values of any two clock frequency do not have other common factors in addition to 1, and mould is calculated afterwards
Block 50 makes remaining frequency values be multiplied the frequency values for drawing and being clock signal under, that is, and frequency value F=1 × 7 being clock signal under ×
16=112MHz。
System is obtained based on above-mentioned clock frequency, the present invention correspondingly provides a kind of clock frequency acquisition methods, please joined
Fig. 2 is read, it includes：
S10, it will be clock signal under in the incoming clock frequency acquisition system of source；
S20, clock frequency obtain that system is ascending is sequentially generated the clock signal of multi-frequency, and judge described a variety of
Whether the clock signal of frequency can be clock signal under dividing exactly；
S30, when the clock signal of the multi-frequency can be clock signal under dividing exactly, preserve the clock signal, and
The frequency being clock signal under is calculated according to the clock signal of preservation.
Wherein, the frequency of clock signal for setting clock generator to produce also is needed in step S20.Clock is such as set
Device produce clock signal frequency for 1MHz, 2MHz, 3MHz ..., N-1MHz, NMHz；（N is 200 energy of clock generator
The highest frequency of the square-wave signal of output）.Specifically refer to above-described embodiment.
The step S30 is specifically included：
Step 1, when the clock signal of the multi-frequency can be clock signal under dividing exactly, the clock of the frequency is believed
Number it is stored in cache module；
The frequency values for the clock signal that the clock enabling signal stored in step 2, filtering cache module retains are relatively prime；
Step 3, the clock frequency of reservation, which is multiplied, obtains measured clock frequency.
For example, clock generator produce frequency be 1MHz, 2MHz, 3MHz, 4MHz, 5MHz, 6MHz, 7MHz, 8MHz, this
Place produces the quantity of clock signal and determined for K≤N.Assuming that measured clock frequency is 8MHz, then the low frequency that clock generator is produced
The frequency that clock signal can be divided exactly by measured clock frequency has：1MHz, 2MHz, 4MHz and 8MHz, and these frequencies are stored in
In cache module.The frequency values in computing module filtering cache module, make the frequency values of the clock signal of reservation relatively prime afterwards, this
When 2MHz, 4MHz, 8MHz there is more than one common factor each other, therefore less frequency is removed, retains maximum
Frequency values, need, by 2MHz and 4MHz removals, to retain 8MHz, now the frequency values in cache module are only 1MHz and 8MHz herein,
Final F=1 × 8=8MHz.
In summary, the present invention is judged by the ascending clock signal for being sequentially generated multi-frequency of clock generator
Whether the clock signal of the multi-frequency can be clock signal under dividing exactly, and preserve can be clock signal under clock letter
Number；The frequency being clock signal under is calculated according to the clock signal of preservation afterwards, realizes with low frequency clock signal to obtain
The frequency of high-frequency clock signal, is not limited by the influence of the factors such as hardware condition and cost.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and its hair
Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention
Protect scope.
Claims (4)
1. a kind of clock frequency obtains system, it is characterised in that including：
Clock generator, for the ascending clock signal for being sequentially generated multi-frequency；
Judge module, with clock generator and being clock signal under source and being connected, the clock signal for judging the multi-frequency
Whether can be clock signal under dividing exactly；
Cache module, for store clock signal；
Frequency setting module, for when the clock signal of the multi-frequency can be clock signal under dividing exactly, clock to be sent out
The frequency that raw device is produced is stored in cache module；
Computing module, for calculating the frequency being clock signal under according to the clock signal preserved in cache module；It was additionally operable to
The frequency values for the clock signal that the clock enabling signal that stores retains are relatively prime in filter cache module, and by retain in cache module when
Clock frequency multiplication obtains measured clock frequency；Specially：Frequency values in filtering cache module, make the frequency of the clock signal of reservation
Rate value is relatively prime, and when there is more than one common factor in the frequency values of the clock signal of filtering, less frequency is removed, and protects
Stay the frequency values of maximum；And the clock frequency multiplication of reservation is obtained into measured clock frequency.
2. clock frequency according to claim 1 obtains system, it is characterised in that the frequency setting module, it is additionally operable to
The frequency of the clock signal of clock generator generation is set.
3. a kind of clock frequency as claimed in claim 1 obtains the clock frequency acquisition methods of system, it is characterised in that including：
A, it will be clock signal under in the incoming clock frequency acquisition system of source；
B, clock frequency obtain that system is ascending is sequentially generated the clock signal of multi-frequency, and judge the multi-frequency
Whether clock signal can be clock signal under dividing exactly；
C, when the clock signal of the multi-frequency can be clock signal under dividing exactly, preserve the clock signal, and according to guarantor
The clock signal deposited calculates the frequency being clock signal under；
The step C is specifically included：
C1, when the clock signal of the multi-frequency can be clock signal under dividing exactly, the clock signal of the frequency is stored
In cache module；
The frequency values for the clock signal that the clock enabling signal stored in C2, filtering cache module retains are relatively prime, are specially：Filtering is slow
Frequency values in storing module, make the frequency values of the clock signal of reservation relatively prime, exist in the frequency values of the clock signal of filtering
During more than one common factor, less frequency is removed, retains maximum frequency values；
C3, the clock frequency of reservation, which is multiplied, obtains measured clock frequency.
4. clock frequency acquisition methods according to claim 3, it is characterised in that the step B also includes：Clock is set
The frequency for the clock signal that generator is produced.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410056036.1A CN103823505B (en) | 2014-02-19 | 2014-02-19 | Clock frequency obtains system and clock frequency acquisition methods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410056036.1A CN103823505B (en) | 2014-02-19 | 2014-02-19 | Clock frequency obtains system and clock frequency acquisition methods |
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| CN103823505A CN103823505A (en) | 2014-05-28 |
| CN103823505B true CN103823505B (en) | 2017-08-08 |
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|---|---|---|---|---|
| US4806878A (en) * | 1985-09-18 | 1989-02-21 | Plessey Overseas Limited | Phase comparator lock detect circuit and a synthesizer using same |
| US6085327A (en) * | 1998-04-10 | 2000-07-04 | Tritech Microelectronics, Ltd. | Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized |
| CN200979669Y (en) * | 2006-11-27 | 2007-11-21 | 天津中晶微电子有限公司 | An internal integration clock generation circuit in USB equipment square chip |
| CN101582732A (en) * | 2009-06-10 | 2009-11-18 | 中兴通讯股份有限公司 | Clock detection method and device |
| CN102314208A (en) * | 2010-06-30 | 2012-01-11 | 重庆重邮信科通信技术有限公司 | Method and device for dynamically adjusting frequency and voltage of embedded equipment |
-
2014
- 2014-02-19 CN CN201410056036.1A patent/CN103823505B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4806878A (en) * | 1985-09-18 | 1989-02-21 | Plessey Overseas Limited | Phase comparator lock detect circuit and a synthesizer using same |
| US6085327A (en) * | 1998-04-10 | 2000-07-04 | Tritech Microelectronics, Ltd. | Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized |
| CN200979669Y (en) * | 2006-11-27 | 2007-11-21 | 天津中晶微电子有限公司 | An internal integration clock generation circuit in USB equipment square chip |
| CN101582732A (en) * | 2009-06-10 | 2009-11-18 | 中兴通讯股份有限公司 | Clock detection method and device |
| CN102314208A (en) * | 2010-06-30 | 2012-01-11 | 重庆重邮信科通信技术有限公司 | Method and device for dynamically adjusting frequency and voltage of embedded equipment |
Non-Patent Citations (2)
| Title |
|---|
| 关于超高频率测量技术的研究;李智奇等;《宇航计测技术》;20040630(第24卷第3期);第12-15页 * |
| 给予离散相位差检测的频率测量方法;汪正军等;《仪器仪表学报》;20130531(第34卷第5期);第994-999页 * |
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