CN103794482A - Method for forming metal gate - Google Patents
Method for forming metal gate Download PDFInfo
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- CN103794482A CN103794482A CN201210422991.3A CN201210422991A CN103794482A CN 103794482 A CN103794482 A CN 103794482A CN 201210422991 A CN201210422991 A CN 201210422991A CN 103794482 A CN103794482 A CN 103794482A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract
A method for forming a metal gate comprises the steps of providing a semiconductor substrate; forming an interface material layer, a high K medium layer and a polycrystalline silicon layer on the surface of the semiconductor substrate; carrying out first nitridation processing on the surface of the polycrystalline silicon layer, and forming a nitrogen silicon compound on the surface of the polycrystalline silicon layer; forming a hard mask layer on the polycrystalline silicon layer after the first nitridation processing, wherein the hard mask layer possesses an opening for exposing the nitrogen silicon compound on the surface of the polycrystalline silicon layer; etching the polycrystalline silicon layer, the high K medium layer and the interface material layer along the opening to form an interface layer, a high K medium layer and a dummy gate; forming an interlayer medium layer on the surface of the semiconductor substrate, wherein the surface of the interlayer medium layer is parallel and level with the top surface of the dummy gate; removing the dummy gate to form a groove, and filling metal in the groove to form the metal gate. The nitrogen silicon compound can prevent an oxygen element from penetrating the polycrystalline silicon layer to react with the silicon on the surface of the semiconductor substrate to form a silicon oxide, and enables the thickness of the interface material layer not to change.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of formation method of metal gates.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in MOS transistor.Impact for fear of the metal material of metal gates on other structures of transistor, the gate stack structure of described metal gates and high K gate dielectric layer adopts " rear grid (gate last) " technique to make conventionally.
Fig. 1 ~ Fig. 4 is that prior art is used " rear grid " technique to form the method cross-sectional view of metal gates.First please refer to Fig. 1, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, form successively boundary material layer 101, high K dielectric layer 102 and polysilicon layer 103; On described polysilicon layer 103, form hard mask layer 104, described hard mask layer 104 has the opening on exposed polysilicon layer 103 surface.The material of described boundary layer 101 is silica.
Then, please refer to Fig. 2, take described hard mask layer 104 as mask, polysilicon layer 103, high K dielectric layer 102 and boundary material layer 101 described in etching successively, forms boundary layer 105, the high-K gate dielectric layer 106 that is positioned at boundary layer 105 surfaces being positioned in described Semiconductor substrate 100, the pseudo-grid 107 that are positioned at high-K gate dielectric layer 106 surfaces.
Then, please refer to Fig. 3, the 104(of hard mask layer shown in removal is with reference to figure 2); In described Semiconductor substrate 100, form dielectric layer 108, the flush of the surface of dielectric layer 108 and pseudo-grid 107.
Then, please refer to Fig. 4, remove described pseudo-grid 107(with reference to figure 3), form groove; In groove, fill full metal, form metal gates 109.
But the thickness of the boundary material layer (or boundary layer) that prior art forms easily changes, and affects transistorized stability.
More manufacture methods about metal gates, please refer to the United States Patent (USP) that publication number is US2002/0064964A1.
Summary of the invention
The problem that the present invention solves is to improve transistorized stability.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of metal gates, comprising: Semiconductor substrate is provided; Form successively boundary material layer, high K dielectric layer and polysilicon layer at described semiconductor substrate surface; The first nitrogen treatment is carried out in described polysilicon layer surface, form nitrogen silicon compound on polysilicon layer surface; After the first nitrogen treatment, form hard mask layer on polysilicon layer, described hard mask layer has the opening of the nitrogen silicon compound on exposed polysilicon layer surface; Along polysilicon layer, high K dielectric layer and boundary material layer described in opening etching, form be positioned at semiconductor substrate surface boundary layer, be positioned at the high-K gate dielectric layer on boundary layer and be positioned at the pseudo-grid on high K dielectric layer; Form interlayer dielectric layer at described semiconductor substrate surface, the surface of interlayer dielectric layer flushes with pseudo-grid top surface; Remove described pseudo-grid, form groove; In groove, fill full metal, form metal gates.
Optionally, the material of described boundary layer is silica or silicon oxynitride.
Optionally, the thickness of described boundary layer is 5 ~ 30 dusts.
Optionally, described the first nitrogen treatment is the first annealing, passes into gas NH when the first annealing
3.
Optionally, the temperature of described the first annealing is 300～1000 degrees Celsius, and the first annealing time is 5 ~ 200 seconds, and the pressure of the first annealing chamber is 0.5 ~ 780 holder.
Optionally, the gas that passes into also comprises N described first when annealing
2o.
Optionally, before forming interlayer dielectric layer, also comprise: described pseudo-grid are carried out to the second nitrogen treatment, form nitrogen silicon compound in the sidewall surfaces of described pseudo-grid.
Optionally, described the second nitrogen treatment is the second annealing, passes into gas NH when the second annealing
3.
Optionally, the temperature of described the second annealing is 300 ~ 1000 degrees Celsius, and the second annealing time is 5 ~ 200 seconds, and the pressure of the second annealing chamber is 0.5 ~ 780 holder.
Optionally, the gas that passes into also comprises N described second when annealing
2o.
Optionally, also comprise: form diffusion impervious layer on described high K dielectric layer surface; In the atmosphere of ammonia, described high K dielectric layer and diffusion impervious layer are annealed.
Optionally, also comprise: form side wall at the both sides of described pseudo-grid sidewall.
Optionally, also comprise: sidewall and lower surface at described groove form functional layer.
Compared with prior art, technical solution of the present invention has the following advantages:
Forming after polysilicon layer, described polysilicon layer is carried out to the first nitrogen treatment, form nitrogen silicon compound on polysilicon layer surface, because the density of nitrogen silicon compound is greater than the density of polysilicon, therefore can effectively stop airborne oxygen element to arrive the surface of Semiconductor substrate through polysilicon layer, follow-up while carrying out various technique, prevent that oxygen element from forming silica with the pasc reaction of semiconductor substrate surface under the environment of high temperature, oxide can make the thickness thickening of boundary material layer, in the time that etching interface material layer forms boundary layer, the thickness that makes boundary layer also can thickening, there is deviation in the actual (real) thickness of boundary layer and the design thickness of boundary layer, affect transistorized performance and stable type.
Further, the temperature of described the first annealing is 300 ~ 1000 degrees Celsius, and the first annealing time is 5 ~ 200 seconds, the pressure of the first annealing chamber is 0.5 ~ 780 holder, make the first annealing form nitrogen silicon compound thinner thickness, compactness is better, and covers uniformly the surface of polysilicon layer.
Further, carry out the second nitrogen treatment, sidewall surfaces at described pseudo-grid forms thinner nitrogen silicon compound, the nitrogen silicon compound of sidewall surfaces and the nitrogen silicon compound of pseudo-grid top surface of pseudo-grid, make pseudo-grid with outside isolated, follow-up while carrying out the higher treatment process of temperature, such as: while adopting depositing operation to form side wall and dielectric layer, oxygen element in prevention environment is through the surface of the Semiconductor substrate under sidewall and the top surface arrival boundary layer of pseudo-grid, under the environment of high temperature, form silica and make the thickness thickening of boundary layer with pasc reaction in Semiconductor substrate, the transistorized stability that impact forms.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of prior art metal gates forming process;
Fig. 5 ~ Figure 11 is the cross-sectional view of embodiment of the present invention metal gates forming process.
Embodiment
Inventor's discovery, prior art is in the time making metal gates, and the thickness of the final boundary layer forming is always partially thick than the thickness of boundary material layer, makes the actual (real) thickness of boundary layer and the design thickness of boundary layer occur deviation, affects transistorized performance and stable type.
Inventor further studies discovery, existing boundary material layer normally forms by thermal oxidation technology, forming after boundary material layer, polysilicon layer, hard mask layer, dielectric layer etc. are all to form by chemical vapor deposition method, when chemical vapor deposition method, the temperature higher (500 ~ 800 degrees Celsius) of deposition chambers, under the environment of high temperature, partial oxygen element can pass the surface of polysilicon layer, hard mask layer arrival Semiconductor substrate, react and form silica with the silicon generation of semiconductor substrate surface, thereby make the thickness thickening of boundary material layer.
For addressing the above problem, inventor proposes a kind of formation method of metal gates, forming after polysilicon layer, described polysilicon layer is carried out to the first nitrogen treatment, form nitrogen silicon compound on polysilicon layer surface, because the density of nitrogen silicon compound is greater than the density of polysilicon, therefore can effectively stop airborne oxygen element to arrive the surface of Semiconductor substrate through polysilicon layer, follow-up while carrying out various technique, make the thickness of boundary material layer remain unchanged or change less.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Describing in detail when the embodiment of the present invention, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
Fig. 5 ~ Figure 11 is the cross-sectional view of embodiment of the present invention metal gates forming process.
With reference to figure 5, Semiconductor substrate 300 is provided, in described Semiconductor substrate 300, form successively boundary material layer 301, high K dielectric layer 302 and polysilicon layer 303, described boundary material layer 301 is positioned in Semiconductor substrate 300, high K dielectric layer 302 is positioned at boundary material layer 301 surface, and polysilicon layer 303 is positioned at high K dielectric layer 302 surface.
The material of described boundary material layer 301 is silica, the formation technique of boundary material layer 301 is thermal oxidation, the thickness of boundary material layer 301 is 5 ~ 30 dusts, described boundary material layer 301 is for avoiding the direct mismatch that produces lattice that contacts of high K dielectric layer and raceway groove, reduce leakage current, the better quality that high K dielectric layer 302 is grown at boundary material layer 301 in addition simultaneously.
In other embodiments of the invention, the material of described boundary material layer is silicon oxynitride, and the formation technique of boundary material layer is chemical vapour deposition (CVD).
Described high K dielectric layer 302 is follow-up is used to form transistorized high-K gate dielectric layer, and high K dielectric layer 302 material are hafnium oxide (HfO
2) also optionally comprise other high dielectric constant materials, for example: TiO
2, HfZrO, Ta
2o
3, ZrO
2or ZrSiO
2.
In other embodiments of the invention, forming after described high K dielectric layer, also comprising: forming diffusion impervious layer on described high K dielectric layer surface; In the atmosphere of ammonia, described high K dielectric layer and diffusion impervious layer are annealed.To annealing in the atmosphere at ammonia at high K dielectric layer, form the compound of HfON on high K dielectric layer surface, can effectively stop that extraneous oxygen element is by the surface of high K dielectric layer diffusion Semiconductor substrate, thereby prevent boundary material layer 301 thickening.
The material of described diffusion impervious layer is the single or multiple lift stacked structure of Ti, Ta, TiN, TaN.
Described polysilicon layer 303 is follow-up is used to form pseudo-grid.
The material of described Semiconductor substrate 300 can be monocrystalline silicon (Si) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material.Described Semiconductor substrate 300 can also be injected certain doping ion to change electrical parameter according to design requirement.In described Semiconductor substrate 300, be also formed with fleet plough groove isolation structure (not shown), described fleet plough groove isolation structure is for isolating different transistors, prevent that between different crystal pipe, electricity connects, the material of described fleet plough groove isolation structure can be silica, silicon nitride, wherein one or more of silicon oxynitride.
Then, please refer to Fig. 6, the first nitrogen treatment is carried out in described polysilicon layer 303 surfaces, form nitrogen silicon compound 304 on polysilicon layer 303 surfaces.
Described the first nitrogen treatment is the first annealing, passes into gas NH when the first annealing
3, under the environment of high temperature, NH
3form the nitrogen silicon compound 304 of one deck thin layer with the pasc reaction on polysilicon layer 303 surfaces, nitrogen silicon compound 304 thickness are 5 ~ 30 dusts, the top surface that described nitrogen silicon compound 304 not only covers polysilicon layer 303 also covers the sidewall surfaces of polysilicon layer 303, described nitrogen silicon compound 304 main components are silicon nitride or silicon oxynitride or both mixtures, because the density of nitrogen silicon compound 304 is higher than the density of polysilicon layer 303, follow-up while carrying out the higher treatment process of temperature, such as: following adopted chemical vapor deposition method forms hard mask layer and relevant etching technics on polysilicon 303, nitrogen silicon compound 304 can effectively stop airborne oxygen element to arrive the surface of Semiconductor substrate 300 through polysilicon layer 303 and high K dielectric layer, under the environment of high temperature, the pasc reaction that prevents oxygen element and Semiconductor substrate 300 surfaces forms oxide, oxide can make the thickness thickening of boundary material layer 301, when subsequent etching boundary material layer 301 forms boundary layer, the thickness that makes boundary layer also can thickening, make the actual (real) thickness of boundary layer and the design thickness of boundary layer occur deviation, affect transistorized performance and stable type.
The temperature of described the first annealing is 300 ~ 1000 degrees Celsius, the first annealing time is 5 ~ 200 seconds, the pressure of the first annealing chamber is 0.5 ~ 780 holder, make the first annealing form nitrogen silicon compound 304 thinner thicknesses, compactness is better, and cover uniformly the surface of polysilicon layer 303, can more effective isolation from oxygen element.
The gas passing into when described the first annealing also comprises N
2o, makes nitrogen silicon compound 304 contain more SiON, to strengthen the isolation effect of nitrogen silicon compound 304.
Then, please refer to Fig. 7, to polysilicon layer 303(with reference to figure 6) carry out, after the first nitrogen treatment, on polysilicon layer 303, forming hard mask layer 305, described hard mask layer 305 has the opening of the nitrogen silicon compound 304 on exposed polysilicon layer 303 surface; Take described hard mask layer 305 as mask, along polysilicon layer 303, high K dielectric layer 302 and boundary material layer 301(described in opening etching with reference to figure 6), form be positioned at Semiconductor substrate 300 surfaces boundary layer 306, be positioned at the high-K gate dielectric layer 307 on boundary layer 306 and be positioned at the pseudo-grid 308 on high K dielectric layer 307.Remaining part nitrogen silicon compound 304 parts as pseudo-grid 308 on pseudo-grid 308.
The material of described hard mask layer 305 is amorphous carbon, SiN, SiON, SiCN, SiC or BN, and it is chemical vapor deposition method that hard mask layer 305 forms technique, and the opening in hard mask layer 305 forms by photoetching and etching technics.In the time forming hard mask layer 305, nitrogen silicon compound 304 can effectively stop airborne oxygen element through polysilicon layer 303.
The technique of etch polysilicon layer 303 is plasma etching, and the gas that plasma etching adopts is HBr and Cl
2, because the nitrogen silicon compound 304 on polysilicon layer 303 surfaces is thinner, the etching nitrogen silicon compound that plasma etching can be easier, therefore without extra etch step with etching nitrogen silicon compound.
Then, please refer to Fig. 8, described pseudo-grid 308 are carried out to the second nitrogen treatment, form nitrogen silicon compound 309 in the sidewall surfaces of described pseudo-grid 308.Nitrogen silicon compound 309 is as a part for pseudo-grid 308.
Carry out the second nitrogen treatment, sidewall surfaces at described pseudo-grid 308 forms thinner nitrogen silicon compound 309, the nitrogen silicon compound 309 of sidewall surfaces and the nitrogen silicon compound 304 of pseudo-grid top surface of pseudo-grid 308, make pseudo-grid with outside isolated, follow-up while carrying out the higher treatment process of temperature, such as: while adopting depositing operation to form side wall and dielectric layer, oxygen element in prevention environment is through the surface of the Semiconductor substrate 300 under sidewall and the top surface arrival boundary layer 306 of pseudo-grid 308, under the environment of high temperature, form silica and make the thickness thickening of boundary layer 306 with pasc reaction in Semiconductor substrate 300, the transistorized stability that impact forms.
Described the second nitrogen treatment is the second annealing, passes into gas NH when the second annealing
3, the temperature of described the second annealing is 300 ~ 1000 degrees Celsius, and the second annealing time is 5 ~ 200 seconds, and the pressure of the second annealing chamber is 0.5 ~ 780 holder, and the gas passing into when described the second annealing also comprises N
2o, the thinner thickness of nitrogen silicon compound 309 that the sidewall surfaces of pseudo-grid 308 is formed, compactness is better, and covers uniformly the surface of the sidewall of pseudo-grid 308.
Then, please refer to Fig. 9, remove described hard mask layer 305(with reference to figure 8); Form interlayer dielectric layer 310 at described semiconductor substrate surface 300, the surface of interlayer dielectric layer 310 flushes with pseudo-grid 308 top surfaces.
The technique of removing described hard mask layer 305 is dry method or wet-etching technology, removes after hard mask layer 305, also comprises: form side wall (not shown) at the both sides of described pseudo-grid 308 sidewall; Take described pseudo-grid 308 and side wall as mask, the Semiconductor substrate 300 of described pseudo-grid 308 both sides is carried out to Implantation, in the transistorized source/drain region of the interior formation of Semiconductor substrate 300 of pseudo-grid 308 both sides (not shown).
Finally, please refer to Figure 10 and Figure 11, remove described pseudo-grid 308(and comprise the nitrogen silicon compound 304 of pseudo-grid 308 top surfaces and the nitrogen silicon compound 309 of both sides sidewall surfaces), form groove 311; Functional layer 312 is formed on sidewall and bottom at groove 311; In groove 311, fill full metal, form metal gates.
The material of described functional layer 312 is Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN or TiAlN.
Described metal be Al, Cu, Ti, Ag, Au, Pt, Ni wherein one or more
To sum up, the formation method of embodiment of the present invention metal gates, forming after polysilicon layer, described polysilicon layer is carried out to the first nitrogen treatment, form nitrogen silicon compound on polysilicon layer surface, because the density of nitrogen silicon compound is greater than the density of polysilicon, therefore can effectively stop airborne oxygen element to arrive the surface of Semiconductor substrate through polysilicon layer, follow-up while carrying out various technique, prevent that oxygen element from forming silica with the pasc reaction of semiconductor substrate surface under the environment of high temperature, oxide can make the thickness thickening of boundary material layer, when subsequent etching boundary material layer forms boundary layer, the thickness that makes boundary layer also can thickening, make the actual (real) thickness of boundary layer and the design thickness of boundary layer occur deviation, affect transistorized performance and stable type.
Further, the temperature of described the first annealing is 300 ~ 1000 degrees Celsius, and the first annealing time is 5 ~ 200 seconds, the pressure of the first annealing chamber is 0.5 ~ 780 holder, make the first annealing form nitrogen silicon compound thinner thickness, compactness is better, and covers uniformly the surface of polysilicon layer.
Further, carry out the second nitrogen treatment, sidewall surfaces at described pseudo-grid forms thinner nitrogen silicon compound, the nitrogen silicon compound of sidewall surfaces and the nitrogen silicon compound of pseudo-grid top surface of pseudo-grid, make pseudo-grid with outside isolated, follow-up while carrying out the higher treatment process of temperature, such as: while adopting depositing operation to form side wall and dielectric layer, oxygen element in prevention environment is through the surface of the Semiconductor substrate under sidewall and the top surface arrival boundary layer of pseudo-grid, under the environment of high temperature, form silica and make the thickness thickening of boundary layer with pasc reaction in Semiconductor substrate, the transistorized stability that impact forms.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (13)
1. a formation method for metal gates, is characterized in that, comprising:
Semiconductor substrate is provided;
Form successively boundary material layer, high K dielectric layer and polysilicon layer at described semiconductor substrate surface; The first nitrogen treatment is carried out in described polysilicon layer surface, form nitrogen silicon compound on polysilicon layer surface;
After the first nitrogen treatment, form hard mask layer on polysilicon layer, described hard mask layer has the opening of the nitrogen silicon compound on exposed polysilicon layer surface;
Along polysilicon layer, high K dielectric layer and boundary material layer described in opening etching, form be positioned at semiconductor substrate surface boundary layer, be positioned at the high-K gate dielectric layer on boundary layer and be positioned at the pseudo-grid on high K dielectric layer;
Form interlayer dielectric layer at described semiconductor substrate surface, the surface of interlayer dielectric layer flushes with pseudo-grid top surface;
Remove described pseudo-grid, form groove;
In groove, fill full metal, form metal gates.
2. the formation method of metal gates as claimed in claim 1, is characterized in that, the material of described boundary layer is silica or silicon oxynitride.
3. the formation method of metal gates as claimed in claim 1, is characterized in that, the thickness of described boundary layer is 5 ~ 30 dusts.
4. the formation method of metal gates as claimed in claim 1, is characterized in that, described the first nitrogen treatment is the first annealing, passes into gas NH when the first annealing
3.
5. the formation method of metal gates as claimed in claim 4, is characterized in that, the temperature of described the first annealing is 300 ~ 1000 degrees Celsius, and the first annealing time is 5 ~ 200 seconds, and the pressure of the first annealing chamber is 0.5 ~ 780 holder.
6. the formation method of metal gates as claimed in claim 4, is characterized in that, the gas passing into when described the first annealing also comprises N
2o.
7. the formation method of metal gates as claimed in claim 1, is characterized in that, before forming interlayer dielectric layer, also comprises: described pseudo-grid are carried out to the second nitrogen treatment, form nitrogen silicon compound in the sidewall surfaces of described pseudo-grid.
8. the formation method of metal gates as claimed in claim 7, is characterized in that, described the second nitrogen treatment is the second annealing, passes into gas NH when the second annealing
3.
9. the formation method of metal gates as claimed in claim 8, is characterized in that, the temperature of described the second annealing is 300 ~ 1000 degrees Celsius, and the second annealing time is 5 ~ 200 seconds, and the pressure of the second annealing chamber is 0.5 ~ 780 holder.
10. the formation method of metal gates as claimed in claim 8, is characterized in that, the gas passing into when described the second annealing also comprises N
2o.
The formation method of 11. metal gates as claimed in claim 1, is characterized in that, also comprises: form diffusion impervious layer on described high K dielectric layer surface; In the atmosphere of ammonia, described high K dielectric layer and diffusion impervious layer are annealed.
The formation method of 12. metal gates as claimed in claim 1, is characterized in that, also comprises: form side wall at the both sides of described pseudo-grid sidewall.
The formation method of 13. metal gates as claimed in claim 1, is characterized in that, also comprises: sidewall and lower surface at described groove form functional layer.
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| CN105206523A (en) * | 2015-10-14 | 2015-12-30 | 上海华力微电子有限公司 | Method for manufacturing high-K dielectric layer |
| CN105826260A (en) * | 2015-01-08 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN106298491A (en) * | 2016-11-09 | 2017-01-04 | 上海华力微电子有限公司 | A kind of forming method of high-K metal gate |
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| US6093590A (en) * | 1999-09-14 | 2000-07-25 | Worldwide Semiconductor Manufacturing Corp. | Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant |
| US20020064964A1 (en) * | 2000-10-13 | 2002-05-30 | Hynix Semiconductor Inc. | Method for forming damascene metal gate |
| US20050253173A1 (en) * | 2004-04-27 | 2005-11-17 | Chih-Hao Wang | Dual work-function metal gates |
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| US6093590A (en) * | 1999-09-14 | 2000-07-25 | Worldwide Semiconductor Manufacturing Corp. | Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant |
| US20020064964A1 (en) * | 2000-10-13 | 2002-05-30 | Hynix Semiconductor Inc. | Method for forming damascene metal gate |
| US20050253173A1 (en) * | 2004-04-27 | 2005-11-17 | Chih-Hao Wang | Dual work-function metal gates |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105826260A (en) * | 2015-01-08 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN105826260B (en) * | 2015-01-08 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN105206523A (en) * | 2015-10-14 | 2015-12-30 | 上海华力微电子有限公司 | Method for manufacturing high-K dielectric layer |
| CN106298491A (en) * | 2016-11-09 | 2017-01-04 | 上海华力微电子有限公司 | A kind of forming method of high-K metal gate |
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