CN103793572A - Method for inspecting PCB packaged bonding pads - Google Patents

Method for inspecting PCB packaged bonding pads Download PDF

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Publication number
CN103793572A
CN103793572A CN201410051265.4A CN201410051265A CN103793572A CN 103793572 A CN103793572 A CN 103793572A CN 201410051265 A CN201410051265 A CN 201410051265A CN 103793572 A CN103793572 A CN 103793572A
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CN
China
Prior art keywords
bonding pads
pcb
welding
attribute
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410051265.4A
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Chinese (zh)
Inventor
杜光芹
于治楼
翟西斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inspur Group Co Ltd
Original Assignee
Inspur Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inspur Group Co Ltd filed Critical Inspur Group Co Ltd
Priority to CN201410051265.4A priority Critical patent/CN103793572A/en
Publication of CN103793572A publication Critical patent/CN103793572A/en
Pending legal-status Critical Current

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Abstract

The invention provides a method for inspecting PCB packaged bonding pads. The method includes the steps of carrying out attribute setting on the PCB packaged bonding pads, and adding the two attributes PM and SM including welding assisting layers and welding resisting layers, wherein when the welding assisting layers and the welding resisting layers exist in the bonding pads, attribute values are one, and when the welding assisting layers and the welding resisting layers do not exist in the bonding pads, the attribute values are zero; inspecting the bonding pads in a PCB, carrying out logic XOR operation on the two attributes, reporting errors when the logic XOR operation result of the PM and the SM is zero to explain that the attribute welding assisting layers or the attribute welding resisting layers of the bonding pads have faults, and then carrying out inspection and modification. Compared with the prior art, the method for inspecting the PCB packaged bonding pads has the advantages that the accuracy of the bonding pads is guaranteed, welding and manufacturing of the PCB are prevented from being influenced by the fact that certain attributes are missed due to manual reasons, the welding quality and the design efficiency of the PCB are accordingly improved, and the method is high in practicability and easy to popularize.

Description

A kind of inspection method of PCB encapsulation welding tray
Technical field
The present invention relates to a kind of automatic electronic technical field, specifically a kind of inspection method of PCB encapsulation welding tray.
Background technology
Along with the complexity of PCB design is increasing, device on pcb board is more and more, while doing pad, sometimes miss unavoidably some attributes, in PCB, check out by artificial being difficult to, therefore the inspection of encapsulation storehouse pad has been helped in the urgent need to platform software, even if use assistant software in prior art, still can not well improve PCB welding quality and design efficiency, based on this, now provide a kind of inspection method of PCB encapsulation welding tray of the problem that can easily find PCB encapsulation welding tray design existence.
Summary of the invention
Technical assignment of the present invention is to solve the deficiencies in the prior art, provides a kind of artificial origin of avoiding to miss some attributes and affects the inspection method of the welding of PCB and the PCB encapsulation welding tray of manufacture.
Technical scheme of the present invention realizes in the following manner, the inspection method of this kind of PCB encapsulation welding tray, and its specific implementation process is: 1) each pad of PCB encapsulation is carried out to setup of attribute, increase and help layer and two attribute PM of solder mask and SM;
2) PM=1 in the time that pad existence helps layer, otherwise PM=0;
3) SM=1 in the time that pad exists solder mask, otherwise SM=0;
4) two attributes are carried out to logic XOR, calculate the value of PM ⊕ SM;
5) in the time of PM ⊕ SM=0, report an error, now pad attribute helps layer or solder mask to have omission, then checks and revises;
6) reexamine, reach requirement until work as PM ⊕ SM=1.
The beneficial effect that the present invention compared with prior art produced is:
The inspection method of a kind of PCB encapsulation welding tray of the present invention is by the inspection to PCB encapsulation welding tray, guarantee the accuracy of pad, avoid artificial origin to miss some attributes and affect welding and the manufacture of PCB, thereby improve PCB welding quality and design efficiency, practical, be easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 is checking process process flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the inspection method of a kind of PCB encapsulation welding tray of the present invention is described in detail below.
As shown in Figure 1, the inspection method of this kind of PCB encapsulation welding tray, its specific implementation process is:
1) each pad of PCB encapsulation is carried out to setup of attribute, increase and help layer Pastemask and two attribute PM of solder mask Soldermask and SM;
2) PM=1 in the time that pad existence helps layer Pastemask, otherwise PM=0;
3) SM=1 in the time that pad exists solder mask Soldermask, otherwise SM=0;
4) two attributes are carried out to logic XOR, calculate the value of PM ⊕ SM;
5) in the time of PM ⊕ SM=0, report an error, now pad attribute helps layer or solder mask to have omission, then checks and revises;
6) reexamine, reach requirement until work as PM ⊕ SM=1.
PCB encapsulation welding tray inspection method of the present invention, is conducive to find the problem that exists in the design of PCB encapsulation welding tray improve the quality of PCB welding, improves PCB design efficiency.
The foregoing is only embodiments of the invention, within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (1)

1. an inspection method for PCB encapsulation welding tray, is characterized in that its implementation procedure is:
1) each pad of PCB encapsulation is carried out to setup of attribute, increase and help layer and two attribute PM of solder mask and SM;
2) PM=1 in the time that pad existence helps layer, otherwise PM=0;
3) SM=1 in the time that pad exists solder mask, otherwise SM=0;
4) two attributes are carried out to logic XOR, calculate the value of PM ⊕ SM;
5) in the time of PM ⊕ SM=0, report an error, now pad attribute helps layer or solder mask to have omission, then checks and revises;
6) reexamine, reach requirement until work as PM ⊕ SM=1.
CN201410051265.4A 2014-02-14 2014-02-14 Method for inspecting PCB packaged bonding pads Pending CN103793572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410051265.4A CN103793572A (en) 2014-02-14 2014-02-14 Method for inspecting PCB packaged bonding pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410051265.4A CN103793572A (en) 2014-02-14 2014-02-14 Method for inspecting PCB packaged bonding pads

Publications (1)

Publication Number Publication Date
CN103793572A true CN103793572A (en) 2014-05-14

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ID=50669234

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410051265.4A Pending CN103793572A (en) 2014-02-14 2014-02-14 Method for inspecting PCB packaged bonding pads

Country Status (1)

Country Link
CN (1) CN103793572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104133967A (en) * 2014-08-01 2014-11-05 浪潮集团有限公司 PCB packaging silk-screen printing setting and pin silk-screen printing positioning inspection method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1575109A (en) * 2003-06-03 2005-02-02 三星电机株式会社 Method of forming solder resist pattern
CN1719447A (en) * 2004-07-07 2006-01-11 华为技术有限公司 Board pattern designing method of integrated designing element in printed circuit board and its device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1575109A (en) * 2003-06-03 2005-02-02 三星电机株式会社 Method of forming solder resist pattern
CN1719447A (en) * 2004-07-07 2006-01-11 华为技术有限公司 Board pattern designing method of integrated designing element in printed circuit board and its device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
于治楼 等: ""高速PCB的地线布线设计"", 《信息技术与信息化》 *
刘静波: ""分析"应用PROTEL 99SE设计原理图和印制电路板"出现的问题"", 《中国现代教育装备》 *
车固勇: ""FPC焊盘设计类型选择导致的DFM问题及其对策"", 《2011中国电子制造与封装技术年会论文集》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104133967A (en) * 2014-08-01 2014-11-05 浪潮集团有限公司 PCB packaging silk-screen printing setting and pin silk-screen printing positioning inspection method

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Application publication date: 20140514