CN103780320B - Multiband data detection instrument based on FPGA - Google Patents
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Abstract
The present invention is claimed a kind of multiband data detection instrument based on FPGA, relates to wireless sensor network technology field.This multiband data detection instrument includes, wireless data acquisition module, data management and transport module, memory module, wireless data acquisition module is made up of the Receiver Module of 21 functional independences, each Receiver Module is responsible for the data acquisition of a channel, complete 16 channels of 2.4GHz frequency range, 4 channels of 780MHz frequency range and the collection of 1 channel wireless data message of 433MHz frequency range, host computer is passed to data management module, data management module scheduling channel by Ethernet by Serial Port Transmission；Memory module controls a serial ports receiver, receives the serial bit stream from Receiver Module.Being buffered in total FIFO by data message time-stamped for all channels, finally, the data message after processing uploads to host computer by network interface and does protocal analysis.
Description
Technical field
The present invention relates to wireless industrial Internet of Things field, be specifically related to the test of wireless industrial Internet of Things sensing network
Multiband data detection method based on FPGA in system.
Technical background
Along with the development of Internet of Things, its sensing layer wireless network has permeated in multiple frequency ranges, such as 433MHz frequency
Section, 780MHz frequency range and 2.4GHz frequency range, network data analysis the most required in R&D process, or
Popularizing at network security assessment, fault diagnosis and Internet of Things subject, a monitoring wireless network packet
Data detection instrument be necessary.Along with the existing public affairs of the data detection instrument developing each separate frequency bands of Internet of Things
Department develops, but all can not capture the wireless data packet of multiple frequency range simultaneously.Such as Texas Instruments
SmartRF protocol software bag audiomonitor, can obtain one channel of 2.4GHz frequency range and less than 1GHz frequency range one
The wireless data packet of individual channel, it is adaptable to ZigBee and IEEE802.15.4 network；Guangzhou causes remote electronics
The ZigBee data packet analysis instrument of company limited, supports 2.4GHz RF network, serves mainly to facilitate user and catch
Obtain Zigbee network packet；The packet audiomonitor supporting 780MHz frequency range has existed, as Nanjing is vast
The 780MHz Zig Bee data detection instrument of Zhi Xian Electronic Science and Technology Co., Ltd., also for Zig Bee network
Packet is analyzed.The most above-mentioned, current already present data detection instrument is just for certain independent frequency
Section or certain channel of certain frequency range carries out channel acquisition.Therefore, one can capture three frequency range institutes simultaneously
There are channel (totally 21 channels: 16 channels of 2.4G frequency range, 4 channels, 433MHz of 780MHz frequency range
1 channel of frequency range) the data detection instrument of data message significant for the development of Internet of Things.
The content of invention
The present invention is directed to existing data detection instrument and can only detect the single channel of separate frequency bands or separate frequency bands
Technological deficiency, it is provided that a set of multiband Data Detection based on FPGA for industrial wireless sensing net
Instrument.This detector can to three frequency ranges of the industrial wireless sensing net of 433MHz, 780MHz and 2.4GHz altogether
Count 21 channel datas to detect simultaneously.
The present invention solves the technical scheme of above-mentioned technical problem, proposes a kind of multiband data based on FPGA
Detector, including: wireless data acquisition module, data management and transport module, memory module, wherein,
Wireless data acquisition module is made up of the Receiver Module of 21 functional independences, and each Receiver Module is born
The data acquisition of one channel of duty, completes 21 of 2.4GHz frequency range, 780MHz frequency range and 433MHz frequency range
The collection of channel wireless data message, for wireless data message add packet header, bag tail, channel number, length,
Link-quality instruction LQI value and receiving sensitivity RSSI value, by Serial Port Transmission to data management and transmission mould
Block；Data management and transport module include FPGA data processing unit and radio-frequency module, and this module controls to deposit
The data cached message of reservoir load time stamp, the message adding timestamp is passed to host computer by scheduling channel.
Memory module includes asynchronous data FIFO, and memory module controls a serial ports receiver, receives from penetrating
Frequently the serial bit stream of receiver module, removes start bit, and transfers data to asynchronous with 8bit parallel form
In data FIFO, produce the write enable signal of asynchronous data FIFO, start byte enables signal and knot simultaneously
Bundle byte enables signal.Start byte in 1843200Hz time domain is enabled letter by data management and transport module
Number Start_bytes_en and end byte enable signal Finish_bytes_en and are synchronized to the time domain of 50MHz
In, the start byte that serial ports receiver produces enables signal Start_bytes_en triggering timing device timer note
Record present channel timestamp, end byte enables signal Finish_bytes_en and triggers scheduling channel gating letter
Number channel_en.Synchronization module uses Edge check lock unit, start byte enables signal and terminates word
Joint enables signal and is synchronized to fast clock zone by slow clock zone, the digital circuit of edge synchroniser, slow clock zone
Signal, by a trigger on slow clock zone, is directly entered in first trigger of lock unit, soon
Generation one and fast clock cycle etc. after in clock zone, input signal negates with the output of last trigger
Wide, the effective pulse signal of high level, is the fast_trigger_o signal after synchronization.Timer periods
Stamp form is the data form of 7 bytes, including: minute territory of 2 bytes, the second territory of 1 byte, 2 bytes
Millisecond territory and the millisecond territory of 2 bytes, use 4 enumerators to be respectively minute chronograph
Min_counter [15:0], second enumerator sec_counter [7:0], millisecond counter ms_counter [15:0]
With millisecond counter us_counter [15:0], the clock of the 50MHz that the clock of current time uses, often warp
After spending 50 clock cycle, millisecond counter us_counter adds 1, is added to 999 clearings；Often through 50000
After clock cycle, millisecond counter ms_counter adds 1, when being added to 999 clearings；Often through 50000000 time
Clock week after date second enumerator sec_counter adds 1, when being added to 59 clearings；Often through 3000000000 clocks
Week, after date minute counter min_counter added 1, reset when counting down to maximum.The wireless data of each channel
After message and timestamp thereof are buffered in respective FIFO, when the end byte after certain channel synchronization enables
Signal just sets high present channel and enables signal when arriving, until receiving the whole end-of-packet signal from sending module,
Just disable this channel and enable signal.When data message transmission, transport module order reads 21 data FIFO
With 21 timestamp FIFO, the timestamp of each channel is added on after message simultaneously, produces and write control letter
Number by radio-frequency module receive message and timestamp be stored in total FIFO.
Present invention multiband based on FPGA data detection instrument can capture simultaneously 433MHz, 780MHz and
21 channel data message of three frequency ranges of 2.4GHz.This multiband data detection instrument receives from radio frequency reception
The serial bit stream of module, removes the start bit of serial bit stream, transfers data to asynchronous with parallel form
In data pushup storage FIFO, produce writing of asynchronous data pushup storage FIFO simultaneously and make
Energy signal, start byte enable signal and end byte enables signal, it is thus achieved that synchronizing signal.Realize data inspection
Survey instrument 433MHz, 780MHz and 2.4GHz 21 channel data message of tri-frequency ranges are captured simultaneously.
The phase that the data message received from 21 radio-frequency modules (21 channels) and FPGA main control module are produced
Answer timestamp to be respectively stored in 21 data pushup storage FIFO and 21 timestamp FIFOs are deposited
In reservoir FIFO.When data message transmission, transport module order reads 21 data FIFO storages
Device FIFO and 21 timestamp pushup storage FIFO, is added on the timestamp of each channel simultaneously
After corresponding message, message and timestamp that radio-frequency module is received by generation write control signal are stored in total elder generation
Enter first to go out in memorizer FIFO.Data message adds timestamp and is easy to host computer protocal analysis.
Accompanying drawing explanation
Fig. 1 multiband data detection instrument functional structure chart；
Fig. 2 multiband data detection instrument General layout Plan figure；
Fig. 3 multiband data detection instrument system construction drawing.
Detailed description of the invention
Below in conjunction with the accompanying drawings and instantiation, the present invention is further made a concrete analysis of and describes.
It is illustrated in figure 1 multiband data detection instrument functional block diagram, specifically includes that data acquisition
Module, data management and transport module and power management module.
Wireless data acquisition module monitors the wireless data message of three frequency ranges, then the wireless data report by capture
Literary composition is passed to data management module after treatment and is processed.Wireless data acquisition module is according to gathering data frequency
Section includes: 433MHz, 780MHz and 2.4GHz frequency range wireless data acquisition module, it is right to be respectively completed
16 channels of 1 channel of 433MHz frequency range, 4 channels of 780MHz frequency range and 2.4GHz frequency range without
The capture of line data, adds packet header, bag tail, channel number, length, LQI(chain for wireless data message simultaneously
The instruction of road quality) value and RSSI(receiving sensitivity) after value, then by Serial Port Transmission to data management module.
Data management module caching, from the data message of 21 radio-frequency modules, meanwhile, records each channel data message
Timestamp during arrival, then by the timestamp caching of record, by United Dispatching, complete each channel wireless number
According to orderly being transferred in internal storage of message and timestamp, data management module uses FPGA to realize.
Transport module reads data message and the timestamp of caching, is transferred to ether by the way of network interface uses UDP
Net, and then pass to PC.In the process power management management module complete to wireless data detection module with
Data management and the power supply of transport module, it is desirable to the output providing enough meets system maximum load, with
Shi Yaoqiu power supply ripple is small, it is ensured that the reliability service of system.
Be illustrated in figure 2 multiband data detection instrument design block diagram, including FPGA core core hardware circuit and
Wireless radio frequency modules interface circuit.FPGA core core hardware circuit includes power circuit, clock circuit, answers
Position circuit, FPGA configuration circuit, GPIO expanded circuit, memory module circuit and network interface communication module electricity
Road；Wireless radio frequency modules interface includes 21 radio-frequency module interface circuits.FPGA internal data processing unit
Logic completes the verilog HDL of 21 channel data cache modules and data control based on Nios II processor
System and transmission unit；Radio-frequency module includes that 433MHz, 780MHz and 2.4GHz frequency range less radio-frequency receives
Module.
It is illustrated in figure 3 multiband data detection instrument system construction drawing.Wireless data acquisition module is by 21 functions
Independent Receiver Module is constituted, and includes 16 channels of 2.4GHz frequency range corresponding 16 respectively solely
Corresponding 4 the independent Receiver Modules of vertical Receiver Module, 4 channels of 780MHz frequency range,
1 independent Receiver Module that 1 channel of 433MHz frequency range is corresponding, and the reception write
Download program is in corresponding independent radio frequency receiver module.Each Receiver Module is responsible for a channel
Data acquisition, can complete 16 channels of 2.4GHz frequency range, 4 channels of 780MHz frequency range and 433MHz
The collection of 1 channel wireless data message of frequency range, and add packet header, bag tail, channel for wireless data message
Number, the instruction of length, LQI(link-quality) value and RSSI(receiving sensitivity) value.Then serial ports is passed through
Transfer data to data management module, when the data management module with FPGA as core is by 1843200Hz
It is same that start byte in territory enables signal Start_bytes_en and end byte enable signal Finish_bytes_en
Walking in the time domain of 50MHz, the start byte that serial ports receiver produces enables signal Start_bytes_en and touches
Sending out timer timer and record present channel timestamp, end byte enables signal Finish_bytes_en and triggers tune
Degree channel gating signal channel_en.Use Edge check lock unit, start byte is enabled signal and end
Byte enables signal and is synchronized to fast clock zone, Edge check lock unit, the signal of slow clock zone by slow clock zone
By the trigger on slow clock zone, enter in first trigger of Edge check lock unit, at fast clock
In territory, two all after dates of input signal time delay negate with the output of last trigger of Edge check lock unit
Rear generation one is wide with the fast clock cycle, the effective pulse signal of high level, is the letter of the triggering after synchronization
Number fast_trigger_o signal.Clock circuit timer periods stamp form is the data form of 7 bytes, bag
Include: minute territory of 2 bytes, the second territory of 1 byte, the millisecond territory of 2 bytes and the microsecond territory of 2 bytes, use
4 enumerators be respectively minute chronograph min_counter [15:0], second enumerator sec_counter [7:0], in the least
Second enumerator ms_counter [15:0] and microsecond enumerator us_counter [15:0], the clock of current time uses
The clock of 50MHz, often after 50 clock cycle, millisecond counter us_counter adds 1, is added to
999 reset；Often after 50000 clock cycle, millisecond counter ms_counter adds 1, clear when being added to 999
Zero；Often after 50000000 clock cycle, second enumerator sec_counter adds 1, when being added to 59 clearings；
Often after 3000000000 clock cycle, minute counter min_counter adds 1, resets when counting down to maximum.
The wireless data message of each channel and timestamp thereof are buffered in respective FIFO(pushup storage)
After in, just set high present channel enable signal when signal arrives when the end byte after certain channel synchronization enables,
Until receiving the whole end-of-packet signal from sending module, just disabling this channel and enabling signal.When transmission data
During message, transport module order reads 21 data FIFO(pushup storages) and 21 timestamps
FIFO(pushup storage), the timestamp of each channel is added on after message simultaneously, produces and write control
Message and timestamp that radio-frequency module is received by signal processed are stored in total FIFO(pushup storage) in.
The asynchronous reset signal of transport module makes transmission state machine enter idle(holding state) state, owns simultaneously
Depositor reset, the next clock cycle enters state_Transmit_Data_1(data transmission state)
State, enables when channel 1 enables signal channel_1_en(channel 1) for high, the whole bag of channel 1 simultaneously
End byte enables signal data_package_finish_1(packet end of transmission) and the data of channel 1
When FIFO reading spacing wave is all low, state keeps, sets high channel 1 data FIFO reading request signal simultaneously
Ata_fifo_rdreq_1 enables signal load_data_1(loading data with the loading of channel 1), wherein fill
Carrying enable signal load_data_1 utilizes one all after dates total FIFO's of generation of d type flip flop time delay to write enable letter
Number；Being low when channel 1 enables signal channel_1_en, state machine is directly entered
State_Transmit_Data_2 state；When channel 1 enables signal channel_1_en for high and channel 1
Whole bag sends when terminating to enable signal data_package_finish_1 arrival, and state transition is to state
State_Transmit_Time_1(time state transmits).Under state_Transmit_Time_1 state,
When clock counter time_bytes_counter does not count down to 7, and channel 1 timestamp FIFO does not has simultaneously
When being read empty, state keeps, juxtaposition inc_time_bytes_counter, (time byte counter)
Timer_fifo_rdreq_1(time FIFO read request) and the load_time_1(loading time) it is 1,
Wherein time_bytes_counter is used for counting the byte number reading timestamp；When timestamp byte number counts
When device is more than 7, state transfers to state_Transmit_Data_2, puts clearing enumerator simultaneously and enables signal
Clr_time_bytes_counter and whole end-of-packet signal package_finish_1 is high.Other state
Jump condition and output signal thereof are similar to, the only coherent signal of different channels.When state is
During state_Transmit_Data_21, it is height when channel 21 enables signal channel_21_en, believes simultaneously
The whole bag in road 21 sends and terminates to enable signal data_package_finish_21 and data FIFO of channel 21
When reading spacing wave is all low, state keeps, and exports the reading request signal of channel 21 data FIFO simultaneously
Data_fifo_rdreq_21 enables signal load_data_21 with the loading of channel 21, wherein loads enable
Signal load_data_21 utilizes one all after date of d type flip flop time delay to produce the write enable signal of total FIFO；
Being low when channel 21 enables signal channel_21_en, state machine is directly entered idle state；Work as channel
21 enable signal channel_21_en are high and the whole end-of-packet of channel 21 enables signal
Data_package_finish_21(packet terminates) arrive time, state transition arrives
State_Transmit_Time_1 state, reads the timestamp of 21 channels.Reading reenters down after terminating
One takes turns cycle of states.Above procedure completes 21 letters of tri-frequency ranges of 433MHz, 780MHz and 2.4GHz
Track data acquisition process and transmission.
It is low that this multiband data detection instrument has packet loss, and capacity of resisting disturbance is strong, the feature of good stability, it is possible to
Meet the demand of Internet of Things testing service platform.
Claims (3)
1. multiband data detection instrument based on FPGA, including: wireless data acquisition module, data management and transport module, memory module, it is characterized in that, wireless data acquisition module is made up of the Receiver Module of 21 functional independences, each Receiver Module is responsible for the data acquisition of a channel, complete 2.4GHz frequency range, the collection of 21 channel wireless data messages of 780MHz frequency range and 433MHz frequency range, packet header is added for wireless data message, bag tail, channel number, length, link-quality instruction LQI value and receiving sensitivity RSSI value, by Serial Port Transmission to data management and transport module；nullData management module receives the data message from 21 radio-frequency modules，Record the timestamp that each channel data message arrives，Again by the timestamp caching of record，Dispatch each channel data message and timestamp is transferred to memory module in order，And obtain synchronizing signal，Transport module reads data message and the timestamp of caching，UDP mode is used to be transferred to host computer，Data management module scheduling channel specifically includes，Start byte in 1843200Hz time domain is enabled signal Start_bytes_en by FPGA data processing unit and end byte enables signal Finish_bytes_en and is synchronized in the time domain of 50MHz，The start byte that Receiver Module serial ports receiver produces enables signal Start_bytes_en triggering timing device record present channel timestamp，End byte enables signal Finish_bytes_en and triggers scheduling channel gating signal channel_en,Synchronization module uses Edge check lock unit，Start byte is enabled signal and end byte enables signal and is synchronized to fast clock zone by slow clock zone，The digital circuit of edge synchroniser，The signal of slow clock zone is by a trigger on slow clock zone，It is directly entered in first trigger of lock unit，After input signal negates with the output of last trigger in the fast clock domain, generation one is wide with the fast clock cycle、The effective pulse signal of high level，It is the fast_trigger_o signal after synchronization，When data message transmission，Transport module order reads 21 data FIFO and 21 timestamp FIFO，The timestamp of each channel is added on after message simultaneously，Message and timestamp that radio-frequency module is received by generation write control signal are stored in total FIFO；Memory module includes asynchronous data pushup storage FIFO, dispatch each channel data message and timestamp is transferred to memory module in order and includes, memory module controls a serial ports receiver, the data message of each channel and timestamp thereof are buffered in respective pushup storage FIFO, present channel enable signal is set high when signal arrives when the end byte after certain channel synchronization enables, until receiving the whole end-of-packet signal from sending module, disabling this channel and enabling signal；When data message transmission, transport module order reads 21 data pushup storage FIFO and 21 timestamp pushup storage FIFO, being added on after message by the timestamp of each channel, message and timestamp that radio-frequency module is received by generation write control signal are stored in total pushup storage FIFO simultaneously.
Multiband data detection instrument the most according to claim 1, it is characterized in that, acquisition synchronizing signal specifically includes: memory module uses Edge check lock unit, start byte is enabled signal and end byte enables signal and is synchronized to fast clock zone by slow clock zone, the signal of slow clock zone is by the trigger on slow clock zone, it is directly entered in first trigger of Edge check lock unit, two cycles of input signal time delay in the fast clock domain, after negating with the output of last trigger of Edge check lock unit, generation one is wide with the fast clock cycle, the effective pulse signal of high level, it is synchronizing signal.
Multiband data detection instrument the most according to claim 1, it is characterized in that, timer periods stamp form is the data form of 7 bytes, including: minute territory of 2 bytes, the second territory of 1 byte, the millisecond territory of 2 bytes and the microsecond territory of 2 bytes, using 4 enumerators to be respectively minute chronograph min_counter [15:0], second enumerator sec_counter [7:0], millisecond counter ms_counter [15:0] and microsecond enumerator us_counter [15:0], the clock of current time uses 50MHz clock.
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| CN104936220B (en) * | 2015-04-30 | 2018-06-12 | 无锡悟莘科技有限公司 | Space interference detection method based on 2.4G frequency ranges |
| CN104936213B (en) * | 2015-04-30 | 2018-06-12 | 无锡悟莘科技有限公司 | A kind of interactive hand-held terminal |
| CN104994476B (en) * | 2015-06-25 | 2018-07-06 | 苏州市英富美欣科技有限公司 | The data transmission method of network node based on 2.4G frequency ranges |
| CN105050098B (en) * | 2015-06-25 | 2019-02-01 | 苏州市英富美欣科技有限公司 | The network-building method of network node based on 2.4G frequency range |
| CN105162537B (en) * | 2015-06-25 | 2017-09-19 | 苏州市英富美欣科技有限公司 | A kind of interactive hand-held terminal based on 2.4G frequency ranges |
| CN104936196B (en) * | 2015-06-25 | 2018-05-01 | 苏州市英富美欣科技有限公司 | Gateway installation site acquisition methods based on 2.4G frequency ranges |
| CN104932282B (en) * | 2015-06-25 | 2017-10-03 | 苏州市英富美欣科技有限公司 | A kind of Interactive control switch based on 2.4G frequency ranges |
| CN104902590B (en) * | 2015-06-25 | 2018-06-05 | 苏州市英富美欣科技有限公司 | A kind of interactive gateway based on 2.4G frequency ranges |
| CN105867295A (en) * | 2016-06-03 | 2016-08-17 | 浪潮通用软件有限公司 | Communication method and upper computer |
| CN106789410B (en) * | 2016-12-07 | 2020-04-07 | 山东省科学院自动化研究所 | CAN network intelligent monitoring system and monitoring method based on Bluetooth and OBD |
| CN112865901B (en) * | 2019-11-28 | 2023-04-07 | 郑州芯兰德网络科技有限公司 | High-speed data packet acquisition system and method based on FPGA nanosecond timestamp |
| CN113395270A (en) * | 2021-06-07 | 2021-09-14 | 中嘉能源管理（北京）有限公司 | Thermal original data acquisition equipment, method and system |
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