CN103779270A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN103779270A CN103779270A CN201210415061.5A CN201210415061A CN103779270A CN 103779270 A CN103779270 A CN 103779270A CN 201210415061 A CN201210415061 A CN 201210415061A CN 103779270 A CN103779270 A CN 103779270A
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- drain electrode
- contact hole
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000005516 engineering process Methods 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 61
- 230000004888 barrier function Effects 0.000 claims description 33
- 230000009977 dual effect Effects 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000004062 sedimentation Methods 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 abstract description 19
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
The invention provides a method for manufacturing a semiconductor device and relates to semiconductor technical field. The method comprises: a step S101 of providing a semiconductor substrate on which a source electrode, a drain electrode, a dummy grid electrode, and a dummy grid electrode sidewall are formed; a step S102 of performing SPT treatment in order to remove a part of the dummy grid electrode sidewall; a step S103 of forming a contact hole etching shielding layer on the semiconductor substrate; a step S105 of etching the contact hole etching shielding layer in order to form an opening over the source electrode and the drain electrode; and a step S105 of metalizing the semiconductor substrate in order to form metal silicide on the source electrode and the drain electrode. According to the method for manufacturing a semiconductor device, metallization technology is executed by forming the contact hole etching shielding layer on the dummy grid electrode and forming the opening on positions, corresponding to the source electrode and the drain electrode, on the contact hole etching shielding layer. Thus, improper restriction on space caused by using a salicide block to execute metallization technology is prevented and yield of the devices is increased.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor device.
Background technology
In technical field of semiconductors, along with developing rapidly of semiconductor fabrication process, the area of semiconductor device (chip) is more and more less, and meanwhile, the quantity of the semiconductor device on a semiconductor chip is also more and more.In semiconductor circuit, the transmission of signal between semiconductor device needs highdensity metal interconnecting wires, in the etching of carrying out need to carrying out when metal interconnected contact hole.But, due in semiconductor device, between grid (such as metal gates) and source/drain electrode, generally there is difference in height, this has brought great challenge to contact through hole etching technics.
In the manufacturing process of semiconductor device, dual damascene (Dual damascene) technique is a kind of common technology means in the time of local interconnect.So-called dual damascene process etches the contact through hole a kind of common technology that the materials such as row metal fill of going forward side by side exactly on dielectric layer.At present, in semiconductor device manufacture, obtained application more widely, and dual damascene process is expected to become the mainstream technology that is applied in 20nm and following process node in the application of stage casing processing procedure.This dual damascene stage casing making technology, integrates traditional contact hole (CT) and traditional first layer metal (M1).But, metal silicide technology is a major challenge of dual damascene stage casing making technology, in the prior art, in front metal silicide (silicide-first) technique, owing to adopting silicide shielding layer (SAB, be salicideblock) realize metallization process, limit (SAB can occupy certain space that originally can form metal silicide) and be often easy to cause pipe effect (piping issue) due to space, cause device bad.Visible, in fabrication of semiconductor device, the related process before application dual damascene stage casing making technology is realized local interconnect, especially metal silicide technology, becomes one of principal element of restriction device performance.
In the prior art, the manufacture method of the semiconductor device of application of aforementioned technique, general main comprising the steps:
Step e 1: semi-conductive substrate is provided, and this Semiconductor substrate comprises dummy gate structure and source electrode and drain electrode.Generally speaking, this dummy gate structure comprises polysilicon dummy grid and dummy grid sidewall.
Step e 2: depositing silicon compound masking material film in described Semiconductor substrate, and by the figure of the technique such as photoetching, etching formation silicide shielding layer (SAB).
Step e 3: carry out silication technique for metal processing take described SAB as mask, form metal silicide (NiSi) in source electrode and the drain locations of Semiconductor substrate.
Step e 4: carry out stress and close on technology (SPT).
Step e 5: deposition contact hole etching barrier layer (CESL).
Step e 6: deposition interlayer dielectric layer (ILD) also carries out CMP processing.
Step e 7: form metal gates.
Abovementioned steps E1 to E7, has completed application dual damascene stage casing making technology and has realized local interconnect related process before, then, can carry out dual damascene stage casing making technology, to realize local interconnect.
In the manufacture method of this semiconductor device, realize metallization process owing to adopting silicide shielding layer (SAB), because (certain open space that SAB can occupy source electrode and drain electrode top) limit in space, be easy to cause source electrode and drain electrode fully to metallize, and then be often easy to cause pipe effect (piping issue), cause device bad.Therefore, need to propose a kind of manufacture method of new semiconductor device, to guarantee the realization of dual damascene stage casing making technology, improve the yield of semiconductor device.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, the method comprises the steps:
Step S101: Semiconductor substrate is provided, is formed with source electrode, drain electrode, dummy grid and dummy grid sidewall in described Semiconductor substrate;
Step S102: described Semiconductor substrate is carried out to stress and close on technical finesse, remove the described dummy grid sidewall of part;
Step S103: form contact hole etching barrier layer in described Semiconductor substrate;
Step S104: described in etching, contact hole etching barrier layer to form opening above described source electrode and drain electrode;
Step S105: described Semiconductor substrate is metallized to form metal silicide in described source electrode and drain electrode.
Wherein, preferred, source electrode and drain electrode that described source electrode and drain electrode are lifting.
Wherein, in described step S102, remove the part of described dummy grid sidewall away from described Semiconductor substrate, retain described dummy grid sidewall in the part between described dummy grid and described source electrode and between described dummy grid and described drain electrode.
Further, the described dummy grid sidewall of reservation is identical at the height of the height of part between described dummy grid and described source electrode and between described dummy grid and described drain electrode and the source electrode of described lifting and drain electrode.
Wherein, in described step S102, carrying out stress while closing on technical finesse, adopt dry etching.
Wherein, the described contact hole etching barrier layer forming in described step S103 is two stress liners or single stress liner.
Wherein, described step S 104 comprises:
Step S1041: form patterned photoresist above described contact hole etching barrier layer, described patterned photoresist covers the region of described Semiconductor substrate except described source electrode and drain electrode;
Step S1042: take described patterned photoresist as mask, etching is carried out in described contact hole etching barrier layer, remove the part that described contact hole etching barrier layer is not covered by described patterned photoresist;
Step S1043: remove described patterned photoresist.
Further, after described step S105, also comprise the steps:
Step S106: form interlayer dielectric layer in described Semiconductor substrate;
Step S107: remove the described contact hole etching barrier layer and the interlayer dielectric layer that are positioned at described dummy grid top by CMP technique;
Step S108: with the alternative described dummy grid of metal gates.
Wherein, in described step S106, the method that forms described interlayer dielectric layer is sedimentation.
Wherein, described step S 108 comprises:
Step S1081: etching is removed described dummy grid;
Step S1082: fill metal in the position that described dummy grid is original, remove unnecessary metal to form metal gates by CMP technique.
Wherein, after described step S108, also comprise: carry out dual damascene stage casing making technology to realize the step of local interconnect.
The manufacture method of the semiconductor device of the embodiment of the present invention, by forming contact hole etching barrier layer and the position of corresponding source electrode and drain electrode on contact hole etching barrier layer forms opening and carries out metallization process in dummy gate structure, improper restriction to space while having avoided available technology adopting silicide shielding layer (SAB) to carry out metallization process, thereby avoided pipe effect (piping issue), improve the yield of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The profile of the structure of formation after each step of the manufacture method of a kind of semiconductor device that Figure 1A-Fig. 1 H is the embodiment of the present invention completes;
Fig. 2 is the flow chart of the manufacture method of a kind of semiconductor device of embodiment of the present invention proposition.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device.For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations.Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.In the time that this uses, " one " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", in the time using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.In the time that this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
Here with reference to the cross-sectional view of the schematic diagram as desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, can expect due to for example manufacturing technology and/or tolerance cause from shown in the variation of shape.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to for example manufacturing the form variations causing.For example, the Qi edge, injection region that is shown as rectangle has round or bending features and/or implantation concentration gradient conventionally, rather than binary from injection region to non-injection regions changes.Equally, when the disposal area forming by injection can cause this disposal area and injection to be carried out some injections in the district between the surface of process.Therefore, the district showing in figure is in fact schematically, their shape be not intended display device district true form and be not intended to limit scope of the present invention.
Unless otherwise defined, all terms (comprising technology and scientific terminology) have the identical implication of conventionally understanding with the those of ordinary skill in field of the present invention as used herein.Also will understand, in dictionary such as common use, defined term should be understood to have the implication consistent with they implications in the environment of association area and/or these specifications, and can not explaining in desirable or excessively formal meaning, unless definition so expressly here.
In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, so that the manufacture method of the semiconductor device that explaination the present invention proposes.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The detailed step of an illustrative methods of the manufacture method of the semiconductor device that the present invention proposes is described with reference to Figure 1A-1H and Fig. 2 below.The profile of the structure of formation after each step of the manufacture method of a kind of semiconductor device that wherein, Figure 1A-Fig. 1 H is the embodiment of the present invention completes; Fig. 2 is the flow chart of the manufacture method of a kind of semiconductor device of embodiment of the present invention proposition.
The manufacture method of the semiconductor device that the embodiment of the present invention provides, comprises the method for utilizing dual damascene process to form local interconnect, specifically comprises the steps:
Step 1, provide semi-conductive substrate 100, in described Semiconductor substrate 100, be formed with dummy gate structure and source electrode, drain electrode.As shown in Figure 1A, wherein, dummy gate structure comprises dummy grid 101 and dummy grid sidewall 102 to the structure of this Semiconductor substrate 100.Those skilled in the art will appreciate that dummy gate structure can also comprise the retes such as high k dielectric layer, boundary layer.And, represent concise and to the point, in Figure 1A, only show a source electrode 103(because of the situation of drain electrode identical therewith, therefore concise and to the point in order to represent, and not shown).
Wherein, dummy grid 101 is generally polycrystalline silicon material.
The Semiconductor substrate 100(providing in this step comprises the parts such as the dummy gate structure on it), can make according to the various manufacture methods of this area, in this no limit.Wherein, described source electrode and drain electrode preferably adopt source electrode and the drain electrode structure of lifting, to improve device performance.
In the embodiment of the present invention, each schematic diagram (Figure 1A to Fig. 1 H) only shows a part for semiconductor device, and this part comprises a source electrode and two grids; Those skilled in the art will appreciate that in the semiconductor device of the embodiment of the present invention, can also comprise more MOS device (NMOS and/or PMOS etc.) and miscellaneous part, accompanying drawing is only used to signal, therefore do not form limitation of the invention.
As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to form.In described Semiconductor substrate, be formed with isolation structure, described isolation structure be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, Semiconductor substrate is divided into nmos area and PMOS district by described isolation structure.In described Semiconductor substrate, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure, by those skilled in the art are had the knack of, is described no longer in detail at this.
Step 2, to described Semiconductor substrate 100 carry out stress close on technology (SPT) process, by SPT processes removal some or all of dummy grid sidewall 102.
Preferably, when source electrode and drain electrode are during for the source electrode of lifting and drain electrode, remove the part away from Semiconductor substrate 100 of dummy grid sidewall 102 by SPT etching, retain dummy grid sidewall 102 in the part 102 ' between dummy grid 101 and source electrode 103 and between dummy grid 101 and drain electrode, the figure of formation as shown in Figure 1B.
Further preferred, the dummy grid sidewall 102 of reservation is identical at the height of the height of part 102 ' between dummy grid 101 and source electrode 103 and between dummy grid 101 and drain electrode and the source electrode of lifting 103 and drain electrode.
Wherein, preferred, the lithographic method that described SPT adopts is dry etching.
Step 3, in Semiconductor substrate 100, form one deck contact hole etching barrier layer (CESL) 104, as shown in Figure 1 C.
Wherein, contact hole etching barrier layer 104 covers whole Semiconductor substrate, comprises the part dummy grid sidewall 102 ' of dummy grid 101 and source electrode 103 and drain electrode (not shown), reservation, as shown in Figure 1 C.Forming the method on contact hole etching barrier layer 104, can be sedimentation, as chemical vapour deposition (CVD) etc.
Wherein, in this step, the contact hole etching barrier layer 104 of formation can adopt two stress liners or single stress liner to realize, and concrete material can be selected according to prior art.Adopt this scheme, not only can play the effect of etching barrier layer, and can improve by stress engineering the performance of semiconductor device.
Step 4, contact hole etching barrier layer (CESL) 104 is carried out to etching to form opening above source electrode 103 and drain electrode, as shown in Fig. 1 D.Wherein, in CESL, form be positioned at source electrode and drain electrode above opening, effect be to be convenient to the follow-up metallization process that carries out, to form metal silicide above source electrode and drain electrode.
Particularly, this technique can comprise the steps:
Step 401: form a patterned photoresist in the top of contact hole etching barrier layer (CESL) 104, described patterned photoresist covers the region of Semiconductor substrate 100 except source electrode 103 and drain electrode.
Step 402: contact hole etching barrier layer (CESL) 104 is carried out to etching take described patterned photoresist as mask, etch away the part that contact hole etching barrier layer (CESL) 104 is not covered by described patterned photoresist, on contact hole etching barrier layer (CESL) 104, the position of corresponding source electrode and drain electrode top forms opening.Wherein, the lithographic method adopting can be dry etching, can be wet etching, also can add wet etching etc. for dry etching, does not also limit at this.
Step 403: remove described patterned photoresist.Wherein, remove method that patterned photoresist can adopt and be that plasma is removed, wet method is peeled off etc.
Through abovementioned steps 401 to 403, the final figure forming is as described in Fig. 1 D.
In this step, while being formed for the opening of metallization process, do not adopt the method that forms silicide shielding layer (SAB) in prior art to realize, thereby can not cause unnecessary restriction to the space of the opening forming, the aperture efficiency of formation is larger, source electrode and drain electrode can come out completely, therefore,, in follow-up metallization process, can realize the abundant metallization of source electrode and drain electrode, avoid pipe effect (piping issue), improve the yield of device.
Step 5, described Semiconductor substrate 100 is carried out to metallization process, in source electrode 103 and drain electrode, form metal silicide 105, the figure of formation is as shown in Fig. 1 E.
Wherein, metal silicide 105 is generally nickle silicide (NiSi).Realize the method for metallization process, can adopt any feasible pattern of the prior art to realize, in this no limit.
While metallization in this step, due in step 4, form to be positioned at the opening for metallization process on contact hole etching barrier layer 104 larger, source electrode and drain electrode can come out completely, therefore, can make fully metallization (upper surface that is source electrode and drain electrode is metallized completely) of source electrode and drain electrode, avoid pipe effect (piping issue), improved the yield of semiconductor device.And in the prior art, because SAB can occupy certain open space, can cause source electrode and drain electrode fully to metallize, particularly, metallization cannot be realized in the unexposed region of the upper surface of source electrode and drain electrode.
Step 6, in Semiconductor substrate 100, form one deck interlayer dielectric layer (ILD) 106, as shown in Fig. 1 F.
Wherein, interlayer dielectric layer 106 covers whole Semiconductor substrate 100 completely.The method that forms interlayer dielectric layer 106, can adopt sedimentation or other suitable methods, in this no limit.
Step 7, Semiconductor substrate 100 is carried out to CMP(chemico-mechanical polishing) process, remove the contact hole etching barrier layer 104 and the interlayer dielectric layer 106 that are positioned at described dummy grid 101 tops, expose dummy grid 101, the figure of formation is as shown in Figure 1 G.
Step 8, use metal gates 101 ' substitute dummy grid 101,, form metal gates 101 ' in the position of dummy grid 101 that is, and the figure of formation is as shown in Fig. 1 H.
Exemplarily, this step can realize in the following way:
Step 801: remove dummy grid 101 by etching technics.Wherein, the etching technics adopting can be wet etching etc.
Step 802: fill metal in the original position of dummy grid 101 and remove unnecessary metal to form metal gates 101 ' by CMP.
In the manufacture method of the semiconductor device of the embodiment of the present invention, complete above-mentioned steps 1 to step 8, can carry out dual damascene stage casing making technology, to realize local interconnect.This dual damascene stage casing making technology, can adopt scheme feasible in any prior art to realize, and does not repeat them here.The structure realizing through abovementioned steps 1 to step 8, with respect to prior art, the metallization of source electrode and drain electrode is more abundant, therefore has enough attaching spaces, therefore can realize better dual damascene stage casing making technology.
So far, completed the introduction of the manufacture method of the exemplary semiconductor device of the embodiment of the present invention.Those skilled in the art will appreciate that the method for the embodiment of the present invention is not as limit; And, although other steps in the irrelevant semiconductor device processing procedure of the embodiment of the present invention pair and inventive point are not described, but this does not represent that the embodiment of the present invention does not comprise these steps, but due to these processing steps and traditional identical the repeating no more of process for fabricating semiconductor device.
The manufacture method of the semiconductor device of the embodiment of the present invention, by forming contact hole etching barrier layer and the position of corresponding source electrode and drain electrode on contact hole etching barrier layer forms opening and carries out metallization process in dummy gate structure, improper restriction to space while having avoided available technology adopting silicide shielding layer (SAB) to carry out metallization process, thereby avoided pipe effect (piping issue), improve the yield of semiconductor device.
With reference to Fig. 2, wherein show the flow chart of a kind of typical method in the manufacture method of semiconductor device that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.The method specifically comprises:
Step S101: Semiconductor substrate is provided, is formed with source electrode, drain electrode, dummy grid and dummy grid sidewall in described Semiconductor substrate;
Step S102: described Semiconductor substrate is carried out to stress and close on technical finesse, remove some or all of dummy grid sidewall;
Step S103: form contact hole etching barrier layer in described Semiconductor substrate;
Step S104: described in etching, contact hole etching barrier layer to form opening above described source electrode and drain electrode;
Step S105: described Semiconductor substrate is metallized to form metal silicide in described source electrode and drain electrode.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (11)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S101: Semiconductor substrate is provided, is formed with source electrode, drain electrode, dummy grid and dummy grid sidewall in described Semiconductor substrate;
Step S102: described Semiconductor substrate is carried out to stress and close on technical finesse, remove the described dummy grid sidewall of part;
Step S103: form contact hole etching barrier layer in described Semiconductor substrate;
Step S104: described in etching, contact hole etching barrier layer to form opening above described source electrode and drain electrode;
Step S105: described Semiconductor substrate is metallized to form metal silicide in described source electrode and drain electrode.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, source electrode and drain electrode that described source electrode and drain electrode are lifting.
3. the manufacture method of semiconductor device as claimed in claim 2, it is characterized in that, in described step S102, remove the part of described dummy grid sidewall away from described Semiconductor substrate, retain described dummy grid sidewall in the part between described dummy grid and described source electrode and between described dummy grid and described drain electrode.
4. the manufacture method of semiconductor device as claimed in claim 3, it is characterized in that, the described dummy grid sidewall of reservation is identical at the height of the height of part between described dummy grid and described source electrode and between described dummy grid and described drain electrode and the source electrode of described lifting and drain electrode.
5. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S102, carrying out stress while closing on technical finesse, adopts dry etching.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the described contact hole etching barrier layer forming in described step S103 is two stress liners or single stress liner.
7. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described step S104 comprises:
Step S1041: form patterned photoresist above described contact hole etching barrier layer, described patterned photoresist covers the region of described Semiconductor substrate except described source electrode and drain electrode;
Step S1042: take described patterned photoresist as mask, etching is carried out in described contact hole etching barrier layer, remove the part that described contact hole etching barrier layer is not covered by described patterned photoresist;
Step S1043: remove described patterned photoresist.
8. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, after described step S105, also comprises the steps:
Step S106: form interlayer dielectric layer in described Semiconductor substrate;
Step S107: remove the described contact hole etching barrier layer and the interlayer dielectric layer that are positioned at described dummy grid top by CMP technique;
Step S108: with the alternative described dummy grid of metal gates.
9. the manufacture method of semiconductor device as claimed in claim 8, is characterized in that, in described step S106, the method that forms described interlayer dielectric layer is sedimentation.
10. the manufacture method of semiconductor device as claimed in claim 8, is characterized in that, described step S108 comprises:
Step S1081: etching is removed described dummy grid;
Step S 1082: fill metal in the position that described dummy grid is original, remove unnecessary metal to form metal gates by CMP technique.
The manufacture method of 11. semiconductor device as claimed in claim 8, is characterized in that, after described step S 108, also comprises: carry out dual damascene stage casing making technology to realize the step of local interconnect.
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| CN111128734A (en) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Method of manufacturing semiconductor device and semiconductor device |
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| US20090289309A1 (en) * | 2008-05-21 | 2009-11-26 | Chartered Semiconductor Manufacturing, Ltd. | Method for reducing silicide defects in integrated circuits |
| CN102376686A (en) * | 2010-08-11 | 2012-03-14 | 中国科学院微电子研究所 | Semiconductor device and production method thereof |
| CN102569073A (en) * | 2010-12-07 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
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| US20090289309A1 (en) * | 2008-05-21 | 2009-11-26 | Chartered Semiconductor Manufacturing, Ltd. | Method for reducing silicide defects in integrated circuits |
| CN102376686A (en) * | 2010-08-11 | 2012-03-14 | 中国科学院微电子研究所 | Semiconductor device and production method thereof |
| CN102569073A (en) * | 2010-12-07 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111128734A (en) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Method of manufacturing semiconductor device and semiconductor device |
| US11764289B2 (en) | 2018-10-31 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
| CN111128734B (en) * | 2018-10-31 | 2023-12-19 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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