CN103754817A - Three-dimensional vertical-interconnection silicon-based light and electricity simultaneous transmission device and manufacturing method thereof - Google Patents
Three-dimensional vertical-interconnection silicon-based light and electricity simultaneous transmission device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a three-dimensional vertical-interconnection silicon-based light and electricity simultaneous transmission device and a manufacturing method of the three-dimensional vertical-interconnection silicon-based light and electricity simultaneous transmission device. The light and electricity simultaneous transmission device comprises a silicon substrate. The silicon substrate is provided with a copper layer, a horizontal waveguide layer and an upper wrapping layer and is further provided with vertical silicon through holes and a vertical light through hole, wherein the copper layer is provided with a wiring pattern, the horizontal waveguide layer is provided with light and electricity interconnection holes and an inverted-triangle-shaped reflector, the upper wrapping layer is provided with openings communicated with the light and electricity interconnection holes, and the light and electricity interconnection holes and the openings are electroplated with interconnection metal. The manufacturing method includes the steps of photoetching of the vertical light through hole and the vertical silicon through holes, manufacturing of a dielectric layer, manufacturing of a vertical waveguide core layer and the horizontal waveguide layer, forming of a metal RDL layer and the like. By means of the method, simultaneous manufacturing of the horizontal waveguide layer and a vertical light waveguide layer can be completed on the silicon substrate, and horizontal and vertical light interconnection of light waveguides, horizontal and vertical electricity interconnection and light and electricity mutual conduction are achieved; the manufacturing process is simple, and cost is low.
Description
Technical field
The present invention relates to integrated electronic technical field, particularly a kind of three-dimensional photoelectricity simultaneous interpretation device and preparation method thereof.
Background technology
Existing integrated circuit mostly is two-dimentional integrated circuit, and two station integrated circuits refer to by the distribution side by side of the various components and parts of integrated circuit in one plane.Along with integrated level improves constantly, the device cell quantity on every sharply increases, and chip area increases, and between unit, the growth of line not only affects circuit working speed but also takies a lot of areas, has a strong impact on integrated circuit and further improves integrated level and operating rate.So produce three-dimensional integrated new technology thinking.Three dimensional integrated circuits multilayer device overlay structure can significantly improve chip integration, and overlay structure shortens unit line, and makes parallel signal be treated as possibility, thereby realizes the high speed operation of circuit, has plurality of advantages; But due to the design of multilayer circuit, there is more complicated electrical interconnection conduction, will inevitably be at the technical barrier that occurs being difficult to overcome aspect limit bandwidth, electromagnetic interference, delay, energy consumption, make the processing speed that the growth rate of input information output cannot match information.Light interconnection technique has great bandwidth resources and the information that can realize is easily intersected and multiplexing advantage, can make single transmission channel realize the transmission of mass data, and independent of one another between different channels optical signal, there will not be and intersect and crosstalk phenomenon, be therefore the desirable technique that substitutes electrical interconnection.The current application in light interconnection technique, mostly the research of passing through horizon light waveguide and realize the two dimension interconnection of optical signalling and the photoelectricity perpendicular interconnection by vertical light waveguide and the integrated manufacture of TSV being embodied in based on silica-based interposer, and for the research of the fiber waveguide manufacture method of vertical light waveguide and the integrated manufacture of horizon light waveguide and transmission and use and interposer process compatible also in blank.
In addition, even if adopt light interconnection technique, because the surface of wiring board needs welding electronic component, therefore wiring board also needs to consider the factor of optical signal switching electrical signals and signal of telecommunication transmitting photo-signal in design process.For the mutual teach skill art of photoelectricity, in the integrated middle application of three-dimensional, be only to separate integrated mode based on light interposer and electric interposer at present, cannot realize the real fusion that three-dimensional integrated middle photoelectricity passes mutually.
Summary of the invention
The technical problem that the present invention solves be to provide a kind of three-dimensional integrated in photoelectricity based on silica-based interposer pass mutually device and preparation method thereof, to realize between the horizon light interconnection of fiber waveguide and the electrical interconnection of perpendicular interconnection, vertical direction and horizontal direction and photoelectricity the object of conduction mutually in same packaging body.
For solving the problems of the technologies described above, the technical solution used in the present invention is as follows.
Three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device, comprises silicon substrate, is disposed with insulating barrier, dielectric layer, copper layer, horizontal wave conducting shell and top covering on described silicon substrate; On described silicon substrate, be vertically installed with the vertical silicon through hole and the vertical light through hole that are communicated with copper layer, on copper layer between described adjacent vertical silicon through hole, be laid with the wiring pattern being communicated with horizontal wave conducting shell, sandwich layer and horizontal wave conducting shell in described vertical light through hole are connected as a single entity, on described horizontal wave conducting shell, be provided with and the photovoltaic interconnects hole of wiring pattern dislocation layout and the del speculum of corresponding vertical light through hole lateral wall, on described top covering, be provided with the opening being communicated with photovoltaic interconnects hole; Described photovoltaic interconnects hole and opening are electroplate with interconnecting metal.
The preparation method of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device, mainly comprises the following steps: first on silicon substrate, by photoetching, etching or sputtering technology, manufacture vertical light through hole and vertical silicon through hole; Secondly copper steam-plating layer above silicon substrate; Then adopt the PI material of light sensitivity by whirl coating and exposure technology, to complete the making of vertical light through hole sandwich layer and horizontal wave conducting shell; The last interconnection that forms metal RDL layer above horizontal wave conducting shell.
Three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device manufacture method specifically comprises the following steps:
The first step, in the some blind holes perpendicular to silicon substrate of the positive etching of silicon substrate, blind hole comprises vertical silicon through hole and the vertical light through hole of finished product;
Second step, depositing insulating layer on silicon substrate and blind hole sidewall;
The 3rd step, coating dry film is as photoresist, and the dry film place above the blind hole of corresponding vertical light through hole carries out photoetching and forms through hole;
The 4th step after dry film photoetching development, is filled outsourcing layer in exposed vertical light through hole;
The 5th step, peels off dry film, removes outsourcing layer residual on dry film simultaneously;
The 6th step, adopts PVD deposition techniques dielectric layer;
The 7th step, fills to electro-coppering in vertical silicon through hole, and annealing;
The 8th step, evaporation one deck underlying metal, then on underlying metal, sputter copper forms copper layer;
The 9th step, mask, photoetching, etching front copper layer above the silicon substrate between adjacent vertical silicon through hole, form wiring pattern; And etching is positioned at the copper layer of vertical light through hole top;
The tenth step, the outsourcing layer in etching vertical light through hole, forms a ring shape surrounding layer, and the thickness of annular surrounding layer is at 3 ~ 10 μ m;
The 11 step is filled waveguide material in wiring pattern and vertical light through hole, and fills waveguide material formation horizontal wave conducting shell at copper layer upper surface;
The 12 step, forms horizontal waveguide, photovoltaic interconnects hole in horizontal wave conducting shell etching, and on the horizontal wave conducting shell above corresponding vertical light through hole lateral wall etching del speculum;
The 13 step, to the electro-coppering of photovoltaic interconnects hole;
The 14 step, above horizontal wave conducting shell, the photosensitive PI material of spin coating is made top covering, and photoetching, development on top covering, solidifies and offer opening;
The 15 step, forms UBM to electro-coppering in the opening of top covering;
The 16 step, the attenuate silicon substrate back side;
The 17 step, repeats the first step to the 15 steps at the silicon substrate back side, complete the waveguide of bottom or the making at distribution layer.
The improvement of preparation method the 6th step is: described dielectric layer comprises the diffusion impervious layer, adhesion layer and the Seed Layer that from insulating barrier, upwards set gradually, the preferred TiN/Ti/Cu combination of diffusion impervious layer, adhesion layer and Seed Layer, and thickness is got 200nm/200nm/1000nm.
The improvement of preparation method the tenth step is: described in the tenth step, etching is selected dry etching or laser ablation.
The improvement of preparation method the 12 step: del speculum described in the 12 step obtains the del waveguide shapes needing, the equilateral triangle that is shaped as handstand of del speculum by exposure, development, post bake.
Owing to having adopted above technical scheme, the invention technological progress is as follows.
The present invention manufactures when can complete horizon light waveguide and vertical light waveguide in silica-based interposer, in same packaging body, realized the object of mutually conducting between the horizon light interconnection of fiber waveguide and the electrical interconnection of perpendicular interconnection, vertical direction and horizontal direction and photoelectricity, manufacture craft is simple, with low cost.
The photoelectricity simultaneous interpretation device that adopts the present invention to make, have the following advantages: one, reduced encapsulation level, a large amount of can only be with sheet under traditional integration mode between the logic interconnection realized of communication mode can become in sheet and interconnect, significantly reduction pin size, improves integrated level; Its two, the integrated permission of three-dimensional photoelectricity is carried out space wiring in three-dimensional mode to circuit, light path module, thereby significantly shortens wire length on sheet, improves transmission speed and reduces power consumption; Its three, three-dimensional photoelectricity is integrated by the technology being realized by non-CMOS at first with integrate based on CMOS technology, allows the chip of different process integrated in natural mode, forms accurate SOC system.Therefore photoelectron three-dimensional is integrated, active, passive and photon, electronic chip are directly integrated in photoelectricity hybrid system, can realize the perpendicular interconnection of the signal of telecommunication and optical signal simultaneously, can make the 3D electronic integrated circuit and the photonic interconnections that mutually combine display one's respective advantages, realize integrated system and on-chip integration system between the sheet of high density, high-performance, low-power consumption, for the demand that solves multiple IO interconnection, pin miniaturization, high-speed interconnect, new application has been carried for more superior In System Integration Solutions.
Accompanying drawing explanation
Fig. 1 is the structural representation of photoelectricity simultaneous interpretation device of the present invention.
Fig. 2 is the process chart that the present invention makes photoelectricity simultaneous interpretation device.
Wherein: 1. silicon substrate, 2. insulating barrier, 3. dielectric layer, 4. copper layer, 5. horizontal wave conducting shell, 6. top covering, 7. vertical silicon through hole, 8. annular surrounding layer, 9. vertical light through hole, 10. wiring pattern, 11. photovoltaic interconnects holes, 12. openings, 13. speculums, 14. dry films.
The specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further elaborated.
A kind of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device, its structure as shown in Figure 1, comprises silicon substrate 1, is disposed with insulating barrier 2, dielectric layer 3, copper layer 4, horizontal wave conducting shell 5 and top covering 6 on described silicon substrate 1; On described silicon substrate 1, be vertically installed with the vertical silicon through hole 7 and the vertical light through hole 9 that are communicated with copper layer 4, on copper layer between described adjacent vertical silicon through hole, be laid with the wiring pattern 10 being communicated with horizontal wave conducting shell 5, sandwich layer and horizontal wave conducting shell in described vertical light through hole are connected as a single entity, on described horizontal wave conducting shell 5, be provided with and the photovoltaic interconnects hole 11 of wiring pattern dislocation layout and the del speculum 13 of corresponding vertical light through hole 9 lateral walls, on described top covering, be provided with the opening 12 being communicated with photovoltaic interconnects hole 11; Described photovoltaic interconnects hole 11 and opening 12 are electroplate with metal.
The preparation method of above-mentioned three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device, is mainly included in the step of making vertical silicon through hole, vertical light through hole, copper steam-plating layer, spin coating horizontal wave conducting shell, making photovoltaic interconnects hole and speculum, making top covering on silicon substrate.First on silicon substrate, by techniques such as photoetching, etching or sputters, manufacture vertical light through hole and vertical silicon through-hole structure, vertical light through hole, after making vertical silicon through hole, adopts the PI material of light sensitivity by whirl coating and exposure technology one step, to complete the making moulding of vertical waveguide sandwich layer and horizontal wave conducting shell; The follow-up interconnection that forms successively metal RDL layer.
Because silica-based interposer exists two-sided interconnection process, the present invention only sets forth for one side technique, and the technique of another side has identical structure and preparation method, repeats no more.One side process chart as shown in Figure 2, specifically comprises the following steps:
The first step forms some blind holes perpendicular to silicon substrate by chemical etching on silicon substrate 1, and blind hole comprises vertical silicon through hole 7 and the vertical light through hole 9 of finished product.
The aperture of blind hole is relevant with the thickness of silicon substrate.Generally, the aperture depth-to-width ratio of vertical silicon via etch is 10:1 or 5:1, and the diameter of vertical light through hole and vertical silicon through-hole diameter can be different, depends on the optical mode design of light through hole transmission.Take the aperture depth-to-width ratio 5:1 of the thick silica-based interposer of 150 μ m, vertical silicon through hole as example, the pore size of vertical silicon through hole is 30 μ m.
Be arranged side by side in the present embodiment four blind holes, wherein three, the left side is vertical silicon through hole, and the rightmost side is vertical light through hole.The etching of blind hole can adopt dry etching, such as DRIE etc.Silicon substrate can be low-resistance silicon, High Resistivity Si or SOI material.
Second step, is used the positive silicate of tetraethyl (TEOS) or thermal oxide depositing insulating layer 2, and the thickness of insulating layer of silicon substrate upper surface is 1 μ m, and the thickness of insulating layer of blind hole hole wall is a hundreds of nm.The isolation that insulating barrier sinks to the bottom for realizing signal and silicon substrate, guarantees good electricity transmission characteristic.Certainly, also can use thermal oxide to form the insulating barrier of hole wall and silicon substrate upper surface.TEOS is a kind of low temperature process, preferably TEOS technique.
The 3rd step, coating dry film 14 is as photoresist, and the dry film place above the blind hole of corresponding vertical light through hole carries out photoetching and forms through hole.Dry film is a kind of photosensitive PI material, as interim mask.The thickness of dry film can be divided into four classes: 0.8mil, 1.2mil, 1.5mil, 2.0mil, and dry film is thinner, and the circuit of making is meticulousr.
In the present embodiment, on dry film corresponding to the rightmost side of silicon substrate blind hole, make the through hole corresponding with vertical light through hole by lithography.
The 4th step, dry film photoetching (uv-exposure) is filled outsourcing layer after developing in exposed vertical light through hole, and after filling, toasting and making outsourcing layer curing molding, baking temperature is 50 ~ 80 °.The preferred PMMA material of outsourcing layer, the method for filling can be spin coating or spraying.
The 5th step, peels off dry film, removes outsourcing layer residual on dry film simultaneously, then the vertical light through hole at outsourcing layer place is polished.
The 6th step, adopts PVD deposition techniques dielectric layer 3.Dielectric layer comprises the diffusion impervious layer, adhesion layer and the Seed Layer that from insulating barrier, upwards set gradually, the preferred TiN/Ti/Cu combination of diffusion impervious layer, adhesion layer and Seed Layer, and thickness is got 200nm/200nm/1000nm.
The 7th step, fills to electro-coppering in vertical silicon through hole, and annealing.Optimization of Copper bath element proportioning, optimizes Current Control waveform, realizes the excellent filling of high-aspect-ratio, controls overburden below 3 μ m.
Use the method for chemically mechanical polishing (CMP) or etching to remove surperficial excess metal layer, remove surperficial copper and dielectric layer.Preferably CMP technique, because the cost of copper etching is higher than CMP.
The 8th step, is used PVD technology evaporation one deck underlying metal, such as TiW, and a thickness hundreds of nm; Then on underlying metal, sputter copper forms copper layer 4, and copper layer thickness is several microns, also can adopt electro-coppering.
The 9th step, mask, photoetching, etching front copper layer 4 above the silicon substrate between adjacent vertical silicon through hole, form wiring pattern 10, uses subtractive process, retains wiring, removes unnecessary metal; And etching is positioned at the copper layer of vertical light through hole top.Preferred wet etching in this step.
The tenth step, the outsourcing layer in etching vertical light through hole, forms a ring shape surrounding layer 8, and the thickness of annular surrounding layer is at 3 ~ 10 μ m.Can use laser or dry method to carry out the etching of surrounding layer, preferably dry etching, can make the sidewall of etching Paint Gloss, improves fiber waveguide performance, reduces loss.
The 11 step is filled waveguide material in wiring pattern 10 and vertical light through hole 9, and at copper layer 4 upper surface, fills waveguide materials and form horizontal wave conducting shells 5, the thickness of horizontal wave conducting shell at several microns to tens microns.Horizontal wave conducting shell 5 is connected as a single entity with the waveguide material in wiring pattern 10 and vertical light through hole 9, and the method for filling can be spin coating or spraying.The preferred BCB material of waveguide material.
The 12 step, forms horizontal waveguide, photovoltaic interconnects hole 11 in horizontal wave conducting shell 5 etchings, and on the horizontal wave conducting shell 5 above corresponding vertical light through hole 9 lateral walls etching del speculum 13.Adopt light-sensitive material, by exposure, development, post bake, can obtain del speculum 13 waveguide shapes of needs, the equilateral triangle that the shape of del speculum is preferably stood upside down.
Del waveguide shapes also can be used laser cutting to form, and waveguide also can form by the mode of impression.
The 13 step, to 11 electro-copperings of photovoltaic interconnects hole, realizes the parallel link of electricity, and copper improves reflectivity as the reflecting surface of speculum 13.Adopt photoetching, etch process to make the RDL of the second layer.
The 14 step, above horizontal wave conducting shell 5, the photosensitive PI material of spin coating is made top covering 6, realizes surperficial passivation; And photoetching, development on top covering 6, solidify and offer opening 12, minimal openings is 10 μ m.Photosensitive PI material category is a lot, and refractive index ratio BCB is low.
The 15 step, forms UBM to electro-coppering in the opening 12 of top covering 6, and UBM thickness is at several microns.
The 16 step, the attenuate silicon substrate back side, to expose vertical silicon through hole and vertical light through hole is advisable.
The 17 step, repeats the first step to the 15 steps at the silicon substrate back side, complete the waveguide of bottom or the making at distribution layer.
Claims (6)
1. three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device, comprises silicon substrate (1), it is characterized in that: on described silicon substrate (1), be disposed with insulating barrier (2), dielectric layer (3), copper layer (4), horizontal wave conducting shell (5) and top covering (6), on described silicon substrate (1), be vertically installed with the vertical silicon through hole (7) and the vertical light through hole (9) that are communicated with copper layer (4), on copper layer between described adjacent vertical silicon through hole, be laid with the wiring pattern (10) being communicated with horizontal wave conducting shell (5), sandwich layer and horizontal wave conducting shell in described vertical light through hole are connected as a single entity, on described horizontal wave conducting shell (5), be provided with and the photovoltaic interconnects hole (11) of wiring pattern dislocation layout and the del speculum (13) of corresponding vertical light through hole (9) lateral wall, on described top covering, be provided with the opening (12) being communicated with photovoltaic interconnects hole (11), described photovoltaic interconnects hole (11) and opening (12) are electroplate with interconnecting metal.
2. the preparation method of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device, is characterized in that mainly comprising the following steps: first on silicon substrate, by photoetching, etching or sputtering technology, manufacture vertical light through hole and vertical silicon through hole; Secondly copper steam-plating layer above silicon substrate; Then adopt the PI material of light sensitivity by whirl coating and exposure technology, to complete the making of vertical light through hole sandwich layer and horizontal wave conducting shell; The last interconnection that forms metal RDL layer above horizontal wave conducting shell.
3. the preparation method of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device according to claim 2, is characterized in that specifically comprising the following steps:
The first step, in the some blind holes perpendicular to silicon substrate of the positive etching of silicon substrate (1), blind hole comprises vertical silicon through hole (7) and the vertical light through hole (9) of finished product;
Second step, depositing insulating layer (2) on silicon substrate (1) and blind hole sidewall;
The 3rd step, coating dry film (14) is as photoresist, and the dry film place above the blind hole of corresponding vertical light through hole carries out photoetching and forms through hole;
The 4th step after dry film photoetching development, is filled outsourcing layer in exposed vertical light through hole;
The 5th step, peels off dry film, removes outsourcing layer residual on dry film simultaneously;
The 6th step, adopts PVD deposition techniques dielectric layer (3);
The 7th step, fills to electro-coppering in vertical silicon through hole, and annealing;
The 8th step, evaporation one deck underlying metal, then on underlying metal, sputter copper forms copper layer (4);
The 9th step, mask, photoetching, etching front copper layer (4) above the silicon substrate between adjacent vertical silicon through hole, form wiring pattern (10); And etching is positioned at the copper layer of vertical light through hole top;
The tenth step, the outsourcing layer in etching vertical light through hole, forms a ring shape surrounding layer (8), and the thickness of annular surrounding layer is at 3 ~ 10 μ m;
The 11 step is filled waveguide material, and is filled waveguide material formation horizontal wave conducting shell (5) at copper layer (4) upper surface in wiring pattern (10) and vertical light through hole (9);
The 12 step, forms horizontal waveguide, photovoltaic interconnects hole (11) in horizontal wave conducting shell (5) etching, and the upper etching del speculum (13) of the horizontal wave conducting shell (5) in corresponding vertical light through hole (9) lateral wall top;
The 13 step, to photovoltaic interconnects hole (11) electro-coppering;
The 14 step, makes top covering (6) at the photosensitive PI material of horizontal wave conducting shell (5) top spin coating, and goes up photoetching, development, solidifies and offer opening (12) at top covering (6);
The 15 step, forms UBM to the middle electro-coppering of opening (12) of top covering (6);
The 16 step, the attenuate silicon substrate back side;
The 17 step, repeats the first step to the 15 steps at the silicon substrate back side, complete the waveguide of bottom or the making at distribution layer.
4. the preparation method of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device according to claim 3, it is characterized in that: described in the 6th step, dielectric layer comprises the diffusion impervious layer, adhesion layer and the Seed Layer that from insulating barrier, upwards set gradually, the preferred TiN/Ti/Cu combination of diffusion impervious layer, adhesion layer and Seed Layer, thickness is got 200nm/200nm/1000nm.
5. the preparation method of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device according to claim 3, is characterized in that: described in the tenth step, etching is selected dry etching or laser ablation.
6. the preparation method of three-dimensional perpendicular interconnection silicon based opto-electronics simultaneous interpretation device according to claim 3, it is characterized in that: del speculum (13) described in the 12 step obtains the del waveguide shapes of needs by exposure, development, post bake the equilateral triangle that is shaped as handstand of del speculum.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104101967A (en) * | 2014-07-31 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Photo-communication device and forming method of stop hole |
| CN110687630A (en) * | 2019-09-30 | 2020-01-14 | 华中科技大学 | SOI substrate applied to three-dimensional optical interconnection and preparation method thereof |
| CN111538119A (en) * | 2020-04-21 | 2020-08-14 | 东南大学 | Preparation method of three-dimensional photoelectric interconnection substrate |
| CN113517362A (en) * | 2021-07-08 | 2021-10-19 | 曲靖师范学院 | Integrated photosensitive transistor |
| CN114784473A (en) * | 2022-03-16 | 2022-07-22 | 上海交通大学 | Dual-folded substrate integrated waveguide filtering balun based on silicon-based photosensitive film |
| US20230358956A1 (en) * | 2020-01-31 | 2023-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package, optical device, and manufacturing method of package |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001074955A (en) * | 1999-08-31 | 2001-03-23 | Susumu Noda | Photonic crystal waveguide |
| US20040114856A1 (en) * | 2001-11-08 | 2004-06-17 | Xerox Corporation | Monolithic reconfigurable optical multiplexer systems and methods |
| CN1956284A (en) * | 2005-10-29 | 2007-05-02 | 深圳飞通光电子技术有限公司 | Ridge waveguide type semiconductor laser and its manufacturing method |
| CN102495445A (en) * | 2011-12-15 | 2012-06-13 | 中国科学院微电子研究所 | Optical vertical interconnection structure and interconnection method thereof |
| CN103474739A (en) * | 2013-09-26 | 2013-12-25 | 中国工程物理研究院电子工程研究所 | Micro-machine manufacturing method for rectangular waveguide transmission device |
-
2014
- 2014-01-28 CN CN201410042670.XA patent/CN103754817B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001074955A (en) * | 1999-08-31 | 2001-03-23 | Susumu Noda | Photonic crystal waveguide |
| US20040114856A1 (en) * | 2001-11-08 | 2004-06-17 | Xerox Corporation | Monolithic reconfigurable optical multiplexer systems and methods |
| CN1956284A (en) * | 2005-10-29 | 2007-05-02 | 深圳飞通光电子技术有限公司 | Ridge waveguide type semiconductor laser and its manufacturing method |
| CN102495445A (en) * | 2011-12-15 | 2012-06-13 | 中国科学院微电子研究所 | Optical vertical interconnection structure and interconnection method thereof |
| CN103474739A (en) * | 2013-09-26 | 2013-12-25 | 中国工程物理研究院电子工程研究所 | Micro-machine manufacturing method for rectangular waveguide transmission device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104101967A (en) * | 2014-07-31 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Photo-communication device and forming method of stop hole |
| CN104101967B (en) * | 2014-07-31 | 2016-02-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of formation method of optical communication apparatus and stop hole |
| CN110687630A (en) * | 2019-09-30 | 2020-01-14 | 华中科技大学 | SOI substrate applied to three-dimensional optical interconnection and preparation method thereof |
| US20230358956A1 (en) * | 2020-01-31 | 2023-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package, optical device, and manufacturing method of package |
| CN111538119A (en) * | 2020-04-21 | 2020-08-14 | 东南大学 | Preparation method of three-dimensional photoelectric interconnection substrate |
| CN113517362A (en) * | 2021-07-08 | 2021-10-19 | 曲靖师范学院 | Integrated photosensitive transistor |
| CN114784473A (en) * | 2022-03-16 | 2022-07-22 | 上海交通大学 | Dual-folded substrate integrated waveguide filtering balun based on silicon-based photosensitive film |
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