CN103744698A - Method and system for DSP project efficient running - Google Patents
Method and system for DSP project efficient running Download PDFInfo
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- CN103744698A CN103744698A CN201310737272.5A CN201310737272A CN103744698A CN 103744698 A CN103744698 A CN 103744698A CN 201310737272 A CN201310737272 A CN 201310737272A CN 103744698 A CN103744698 A CN 103744698A
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Abstract
The invention discloses a method and system for DSP project efficient running and relates to the technical field of DSP project. By dividing a to-be-run project into two parts and respectively loading the two parts to an SRAM and an SDRAM, possibility is provided for loading of a large data volume and a large project; by setting two-stage caching, and not only can the large project be loaded, but also large project treatment efficiency can be kept as the same as small project treatment efficiency. Developers can add programs and bulk data on a hardware platform almost without limitation, an extra-chip theoretical expanding space can reach a GB level, and deceleration of project treatment efficiency of a DSP chip caused by program and data adding in a DSP project is avoided.
Description
Technical field
The present invention relates to DSP field of engineering technology, particularly a kind of efficient operation method and system of DSP engineering.
Background technology
Dsp chip, also claims digital signal processor, is a kind of microprocessor that is particularly suitable for carrying out digital signal processing computing, and it is mainly applied is to realize real-time various digital signal processing algorithms.According to the requirement of digital signal processing, dsp chip generally has the following principal character: within an instruction cycle, can complete multiplication and a sub-addition; Program and data space separates, simultaneously access instruction and data; There is low expense or without circulation and the redirect hardware supported of expense; There are a plurality of hardware address generators that operate within the monocycle; Can a plurality of operations of executed in parallel; Support stream line operation, fetching, decoding and execution etc. are operated can executed in parallel.
Existing DSP development procedure, conventionally be all first to make PCB development board, then the combined testing action group of exploitation plate (Joint Test Action Group, JTAG) interface, downloads compiled engineering with emulator and carries out real-time debugging and operation.Revise again software, then debug, until reach expection, require.Conventionally the connected mode of computing machine and DSP development board as shown in Figure 1, main flow have jtag interface mode, periphery component interconnection (Peripheral Component Interconnect, a PCI) interface mode, the two selects one.Use the shortcoming of jtag interface to have: 1, connect jtag interface and need emulator, emulator price is comparatively expensive, and as easy as rolling off a log damage, keeps in repair loaded down with trivial details.2, with JTAG emulator, download code, professional software need to be installed in advance, need to have certain DSP exploitation basis.3, in the time of will loading a plurality of engineering, easily maloperation.
For avoiding the shortcoming of jtag interface, so use sometimes general pci interface, the method being communicated with DSP development board as computing machine (PC).The advantage of the method: 1, do not need to use emulator, cost saving, convenient and swift.2, all operations were running background, client is invisible, does not need client to have DSP exploitation basis.The user interface of 3, providing convenience (UI), allows the selection that user can intuitive and convenient load a certain engineering.But use the method also to have drawback: if 1 engineering is excessive, dsp chip internal storage space is inadequate, can not load whole engineering completely; If 2 are carried in engineering in the chip external memory (being SDRAM) of DSP, dsp chip can not high speed real time execution program, causes dsp chip very low to the treatment effeciency of engineering.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: how, in the situation that guaranteeing dsp chip storage space, improve the treatment effeciency of dsp chip to engineering.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of efficient operation method of DSP engineering, said method comprising the steps of:
S1: the data segment in engineering to be moved is split into two parts, and a part is as engineering in sheet, another part data segment and described in program segment in engineering to be moved as the outer engineering of sheet;
S2: described interior engineering is loaded in the common SRAM of DSP development board, described outer engineering is loaded in the SDRAM of described DSP development board;
S3: divide the storage space of preset length as level 2 cache memory in common SRAM;
S4: the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read.
Wherein, in step S1, according to data type and read and write indegree the data segment in engineering described to be moved is split into two parts.
Wherein, step S2 comprises:
S201: described interior engineering is loaded in the common SRAM of described DSP development board by pci interface;
S202: by the DSP core operation suspension of described DSP development board, and open the external memory interface of described DSP development board;
S203: described outer engineering is loaded in the SDRAM of described DSP development board by described pci interface and external memory interface;
S204: the DSP core of described DSP development board is restarted to operation.
Wherein, in step S4, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and read and comprise:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
Wherein, in step S4, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and write and comprise:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory, described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, described level 2 cache memory is written back to the data to be written after write operation in described SDRAM; If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
The invention also discloses a kind of high-efficiency operation system of DSP engineering, described system comprises:
Engineering splits module, and for the data segment of engineering to be moved is split into two parts, a part is as engineering in sheet, another part data segment and described in program segment in engineering to be moved as the outer engineering of sheet;
Engineering load-on module, for described interior engineering being loaded on to the common SRAM of DSP development board, is loaded on described outer engineering in the SDRAM of described DSP development board;
Buffer memory is divided module, for the storage space of dividing preset length at common SRAM as level 2 cache memory;
Read writing module, for the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read.
Wherein, described engineering splits in module, according to data type and read and write indegree the data segment in engineering described to be moved is split into two parts.
Wherein, described engineering load-on module comprises:
In sheet, engineering loads submodule, for described interior engineering is loaded on to the common SRAM of described DSP development board by pci interface;
DSP core suspends submodule, for by the DSP core break-off of described DSP development board, and opens the external memory interface of described DSP development board;
The outer engineering of sheet loads submodule, for described outer engineering is loaded on to the SDRAM of described DSP development board by described pci interface and external memory interface;
Remove DSP halted state submodule, for the DSP core of described DSP development board being restarted to operation.
Wherein, described in read in writing module, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and read and comprise:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
Wherein, described in read in writing module, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and write and comprise:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory, described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM; If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
(3) beneficial effect
The present invention is by being split as two parts by engineering to be moved, be respectively loaded in SRAM and SDRAM, may thereby the loading of giving big data quantity and heavy construction provides, and by level 2 cache memory is set, guarantee that heavy construction not only can load, and can keep the treatment effeciency the same with mini engineering; Developer can be on this hardware platform, almost unconfined interpolation program and chunk data, because the theoretical extending space outside sheet can reach GB rank, but dsp chip can not slow down because of the interpolation of DSP engineering Program and data to the treatment effeciency of engineering.
Accompanying drawing explanation
Fig. 1 is the connected mode schematic diagram between prior art Computer and DSP development board;
Fig. 2 is the process flow diagram of efficient operation method of the DSP engineering of one embodiment of the present invention;
Fig. 3 is that method of the present invention is at the schematic diagram that loads engineering;
Fig. 4 is method of the present invention at the schematic diagram that data read and data write;
Fig. 5 is the process flow diagram of high-efficiency operation system of the DSP engineering of one embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
Fig. 2 is the process flow diagram of efficient operation method of the DSP engineering of one embodiment of the present invention; With reference to Fig. 2, said method comprising the steps of:
S1: the data segment in engineering to be moved is split into two parts, and a part is as engineering in sheet, another part data segment and described in program segment in engineering to be moved as the outer engineering of sheet;
S2: with reference to Fig. 3, described interior engineering is loaded in the common SRAM of DSP development board, described outer engineering is loaded in the SDRAM of described DSP development board;
S3: divide the storage space of preset length as level 2 cache memory in common SRAM;
S4: with reference to Fig. 4, the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read.
Due to the length less (as the data of int type) of some data type in data segment or read that to write indegree (reading in engineering to be moved write indegree) higher, for improving the operational efficiency of DSP engineering, can be using this partial data section engineering in sheet, the engineering outside sheet using remaining data segment and program segment, preferably, in step S1, according to data type and read and write indegree the data segment in engineering described to be moved is split into two parts.
With reference to Fig. 3, for realizing engineering and the sheet loading of engineering outward in sheet, preferably, step S2 comprises:
S201: described interior engineering is loaded in the common SRAM of described DSP development board by pci interface;
S202: by the DSP core operation suspension of described DSP development board, and open the external memory interface of described DSP development board;
S203: described outer engineering is loaded in the SDRAM of described DSP development board by described pci interface and external memory interface;
S204: the DSP core of described DSP development board is restarted to operation.
With reference to Fig. 4, because the data of the data in level 2 cache memory and described SDRAM may be inconsistent for occurring, for guaranteeing its consistance, preferably, in step S4, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and read and comprise:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
Because the data of the data in level 2 cache memory and described SDRAM may be inconsistent for occurring, for guaranteeing its consistance, preferably, in step S4, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and write and comprise:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory, described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM; If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
Embodiment
With a specific embodiment, the present invention is described below, but does not limit protection scope of the present invention.The method of the present embodiment comprises:
Step 1: (the tool software hex6x.exe that the .out file Xian Yong Texas Instruments that engineering is generated provides becomes hexadecimal hex file by engineering to be moved, engineering to be moved described in hex file is) data segment in splits (fractured operation is carried out in chained file .cmd file) and becomes two parts, (data length is less or read and write the more data segment of indegree as engineering in sheet for a part, be designated as in_chip.dat), another part data segment and described in program segment in engineering to be moved as the outer engineering (being designated as out_chip.dat) of sheet, wherein, in sheet, the start address of engineering in hex file is 0x00000000, and the start address of the outer engineering of sheet in hex file is 0x80000000.
Step 2: with reference to Fig. 3, because the data in engineering in sheet can often be called, in order to guarantee the read or write speed of this part data, do not affect the speed of whole engineering, so described interior engineering is loaded in the common SRAM of described DSP development board by pci interface;
Step 3: for writing smoothly the outer engineering of sheet, need first by the DSP core operation suspension of described DSP development board, and open in external memory interface EMIF(the present embodiment of described DSP development board, revise the value of EMIF control register by pci interface and open);
Step 4: because the data in the outer engineering of sheet are are seldom read and write, treatment effeciency is had to slight decline, but the space of SDRAM is large, can put more data, so described outer engineering is loaded in the SDRAM of described DSP development board by described pci interface, enhancement mode direct memory access (EDMA) controller and external memory interface EMIF;
Step 5: the DSP core of described DSP development board is restarted to operation (in the present embodiment, sent out and interrupt waking up DSP core to DSP development board by PCI control register).
Step 6: engineering starts normal operation, the storage space of dividing preset length in the common SRAM not used is as level 2 cache memory;
In this step, the CSL library file first providing by Texas Instrument is opened up the level 2 cache memory of preset length in common SRAM, and the cache that the CSL library file that Zai Yong Texas Instrument provides is opened SDRAM enables, like this, data in SDRAM and program just can buffer memory to described level 2 cache memory
Step 7: the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read.
In step 7, with reference to Fig. 4, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and write and comprise:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory (transmitting by EMIF and EDMA controller), described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM and (by EMIF and EDMA controller, carries out write-back); If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
In step 7, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and read and comprise:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
In step 7, because the program segment in SDRAM is read-only, do not write, so Maintenance free consistance, DSP engineering can efficiently be moved according to said method.
The invention also discloses a kind of high-efficiency operation system of DSP engineering, with reference to Fig. 5, described system comprises:
Engineering splits module, and for the data segment of engineering to be moved is split into two parts, a part is as engineering in sheet, another part data segment and described in program segment in engineering to be moved as the outer engineering of sheet;
Engineering load-on module, for described interior engineering being loaded on to the common SRAM of DSP development board, is loaded on described outer engineering in the SDRAM of described DSP development board;
Buffer memory is divided module, for the storage space of dividing preset length at common SRAM as level 2 cache memory;
Read writing module, for the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read (being operation normally and efficiently of engineering).
Preferably, described engineering splits in module, according to data type and read and write indegree the data segment in engineering described to be moved is split into two parts.
Preferably, described engineering load-on module comprises:
In sheet, engineering loads submodule, for described interior engineering is loaded on to the common SRAM of described DSP development board by pci interface;
DSP core suspends submodule, for by the DSP core break-off of described DSP development board, and opens the external memory interface of described DSP development board;
The outer engineering of sheet loads submodule, for described outer engineering is loaded on to the SDRAM of described DSP development board by described pci interface and external memory interface;
Remove DSP halted state submodule, for the DSP core of described DSP development board being restarted to operation.
Preferably, described in read in writing module, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and read and comprise:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
Preferably, described in read in writing module, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and write and comprise:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory, described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM; If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
Above embodiment is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. an efficient operation method for DSP engineering, is characterized in that, said method comprising the steps of:
S1: the data segment in engineering to be moved is split into two parts, and a part is as engineering in sheet, another part data segment and described in program segment in engineering to be moved as the outer engineering of sheet;
S2: described interior engineering is loaded in the common SRAM of DSP development board, described outer engineering is loaded in the SDRAM of described DSP development board;
S3: divide the storage space of preset length as level 2 cache memory in common SRAM;
S4: the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read.
2. the method for claim 1, is characterized in that, in step S1, according to data type and read and write indegree the data segment in engineering described to be moved is split into two parts.
3. the method for claim 1, is characterized in that, step S2 comprises:
S201: described interior engineering is loaded in the common SRAM of described DSP development board by pci interface;
S202: by the DSP core operation suspension of described DSP development board, and open the external memory interface of described DSP development board;
S203: described outer engineering is loaded in the SDRAM of described DSP development board by described pci interface and external memory interface;
S204: the DSP core of described DSP development board is restarted to operation.
4. the method for claim 1, is characterized in that, in step S4, realizes data read and comprise between described DSP core and described SDRAM by described level 2 cache memory and 1 DBMS buffer memory:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
5. the method for claim 1, is characterized in that, in step S4, realizes data write and comprise between described DSP core and described SDRAM by described level 2 cache memory and 1 DBMS buffer memory:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory, described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM; If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
6. a high-efficiency operation system for DSP engineering, is characterized in that, described system comprises:
Engineering splits module, and for the data segment of engineering to be moved is split into two parts, a part is as engineering in sheet, another part data segment and described in program segment in engineering to be moved as the outer engineering of sheet;
Engineering load-on module, for described interior engineering being loaded on to the common SRAM of DSP development board, is loaded on described outer engineering in the SDRAM of described DSP development board;
Buffer memory is divided module, for the storage space of dividing preset length at common SRAM as level 2 cache memory;
Read writing module, for the DSP core of described DSP development board and be loaded with between the common SRAM of described interior engineering 1 DBMS buffer memory by described DSP development board and carry out that data read and data write, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize that data read and data write, between described DSP core and described SDRAM, by 1 grade of program buffer memory of described level 2 cache memory and described DSP development board, realize program and read.
7. system as claimed in claim 6, is characterized in that, described engineering splits in module, according to data type and read and write indegree the data segment in engineering described to be moved is split into two parts.
8. system as claimed in claim 6, is characterized in that, described engineering load-on module comprises:
In sheet, engineering loads submodule, for described interior engineering is loaded on to the common SRAM of described DSP development board by pci interface;
DSP core suspends submodule, for by the DSP core break-off of described DSP development board, and opens the external memory interface of described DSP development board;
The outer engineering of sheet loads submodule, for described outer engineering is loaded on to the SDRAM of described DSP development board by described pci interface and external memory interface;
Remove DSP halted state submodule, for the DSP core of described DSP development board being restarted to operation.
9. system as claimed in claim 6, is characterized in that, described in read in writing module, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and read and comprise:
First in described level 2 cache memory, search data to be read, if there is no described data to be read in described level 2 cache memory, from described SDRAM, search described data to be read, by described SDRAM, described data to be read are transferred to described DSP core by described level 2 cache memory and 1 DBMS buffer memory successively; If there are described data to be read in described level 2 cache memory, the data described to be read that first lost efficacy in described level 2 cache memory, again by data transmission to be read and write described in described SDRAM to described level 2 cache memory, the legacy data that covers original described data to be read, finally transfers to described DSP core by the new data described to be read in described level 2 cache memory by described 1 DBMS buffer memory.
10. system as claimed in claim 6, is characterized in that, described in read in writing module, between described DSP core and described SDRAM, by described level 2 cache memory and 1 DBMS buffer memory, realize data and write and comprise:
When described DSP core is data writing operation, first in described level 2 cache memory, search data to be written, if there is no described data to be written in described level 2 cache memory, from described SDRAM, search described data to be written, by described SDRAM by described data transmission to be written to described level 2 cache memory, described DSP core carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM; If there are described data to be written in described level 2 cache memory, described DSP core directly carries out write operation by described 1 DBMS buffer memory to described data to be written, and described level 2 cache memory is written back to the data to be written after write operation in described SDRAM.
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