CN103731359A - FIFO cache sharing router based on fiber delay lines and working method thereof - Google Patents
FIFO cache sharing router based on fiber delay lines and working method thereof Download PDFInfo
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Abstract
The invention discloses a FIFO cache sharing router based on fiber delay lines and a working method of the FIFO cache sharing router. The cache sharing router allows sharing of N packets and structurally comprises a (N+M)*(N+M) non-blocking optical switching matrix, the M fiber delay lines and a logic control unit. By setting optical fiber delay line lengths (img file='23068dest_path_image002.TIF', wi='216', he='24'/) and adopting the packet scheduling algorithm based on sorting, the FIFO light cache sharing function can be simulated under the condition of the arrival of any packet by the FIFO cache sharing router based on the fiber delay lines according to the working method.
Description
Technical field
The present invention relates to the queue of a kind of smooth FIFO shared buffer memory, specifically utilize fiber delay line to realize light grouping dynamic buffering, by feedback structure, realizing light buffer memory shares, and then ensure that by the scheduling strategy based on sequence grouping FIFO dispatches and make full use of fiber delay line storage resources, has realized a kind of full light FIFO shared buffer memory queue based on fiber delay line.
Background technology
In optical transport network, due to the optical memory not having physically, in storage forwarding (store-and-forward) mode, transmitting the network node of information, people are first converted to the signal of telecommunication by the light signal of arrival conventionally, and then by electrical storage (as RAM) storage, then when port is idle, be converted to again light signal and send to light path.But the method for this " light-electrical-optical " conversion has seriously limited the speed of light processing data packets, has brought a large amount of energy consumption simultaneously.On the other hand, fiber delay line (fiber delay line, FDL) is considered at present unique feasible other change of medium that do not need and realizes the method for light signal " storage ".There is the characteristic of time delay in FDL, with different length optical fiber, as medium, postpones input optical signal while mainly utilizing light signal to propagate in optical fiber, thus simulated light caching function.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of router and method of work thereof that realizes full light FIFO shared buffer memory in optical switching network.
Described FIFO shared buffer memory router comprises N input link, and N output link and N abandon link, the clog-free optical switching matrix of (N+M) * (N+M), the Switching Module of N 1 * 2, M bar fiber delay line and a logic control element;
The N of clog-free optical switching matrix input port connects N input link, and N output port is by N output link of Switching Module connection and the individual link that abandons of N of N individual 1 * 2, and a remaining M output port connects back M input port by M bar fiber delay line; Logic control element connects the control end of clog-free optical switching matrix.
Further improve fiber delay time line length r
ibe set to
forming size is the shared buffer memory queue of B, and allows all input/output port access, wherein
The present invention also provides a kind of method of work of the FIFO shared buffer memory router based on fiber delay line, comprises light grouping cache and light packet switching; Light grouping it is characterized in that specifically comprising the following steps: when need to be buffered, by external input port, by fifo queue, send into fiber delay line, via fiber delay line, produce propagation delay time, then send into fiber delay line by switching matrix, realize the dynamic memory light signal that repeatedly circulates; Each light grouping is afterwards left by fifo queue or when cache overflow, will directly be forwarded to output port by switching matrix, and the Switching Module via 1 * 2 is forwarded to respectively output link or abandons link.
Above-mentioned fifo queue setting up procedure is:
1) all arrival groupings are divided into N stream according to its output port, and controller is that the grouping that belongs to same stream distributes unique value K to represent the order of leaving of this grouping, and when there being grouping to leave, the value of leaving that belongs to all groupings of same stream subtracts 1;
2) M bar delay line is divided into N group, every group of delay line belongs to a stream, and length increases according to linear programming, 1,2,3....
The process of fifo queue shared buffer memory is:
The grouping that the value of leaving is k is always sent to the fiber delay line that length is not more than k.
The flow process of FIFO buffer queue packet scheduling is:
Control logic c
j(t), j|[0, N|1] represent output link state, if c
j(t)=1 represents that output link j allows grouping to leave, otherwise output link closes, at each time slot, for all groupings that appear at a switching matrix M+N input port:
1) value of the leaving K of all stores packets is subtracted to 1, the grouping that is 0 by the value of leaving sends to corresponding output link;
2) grouping at a switching matrix M+N output port is left to port according to it and be divided into N stream;
3) to appearing at the grouping that belongs to i stream of switching matrix input, i=1, ..., N, according to grouping, leave sequence valve sequence, the grouping of sorting is sent to successively the short time delay line that belongs to i stream group and is arrived long delay line leave order according to it, repeats this process, until N stream;
4) for each stream, be not assigned to the grouping of delay line, according to the backward of its value of leaving K, send to successively idle long delay line successively and arrive short time delay line;
5) if there is no idle delay line, packets remaining is abandoned via idle output port.
Beneficial effect of the present invention is:
1, realize the shared light buffer memory of high resource utilization.The all input/output ports of shared buffer memory queue router topology are total, do not limit the cache size of single stream, have optimum Buffer Utilization.
2, adopt feedback structure and fiber delay line to realize shared buffer memory.Fiber delay line utilizes light signal to avoid router port collision problem in the propagation delay time of media.Meanwhile, the fiber delay line based on feedback structure can make light signal repeatedly circulation in delay line, realizes the object of optical storage.This strategy is the mode of current unique physically realizable smooth buffer memory.
3, support Preemptive priority scheduling.By realize the scheduling strategy based on sequence, ensure arrive light grouping can according to FIFO order without time delay send to corresponding output port.
4, the grouping that the value of leaving is k is always sent to the fiber delay line that length is not more than k, avoids the extra time delay producing because of packet scheduling by this scheduling rule.
Accompanying drawing explanation
Fig. 1 (a) (b) (c) is feedback fiber delay line buffer structure;
Fig. 2 is N-to-N shared buffer memory schematic diagram;
Fig. 3 is the FIFO shared buffer memory queue structure based on fiber delay line.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
For realizing object of the present invention, the invention provides a kind of full light FIFO shared buffer memory queue structure based on fiber delay line, below in conjunction with accompanying drawing, be elaborated.
Light networking lacks the light packet switching that necessary light buffer memory is realized Store and forword, smooth FIFO shared buffer memory of the present invention queue structure has avoided light-electrical-optical conversion of inefficiency to realize light packet memory, by current physically realizable fiber delay line and optical switching matrix, realizes grouping cache.There is the characteristic of time delay in fiber delay line, with different length optical fiber, as medium, postpones input optical signal while mainly utilizing light signal to propagate in optical fiber, thus simulated light caching function.The router topology of 2-to-2 shown in Fig. 1 of take is example: (a) grouping is sent into fiber delay line by 2 * 2 smooth crosspoints after arriving; (b) be grouped in fiber delay line and circulate and realize specific time delay by limited number of time; (c) by 2 * 2 smooth crosspoints, deliver to output.
Function, shared buffer memory is the type of memory that Buffer Utilization is the highest, as shown in Figure 2.Full light FIFO shared buffer memory queue mainly contains three factors to be needed to investigate: the institutional framework of FDL and switching matrix, the length setting of a plurality of FDLs, and packet scheduling algorithm.We adopt single-stage feedback structure, and all delay lines are organized with the nonblocking switch fabric that can realize any transposition, further design complicated delay line setting and packet scheduling, and system configuration as shown in Figure 3.
1, light FIFO shared buffer memory router topology
The design comprises N input link, and N output link and N abandon link, one (N+M) * (N+M) clog-free optical switching matrix, M bar fiber delay line and logic control element.
The N of nonblocking switch fabric input port connects N input link, and N output link of Switching Module connection by N 1 * 2 of N output port and N is individual abandons link remains M output port and pass through M bar fiber delay line and connect back M input port.
Adopt feedback structure to realize light buffer memory.M root fiber delay line connects switching matrix output port and input port.When grouping need to be stored, by external input port, send into fiber delay line, via fiber delay line, produce propagation delay time, then send into fiber delay line by switching matrix, realize the object of the dynamic memory light signal that repeatedly circulates.If grouping is left or cache overflow, will directly be forwarded to output port by switching matrix, the Switching Module via 1 * 2 is forwarded to respectively output link or abandons link.
2, fiber delay time line length arranges
Fiber delay time line length r
ibe set to r
i=1+[(i-1) modN], i=1,2 ..., M.All fiber delay lines are the shared buffer memory queue of B by forming size, allow all input/output port access, wherein
M bar delay line is divided into N group, and every group of fiber delay line belongs to a stream.
3, FIFO scheduling strategy
(a) priority setting
All arrival grouping is assigned with unique priority integer value and represents that this expectation being grouped in the stream of place leaves order.
(b) priority scheduling rules
The grouping that the value of leaving is k is always sent to the fiber delay line that length is not more than k.By this scheduling rule, avoid the extra time delay producing because of packet scheduling.
(c) flow process of packet scheduling is:
Control logic c
j(t), j ∈ [0, N-1] represents output link state.If c
j(t)=1 represents that output link j allows grouping to leave, otherwise output link is closed.At each time slot, for all groupings that appear at a switching matrix M+N input port,
1) value of leaving of all stores packets is subtracted to 1, the grouping that is 0 by the value of leaving sends to corresponding output link;
2) grouping at a switching matrix M+N output port is left to port according to it and be divided into N stream;
3) to appearing at the grouping that belongs to i stream of switching matrix input, i=1 ..., N, leaves sequence valve sequence according to grouping.The grouping of sorting is sent to successively the short time delay line that belongs to i stream group and is arrived long delay line leave order according to it.Repeat this process, until N stream;
4) for each stream, be not assigned to the grouping of delay line, according to the backward of its value of leaving, send to successively idle long delay line to short time delay line successively;
5) if there is no idle delay line, by packets remaining via idle output port.
The concrete application approach of the present invention is a lot, and the above is only the preferred embodiment of the present invention, should be understood that; for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvement, these improvement also should be considered as protection scope of the present invention.
Claims (6)
1. the FIFO shared buffer memory router based on fiber delay line, it is characterized in that comprising: N input link, N output link and N abandon link, the clog-free optical switching matrix of one (N+M) * (N+M), the Switching Module of N individual 1 * 2, M bar fiber delay line and a logic control element;
The N of clog-free optical switching matrix input port connects N input link, and N output port is by N output link of Switching Module connection and the individual link that abandons of N of N individual 1 * 2, and a remaining M output port connects back M input port by M bar fiber delay line; Logic control element connects the control end of clog-free optical switching matrix.
2. the FIFO shared buffer memory router based on fiber delay line according to claim 1, is characterized in that: fiber delay time line length r
ibe set to
forming size is the shared buffer memory queue of B, and allows all input/output port access, wherein
3. a method of work for the FIFO shared buffer memory router based on fiber delay line, comprises light grouping cache and light packet switching; Light grouping it is characterized in that specifically comprising the following steps: when need to be buffered, by external input port, by fifo queue, send into fiber delay line, via fiber delay line, produce propagation delay time, then send into fiber delay line by switching matrix, realize the dynamic memory light signal that repeatedly circulates; Each light grouping is afterwards left by fifo queue or when cache overflow, will directly be forwarded to output port by switching matrix, and the Switching Module via 1 * 2 is forwarded to respectively output link or abandons link.
4. the method for work of the FIFO shared buffer memory router based on fiber delay line according to claim 1, is characterized in that described fifo queue setting up procedure is:
1) all arrival groupings are divided into N stream according to its output port, and controller is that the grouping that belongs to same stream distributes unique value K to represent the order of leaving of this grouping, and when there being grouping to leave, the value of leaving that belongs to all groupings of same stream subtracts 1;
2) M bar delay line is divided into N group, every group of delay line belongs to a stream, and length increases according to linear programming, 1,2,3....
5. according to the method for work of the FIFO shared buffer memory router based on fiber delay line described in claim 3 or 4, it is characterized in that for the process of fifo queue shared buffer memory being: the grouping that the value of leaving is k is always sent to the fiber delay line that length is not more than k.
6. according to the method for work of the FIFO shared buffer memory router based on fiber delay line described in claim 3 or 4, it is characterized in that the flow process of FIFO buffer queue packet scheduling is:
Control logic c
j(t), j|[0, N|1] represent output link state, if c
j(t)=1 represents that output link j allows grouping to leave, otherwise output link closes, at each time slot, for all groupings that appear at a switching matrix M+N input port:
1) value of the leaving K of all stores packets is subtracted to 1, the grouping that is 0 by the value of leaving sends to corresponding output link;
2) grouping at a switching matrix M+N output port is left to port according to it and be divided into N stream;
3) to appearing at the grouping that belongs to i stream of switching matrix input, i=1, ..., N, according to grouping, leave sequence valve sequence, the grouping of sorting is sent to successively the short time delay line that belongs to i stream group and is arrived long delay line leave order according to it, repeats this process, until N stream;
4) for each stream, be not assigned to the grouping of delay line, according to the backward of its value of leaving K, send to successively idle long delay line successively and arrive short time delay line;
5) if there is no idle delay line, packets remaining is abandoned via idle output port.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111880726A (en) * | 2020-06-19 | 2020-11-03 | 浙江工商大学 | Method for improving CNFET cache performance |
| CN115016918A (en) * | 2022-03-31 | 2022-09-06 | 中国科学院计算技术研究所 | Data processing method for computing equipment of data flow architecture |
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Non-Patent Citations (1)
| Title |
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| XIAOLIANG WANG.ETC: "Constructing N-to-N Shared Optical Queues With Switches and Fiber Delay Lines", 《IEEE》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111880726A (en) * | 2020-06-19 | 2020-11-03 | 浙江工商大学 | Method for improving CNFET cache performance |
| CN111880726B (en) * | 2020-06-19 | 2022-05-10 | 浙江工商大学 | Method for improving CNFET cache performance |
| CN115016918A (en) * | 2022-03-31 | 2022-09-06 | 中国科学院计算技术研究所 | Data processing method for computing equipment of data flow architecture |
| CN115016918B (en) * | 2022-03-31 | 2024-06-11 | 中国科学院计算技术研究所 | Data processing method for computing device of data flow architecture |
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