CN103731317B - Method and device for PCIE address mapping detection - Google Patents
Method and device for PCIE address mapping detection Download PDFInfo
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Abstract
The embodiment of the invention provides a method and device for PCIE address mapping detection. The method comprises the steps that a source device writes a PTMP request message in a current PCIE address of a target device; if it is detected that a PTMP response message written in by the target device exists in the current PCIE address of the target device within the preset time, whether response testing data carried in the PTMP response message is the same as test data carried in the PTMP request message or not is judged; if it is determined that the response testing data carried in the PTMP response message is the same as the test data carried in the PTMP request message, the current PCIE address mapping of the target device and the source device is correct; a series of determination flows are carried out in follow-up operation so as to judge whether other PCIE address mappings of the target device and the source device are correct or not. According to the method and device for PCIE address mapping detection, all the PCIE addresses of the two PCIE bus devices can be detected at the same time by utilizing interaction of the PTMP request message and the response message between the source device and the target device, the detection time is shorter, and the detection accuracy rate is higher.
Description
Technical field
The present invention relates to communication technical field, more particularly, to a kind of method and device of PCIE address of cache detection.
Background technology
Quick external equipment interconnection (Peripheral Component Interconnect Express, PCIE) has
The high advantage of message transmission rate, at present, this message transmission rate highest 16X 2.0 version can reach 10GB/s, Neng Gouman
The demand of low-speed device and high-speed equipment in sufficient the present and the future's certain time.
As shown in figure 1, above-mentioned PCIE architectural framework, generally include root assembly (Root Complex, RC) 101, exchange
Equipment (Switch) 102 and multiple terminal devices (End Point, EP) 103.Wherein, RC101 mainly completes resource allocation, sets
Distribute PCIE address for configuration (bus number/device numbering of such as configuration equipment/function numbering) and for itself with EP；
The downstream port of RC101 can mount Switch102 and extend more PCIE ports naturally it is also possible to directly mount EP；
The downstream port of Switch102 can mount multiple EP103, and Switch102 primarily serves the effect of extension PCIE architectural framework.
In above-mentioned PCIE architectural framework, when RC carries out pci bus and enumerates (Bus Enumeration), from PCIE bus
It is that itself distributes PCIE address with each EP, so that when EP starts, the memory address in local storage domain can map in domain
To PCIE address.
In order to ensure the proper communication between equipment in PCIE architectural framework, it usually needs the PCIE address of EP or RC is reflected
Inject row detection, it is impossible to carry out subsequent communications if PCIE address mapping error.At present, following two kinds of sides are generally adopted
Formula realizes the detection of PCIE address of cache：
First kind of way：Source device writes affairs by PCIE storage, writes pre- in the specified PCIE address of target device
If test data, by target device, the test data of write in this specified PCIE address is printed, then, with preset data
Compare, whether correct with the specified PCIE address of cache that determines target device, if adopting detection source device in this way
PCIE address if, reverse operating.
The second way：Target end equipment first writes default test data, Ran Houyuan in local specified PCIE address
Equipment stores, by PCIE, the test data that read transaction reads write in this specified PCIE address, then, carries out with preset data
Compare, whether correct with the specified PCIE address of cache that determines target device, if adopting detection source device in this way
If PCIE address, reverse operating.
No matter PCIE address is detected using which kind of mode above-mentioned, unidirectional detection can only be realized, that is, detect source device side
PCIE address, or the PCIE address of target device side, this results in when needing to detect source device and target device simultaneously
Detection time is longer.
Content of the invention
Embodiments provide a kind of method and device of PCIE address of cache detection, in order to solve existing detection
The longer problem of the detection time of PCIE address of cache.
Based on the problems referred to above, a kind of method of PCIE address of cache detection provided in an embodiment of the present invention, including：
Source device write in the current PC IE address of described target device point-to-multipoint (Point To Multipoint,
PTMP) request message, the current PC IE address of described target device is described source device according to the local target device preserving
PCIE base address and current PC IE address offset are determined, carry current PC IE of active equipment in described PTMP request message
Address offset and test data；
If there being the PTMP of described target device write in the current PC IE address monitoring itself in Preset Time
Back message is it is determined that whether the response test data that carries in described PTMP back message is taken with described PTMP request message
The test data of band is identical, and the current PC IE address of described source device is that described target device is monitoring current PC IE of itself
After having PTMP request message in address, in the PCIE base address and described PTMP request message according to the local source device preserving
The current PC IE address offset of the source device carrying is determined, carries target device next in described PTMP back message
Individual PCIE address offset and response test data；
When being defined as identical, determine that the current PC IE address of cache of described target device and described source device is correct, and
By the next PCIE address offset of the target device carrying in described PTMP back message and the next PCIE address of itself
Skew, is compared with default PCIE address offset respectively, is determined under described target device and itself according to comparative result
One PCIE address, using it as described target device and the current PC IE address of itself, returns to described target device
Current PC IE address in write the step of described PTMP request message, carry in described PTMP back message until determining
The next PCIE address offset of target device, and the next PCIE address offset of itself to be described default PCIE address inclined
Detection of end during shifting.
A kind of detection means of PCIE address of cache provided in an embodiment of the present invention, including：
Writing module, for writing PTMP request message, described target in the current PC IE address to described target device
The current PC IE address of equipment is PCIE base address and the current PC IE address of the target device according to local preservation for the described device
Skew is determined, carries current PC IE address offset and the test data of described device in described PTMP request message；
Whether monitoring modular, for having described target in the current PC IE address of monitoring described device in Preset Time
The PTMP back message of equipment write, the current PC IE address of described device is that described target device is monitoring the current of itself
After having PTMP request message in PCIE address, the PCIE base address according to the local described device preserving and described PTMP ask
The current PC IE address offset of the described device carrying in message is determined, carries target and set in described PTMP back message
Standby next PCIE address offset and response test data；
Determining module, has described target device in the current PC IE address of described monitoring module monitors to described device
During the PTMP back message of write, determine whether the response test data carrying in described PTMP back message please with described PTMP
Ask the test data carrying in message identical, and when being defined as identical, determine the current of described target device and described device
PCIE address of cache is correct, by the next PCIE address offset of the target device carrying in described PTMP back message and described
The next PCIE address offset of device, is compared with default PCIE address offset respectively, determines institute according to comparative result
State the next PCIE address of target device and described device, it is current as described target device and described device
PCIE address, returns the step writing described PTMP request message in the current PC IE address of described target device, until true
Make the next PCIE address offset of the target device carrying in described PTMP back message, and the next one of described device
Detection of end when PCIE address offset is described default PCIE address offset.
The beneficial effect of the embodiment of the present invention includes：
A kind of method and device of PCIE address of cache detection provided in an embodiment of the present invention, using PTMP request message and
Back message, in interaction between source device and target device, is compared the response test number in local PCIE address by source device
According to whether identical with the test data writing target device before, to determine the PCIE mapping to be detected of source device and target device
Whether correct, thus realizing the two-way detection of source device and target device, significantly shorten detection time.
Brief description
Fig. 1 is the schematic diagram of existing PCIE architectural framework；
Fig. 2 is the method flow diagram of PCIE address of cache detection provided in an embodiment of the present invention；
Fig. 3 is the structural representation of PTMP request message provided in an embodiment of the present invention；
Fig. 4 A- Fig. 4 D is the detection interaction schematic diagram of source device provided in an embodiment of the present invention and target device；
Fig. 5 is the structure drawing of device of PCIE address of cache detection provided in an embodiment of the present invention.
Specific embodiment
Existing PCIE address of cache detection mode, can only unidirectional detect, detection time is longer.Based on this problem, this
A kind of bright method and device providing PCIE address of cache to detect, using PTMP request message and back message in source device and mesh
Interaction between marking device, compares the response test data in local PCIE address by source device and writes target device before
Whether test data is identical, to determine that whether correctly source device and the PCIE to be detected of target device map, thus source of realizing sets
The standby two-way detection with target device, has shortened detection time significantly.
In the present invention, following detection modes referring to are applicable between RC and EP in PCIE architectural framework, also may be used
It is applied between EP and EP, for the ease of subsequent descriptions testing process, the equipment that perform detection is operated is referred to as " source device ",
Detected equipment is referred to as " target device ", so, for above-mentioned PCIE architectural framework, EP or RC can make
For source device it is also possible to as target device, such as, in the case that EP is for source device, any one in other EP all can be made
For target device, RC also can be used as target device；In the case that RC is as source device, any one in each EP can conduct
Target device.
Further, no matter being source device, or target device, they are locally all set up in advance has one to be stored with each
The corresponding relation of device identification and respective PCIE base address (i.e. PCIE initial address) data base, in order to their bases
Each self-corresponding PCIE base address is searched in device identification.For example, device identification can be compiled for bus number/device numbering/function
Number (Bus/Device/Function number, BDF).
In other words, for source device and target device, it is to know the PCIE address of oneself each other, that is, knows oneself
PCIE base address and each PCIE address corresponding PCIE address offset, but be only capable of each other being known according to above-mentioned data base
The PCIE base address of opposite end, subsequently can carry out write operation in PCIE base address each other, if want each other respective other
When PCIE address carries out write operation, both sides are needed to arrange other PCIE address offsets respective in advance, so, source device and target set
Standby all can be according to the PCIE base address of other side, and other PCIE address offsets of respective agreement determine other PCIE addresses, so
Laggard row write operation etc..
With reference to Figure of description, the method that a kind of PCIE address of cache provided in an embodiment of the present invention is detected and dress
The specific embodiment put illustrates.
A kind of method of PCIE address of cache detection provided in an embodiment of the present invention, as shown in Fig. 2 specifically include following step
Suddenly：
S201：Source device writes PTMP request message in the current PC IE address of target device；
Here, the current PC IE address of above-mentioned target device, actually source device set according to the local target preserving
Standby PCIE base address and current PC IE address offset are determined, and carry the current of active equipment in PTMP request message
PCIE address offset and test data；
That is, the current PC IE address of target device can be the PCIE base address of target device, now, source device
The current PC IE address offset of the target device that side preserves is 0；Can also be its in addition to PCIE base address of target device
His PCIE address, now, this other PCIE address, except preserving the PCIE base address of target device, is also preserved in source device side
Skew；In addition, for the current PC IE address offset of source device, can be corresponding according to each PCIE address of itself by source device
PCIE address offset is specified；
S202：The PTMP whether having target device write in the current PC IE address monitoring itself in Preset Time returns
Answer message；If so, execution step S203；Otherwise, execution step S204；
Here, the current PC IE address of above-mentioned source device, actually target device are monitoring the current of itself
After having PTMP request message in PCIE address, in the PCIE base address and PTMP request message according to the local source device preserving
The current PC IE address offset of the source device carrying is determined, and the PTMP of write returns in the current PC IE address of source device
Answer the next PCIE address offset carrying target device in message and respond test data；
S203：Determine the response test data carrying in PTMP back message whether with the survey that carries in PTMP request message
Examination data is identical；If so, execution step S205；Otherwise, execution step S206；
S204：Determine the current PC IE address mapping error of target device.
S205：Determine that the current PC IE address of cache of target device and source device is correct, and will take in PTMP back message
The next PCIE address offset of target device of band and the next PCIE address offset of itself, respectively with default PCIE ground
Location skew is compared, and determines target device and the next PCIE address of itself according to comparative result, using it as mesh
Marking device and the current PC IE address of itself, return the step writing PTMP request message in the current PC IE address of target device
Suddenly, until determining the next PCIE address offset of the target device carrying in PTMP back message, and the next one of itself
Detection of end when PCIE address offset is default PCIE address offset；
S206：Determine the current PC IE address mapping error of source device.
Conventionally, as the specified PCIE address of source device or target device side is open, this is easy for leading
Cause the data cover that the test data writing during detection may be write by other equipment to fall, and then lead to testing result not accurate
Really.
In order to solve this problem, in embodiments of the present invention, by controlling the running status of source device and target device, make
It is not disturbed during both sides' detection, to improve Detection accuracy, i.e. source device can itself is set to busy state,
And after determining that target device is in idle condition, execute above-mentioned steps S201, so, interact with target device in source device
During, would not be affected on locally executing write operation by some other equipment in PCIE architectural framework, and then be improve
Detection accuracy.
Further, source device can be by the side of the data outside the write setting data in local PCIE base address
Formula, determines that itself is in busy state；In addition, source device by read target device PCIE base address in related data Lai
Determine the state of target device, specially：When data in the PCIE base address reading out target device is setting data, really
The equipment of setting the goal is in idle condition.
It should be noted that above-mentioned setting data can be specified in advance, it is used for representing equipment and is in idle condition, for example, will set
According to being set as full 0, the equipment of representative is in idle condition to fixed number, certainly, for the data in the PCIE base address of target device
Speech, different data represents target device and is in different running statuses, and such as data is during full 0 it is meant that target device
It is in idle condition；Data is during full F it is meant that the PCIE base address mistake of target device；When data is non-full 0 and non-full F,
Mean that target device is in busy state etc..
In above-mentioned steps S201, PTMP request message is that the embodiment of the present invention is used for transmitting test request, PCIE address
The protocol massages of the information such as skew, test data, as shown in figure 3, being the structural representation of this PTMP message, specifically may include
Source device mark (Src BDF), target device mark (Dst BDF), PCIE address offset and test data etc..
It should be noted that for the accuracy ensureing the PCIE address of cache detecting target device, above-mentioned test data
Both interactions are always maintained at constant.
In above-mentioned steps S201, source device write in the current PC IE address to target device PTMP request message it
Afterwards, for this side of target device, it can monitor the PTMP message that in this current PC IE address, whether active equipment writes,
It will usually check whether PTMP message is PTMP request message in the case of monitoring to have PTMP message, confirming
During for being, just execute follow-up write flow process, and after having executed follow-up write flow process, empty in this current PC IE address
Data, to ensure the accuracy detecting.For example, the PCIE base address of source device is 0x01000000, current PC IE of source device
Address offset is 0x00300000, in this case, by the write of PTMP back message according to 0x01000000 and
In the PCIE address that 0x00300000 determines.
It should be noted that in above-mentioned steps S202, above-mentioned Preset Time can according to the practical situation of detection value,
For example, Preset Time is 5 seconds, certainly can also be other numerical value.
Preferably, in above-mentioned steps S205, above-mentioned default PCIE address offset, it is used to characterize source device and target sets
No matter the next PCIE address offset of standby last PCIE address offset of both sides is that is to say, that be source device, or target
Equipment, if the next PCIE address offset that it carries in corresponding PTMP message is default PCIE address offset, this is just
Mean the PCIE address not needing to test.Here, default PCIE address offset for example may be set to 0XFFFF_
FFFF, it is of course also possible to using other modes mark, here will not enumerate.
Further, in above-mentioned steps S205, source device specifically can determine target device by following several ways
Next PCIE address with itself：
First kind of way：The next PCIE address offset of the target device carrying in comparing PTMP back message is not
For presetting PCIE address offset, and when the next PCIE address offset of itself is default PCIE address offset, set according to target
The next PCIE address offset of the target device carrying in standby PCIE base address and PTMP back message determines that target sets
Standby next PCIE address；And the PCIE base address according to itself and current PC IE address offset determine next of itself
Individual PCIE address；
The second way：The next PCIE address offset of the target device carrying in comparing PTMP back message is
Default PCIE address offset, and when the next PCIE address offset of itself is not default PCIE address offset, set according to target
Standby PCIE base address and current PC IE address offset determine the next PCIE address of target device；And according to itself
PCIE base address and next PCIE address offset determine the next PCIE address of itself；
The third mode：The next PCIE address offset of the target device carrying in comparing PTMP back message is not
For presetting PCIE address offset, and when the next PCIE address offset of itself is not default PCIE address offset, according to target
The next PCIE address offset of the target device carrying in the PCIE base address of equipment and PTMP back message determines target
The next PCIE address of equipment；And the PCIE base address according to itself and next PCIE address offset determine itself
Next PCIE address.
Specifically, in embodiments of the present invention, for source device and target device, and be unaware of other side be provided with many
Few PCIE address, then, the PCIE address of both sides there may be following several situations：
The first situation：Source device is identical with the PCIE number of addresses of target device, in this case, it is possible to have following
Two kinds of situations：
The first situation：Both sides only include each current PCIE address, in this case, source device and target device
Next PCIE address offset be default PCIE address offset, that is, both sides detect and finish, detection of end；
Second case, both sides include quantity identical PCIE address, in this case, if source device and target set
Standby next PCIE address offset is not all default PCIE address offset, then, mesh is determined using the third mode above-mentioned
Marking device and the next PCIE address of itself, until the PCIE address detected by both sides finishes end.For example, (source sets device A
Standby) include this 3 PCIE addresses of A1, A2 and A3；Equipment B (target device) includes this 3 PCIE addresses of B1, B2 and B3, then,
Device A is interacted with the detection of equipment B can be as shown in Figure 4 A.
Second situation：The PCIE number of addresses of source device is more than the PCIE number of addresses of target device, in this situation
Under, when the next PCIE address offset of source device and target device is not all default PCIE address offset, using above-mentioned the
Three kinds of modes are determining target device and the next PCIE address of itself；In the next PCIE address offset of target device it is
During default PCIE address offset, target device and the next PCIE address of itself are determined using the above-mentioned second way, directly
To the PCIE end of address (EOA) having detected source device.For example, device A (source device) includes this 5 PCIE ground of A1, A2, A3, A4 and A5
Location；Equipment B (target device) includes this 3 PCIE addresses of B1, B2 and B3, then, device A is interacted with the detection of equipment B can be such as
Shown in Fig. 4 B.
The third situation：The PCIE number of addresses of source device is less than the PCIE number of addresses of target device, in this situation
Under, when the next PCIE address offset of source device and target device is not all default PCIE address offset, using above-mentioned the
Three kinds of modes are determining target device and the next PCIE address of itself；It is default in the next PCIE address offset of itself
During PCIE address offset, target device and the next PCIE address of itself, Zhi Daojian are determined using above-mentioned first kind of way
Survey the PCIE end of address (EOA) of target device.For example, device A (source device) includes this 3 PCIE addresses of A1, A2 and A3；Equipment B
(target device) includes this 5 PCIE addresses of B1, B2, B3, B4 and B5, then, device A is interacted with the detection of equipment B can be as figure
Shown in 4C.
Certainly, the embodiment of the present invention is not limited in above-mentioned several ways to determine target device and the next one of itself
PCIE address, can also be realized using other determination modes, for example, be less than target device in the PCIE number of addresses of source device
It is assumed that the next PCIE address offset comparing source device is default PCIE address offset in the case of PCIE number of addresses,
At this moment, source device can select one in the next PCIE address offset from the PTMP message writing target device side before
Individual, the then base address according to itself and selection determines the next PCIE address of source device in the PCIE address offset going out,
This will not enumerate.
Preferably, in embodiments of the present invention, in order to improve the accuracy rate of PCIE address of cache detection, source device further
When not having the PTMP back message that target device writes in the current PC IE address monitoring itself, it is not immediately performed
State step S204, following flow processs can be first carried out：Again write PTMP request message in the current PC IE address of target device, and
When not monitoring PTMP back message yet when the number of times of the PTMP request message re-writing reaches the first set point number, then hold
Row above-mentioned steps S204.
Preferably, in embodiments of the present invention, in order to improve the accuracy rate of PCIE address of cache detection, source device further
The test data carrying in the response test data carrying in determining PTMP back message and PTMP request message differs
In the case of, above-mentioned steps S206 can not be immediately performed, first carry out following flow processs：Again to the current PC IE ground of target device
Location writes PTMP request message, and then the number of times in the PTMP request message re-writing reaches set point number, and determines
When test data in the response test data carrying in PTMP back message, with PTMP request message still differs, then execute
Above-mentioned steps S206.
It should be noted that preferably being carried out in flow process in above two, above-mentioned first set point number and the second set point number
All can determine, the two may be set to identical numerical value according to the practical situation of detection, also may be set to different numerical value, for example,
The two all may be set to 3.
Preferably, in embodiments of the present invention, in order to improve the accuracy rate of PCIE address of cache detection, source device further
The response test data carrying in determining PTMP back message whether with the test data phase that carries in PTMP request message
With afterwards, empty the data in the current PC IE address of source device, or have in monitoring this current PC IE address and newly write
During the PTMP message entering, cover the PTMP message of last write.
Below still taking device A (source device) and equipment B (target device) as a example, above-mentioned detection method is carried out briefly
Bright：
As shown in Figure 4 D it is assumed that the current PC IE address of device A is A1, corresponding PCIE address offset is X1, next
PCIE address is A2, and corresponding PCIE address offset is X2；The current PC IE address of equipment B is B1, and next PCIE address is
B2, corresponding PCIE address offset is Y2；The current PC IE address of equipment B is B1；Device A knows the current PC IE ground of equipment B
The PCIE address of location B1；In addition, it is assumed that device A writes the data outside full 0 to the PCIE base address (Fig. 4 D does not show) of itself,
Make it be currently at busy state, and the data having read in the PCIE base address of equipment B is full 0, the equipment B of determining is in
Idle condition.
So, in this case, device A need to execute above-mentioned steps S201, to the B1 write PTMP request report of equipment B
Literary composition, carries X1 and test data in this PTMP request message, and so, equipment B has this PTMP request message monitoring B1
Afterwards, determine the current PC IE address of device A according to the PCIE base address of the device A of acquisition from local data base and X1, that is,
A1, then, equipment B can write PTMP response message to A1, and (next PCIE address is inclined to carry Y2 in this PTMP response message
Move) and respond test data.
For device A, after it monitors the PTMP response message having equipment B write in A1, first confirm that
Response test data in PTMP response message whether identical with the test data writing B1 before it is assumed that confirming as identical, that
, device A determines the next PCIE of equipment B according to the PCIE base address of equipment B obtaining from local data base and Y2
Address, i.e. B2, and confirm that Y2 is not 0XFFFF_FFFF (default offset address), at this moment, write again to B2 and carry X2
With the PTMP request message of above-mentioned test data, equipment B is when monitoring that B2 has PTMP request message it is known that this address is this
Last PCIE address on ground, in this case, it carries to A2 (concrete determination process the is ibid) write of device A
0XFFFF_FFFF and the PTMP response message responding test data, so, related data in monitoring A2 for the device A
When it is assumed that still confirming as identical, at this moment, A2 is last the PCIE address of itself, and that is, the next PCIE address of itself is inclined
Move as 0XFFFF_FFFF, the next PCIE address offset also 0XFFFF_FFFF of equipment B, show that detection finishes, exit detection
Flow process.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of device of PCIE address of cache detection, due to
The principle of this device institute solve problem is similar to the method that aforementioned PCIE address of cache detects, the enforcement of therefore this device can be joined
See the enforcement of preceding method, repeat no more in place of repetition.
A kind of detection means of PCIE address of cache provided in an embodiment of the present invention, as shown in figure 5, specifically can include：
Writing module 501, for writing PTMP request message in the current PC IE address to target device；
Here, the current PC IE address of above-mentioned target device is the base address according to the local target device preserving for the device
Determine with current PC IE address offset, and in PTMP request message, carry current PC IE address offset and the test of device
Data；
Whether monitoring modular 502, have target device in the current PC IE address for monitoring device in Preset Time
The PTMP back message of write；
Here, the current PC IE address of said apparatus is deposited in the current PC IE address monitoring device for target device
After having PTMP request message, according to working as of the device carrying in the locally PCIE base address of the device of preservation and PTMP request message
Front PCIE address offset is determined, and carries target in the PTMP back message of write in the current PC IE address of device
The next PCIE address offset of equipment and response test data；
Determining module 503, has target device write in the current PC IE address that monitoring modular 502 monitors device
During PTMP back message, determine that whether the response test data carrying in PTMP back message carries with PTMP request message
Test data is identical, and when being defined as identical, determines that the current PC IE address of cache of target device and device is correct, by PTMP
The next PCIE address offset of the target device carrying in back message and the next PCIE address offset of device, respectively with
Default PCIE address offset is compared, and determines the next PCIE address of target device and device according to comparative result, will
It returns the write PTMP in the current PC IE address of target device respectively as the current PC IE address of target device and device
The step of request message, until determining the next PCIE address offset of the target device carrying in PTMP back message, and
Detection of end when the next PCIE address offset of device is default PCIE address offset.
Preferably, said apparatus, may also include：
Setup module 504, for when device is for source device, device being set to busy state；
Above-mentioned determining module 503, for, after device is set to busy state by setup module 504, determining target device
Whether it is in idle condition；
Above-mentioned writing module 501, specifically for when determining module 503 determines that target device is in idle condition, to
PTMP request message is write in the current PC IE address of target device.
Preferably, above-mentioned setup module 504, specifically for the data outside write setting data in the base address to device
Afterwards, determine that device is in busy state；
Above-mentioned determining module 503, during specifically for the data in the base address reading out target device for setting data,
Determine that target device is in idle condition.
Preferably, above-mentioned determining module 503, specifically for comparing the target device carrying in PTMP back message
Next PCIE address offset is not default PCIE address offset, and the next PCIE address offset of device is default PCIE ground
During the skew of location, the next PCIE ground of the target device carrying in the PCIE base address according to target device and PTMP back message
The next PCIE address of target device is determined in location skew；And the PCIE base address according to device and current PC IE address inclined
Move the next PCIE address determining device；The next PCIE of the target device carrying in comparing PTMP back message
Address offset is default PCIE address offset, and when the next PCIE address offset of device is not default PCIE address offset,
PCIE base address according to target device and current PC IE address offset determine the next PCIE address of target device；And
The next PCIE address of device is determined with next PCIE address offset in PCIE base address according to device；And comparing
The next PCIE address offset going out the target device carrying in PTMP back message is not default PCIE address offset, and device
Next PCIE address offset when not being default PCIE address offset, the PCIE base address according to target device and PTMP respond
The next PCIE address offset of the target device carrying in message determines the next PCIE address of target device；And root
Determine the next PCIE address of device according to the PCIE base address of device and next PCIE address offset.
Preferably, above-mentioned writing module 501, is additionally operable to not monitor device in Preset Time in monitoring modular 502
When having the PTMP back message that target device writes in current PC IE address, again in the current PC IE address of target device
Write PTMP request message；
Above-mentioned determining module 503, the number of times of PTMP request message being additionally operable to re-write in writing module 501 reaches
One set point number, and when monitoring modular 502 does not monitor PTMP back message yet, determine that the current PC IE address of target device is reflected
Penetrate mistake, and detection of end.
Preferably, above-mentioned writing module 501, is additionally operable to determine in determining module 503 and carries in PTMP back message
When test data in response test data, with PTMP request message differs, again to the current PC IE address of target device
Write PTMP request message；
Above-mentioned determining module 503, the number of times of PTMP request message being additionally operable to re-write in writing module 501 reaches
Two set point numbers, and determine the response test data carrying in PTMP back message, with the test number in PTMP request message
During according to still differing, determine the current PC IE address mapping error of device, and detection of end.
Preferably, said apparatus, also include：
Empty overlay module 505, for determining the response test data carrying in PTMP back message in determining module 503
After whether identical with the test data carrying in PTMP request message, data in the current PC IE address of emptying apparatus, or
Person, when monitoring modular 502 monitors the PTMP message having new write in this current PC IE address, covers last write
PTMP message.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (10)
1. a kind of method of quick external equipment interconnection PCIE address of cache detection is it is characterised in that include：
Source device writes point-to-multipoint PTMP request message in the current PC IE address of target device, the working as of described target device
Front PCIE address is that described source device is true according to the PCIE base address of the local target device preserving and current PC IE address offset
Make, in described PTMP request message, carry current PC IE address offset and the test data of active equipment；
If the PTMP having described target device write in the current PC IE address monitoring itself in Preset Time responds
Message is it is determined that whether the response test data that carries in described PTMP back message carries with described PTMP request message
Test data is identical, and the current PC IE address of described source device is described target device in the current PC IE address monitoring itself
In have described PTMP request message after, in the PCIE base address and described PTMP request message according to the local source device preserving
The current PC IE address offset of the source device carrying is determined, carries target device next in described PTMP back message
Individual PCIE address offset and response test data；
When being defined as identical, determine that the current PC IE address of cache of described target device and described source device is correct, and by institute
State next PCIE address offset and the next PCIE address offset of itself of the target device carrying in PTMP back message,
It is compared with default PCIE address offset respectively, described target device and the next one of itself are determined according to comparative result
PCIE address, using it as described target device and the current PC IE address of itself, returns working as to described target device
The step writing described PTMP request message in front PCIE address, until determining the target carrying in described PTMP back message
The next PCIE address offset of equipment, and when the next PCIE address offset of itself is described default PCIE address offset
Detection of end.
2. the method for claim 1 is it is characterised in that described source device is on the current PC IE ground to described target device
Before write PTMP request message in location, also include：
Itself is set to busy state, and determines whether described target device is in idle condition；
If so, write described PTMP request message in the current PC IE address of described target device.
3. method as claimed in claim 1 or 2 is it is characterised in that described source device determines described mesh by following manner
Marking device and the next PCIE address of itself：
If described source device compares the next PCIE address offset of the target device carrying in described PTMP back message
Be not default PCIE address offset, and the next PCIE address offset of itself is described default PCIE address offset, then basis
The next PCIE address of the target device carrying in the PCIE base address of described target device and described PTMP back message is inclined
Move the next PCIE address determining described target device；And the PCIE base address according to itself and current PC IE address inclined
Move and determine the next PCIE address of itself；
If described source device compares the next PCIE address offset of the target device carrying in described PTMP back message
For presetting PCIE address offset, and the next PCIE address offset of itself is not described default PCIE address offset, then basis
The PCIE base address of described target device and current PC IE address offset determine the next PCIE address of described target device；
And the PCIE base address according to itself and next PCIE address offset determine the next PCIE address of itself；
If described source device compares the next PCIE address offset of the target device carrying in described PTMP back message
It is not default PCIE address offset, and the next PCIE address offset of itself is not described default PCIE address offset, then root
Next PCIE address according to the target device carrying in the PCIE base address of described target device and described PTMP back message
The next PCIE address of described target device is determined in skew；And the PCIE base address according to itself and next PCIE ground
The next PCIE address of itself is determined in location skew.
4. method as claimed in claim 1 or 2 is it is characterised in that also include：
If source device does not monitor that in described Preset Time having described target device in the current PC IE address of itself writes
The PTMP back message entering, then write described PTMP request message again in the current PC IE address of described target device；
If the number of times of the PTMP request message that source device re-writes reach do not monitor yet during the first set point number described
PTMP back message, determines the current PC IE address mapping error of target device, and detection of end.
5. method as claimed in claim 4 is it is characterised in that also include：
If the response test data that source device carries in determining described PTMP back message, with described PTMP request message
In test data differ, then again to described target device current PC IE address write described PTMP request message；
If the number of times of the PTMP request message that source device re-writes reaches the second set point number, and determine that described PTMP returns
Answer the response test data carrying in message, still differ it is determined that source sets with the test data in described PTMP request message
Standby current PC IE address mapping error, and detection of end.
6. a kind of device of quick external equipment interconnection PCIE address of cache detection is it is characterised in that include：
Writing module, for writing point-to-multipoint PTMP request message, described target in the current PC IE address to target device
The current PC IE address of equipment is PCIE base address and the current PC IE address of the target device according to local preservation for the described device
Skew is determined, carries current PC IE address offset and the test data of described device in described PTMP request message；
Whether monitoring modular, for having described target device in the current PC IE address of monitoring described device in Preset Time
The PTMP back message of write, the current PC IE address of described device is that described target device is monitoring the current of described device
After having PTMP request message in PCIE address, the PCIE base address according to the local described device preserving and described PTMP ask
The current PC IE address offset of the described device carrying in message is determined, carries target and set in described PTMP back message
Standby next PCIE address offset and response test data；
Determining module, has described target device write in the current PC IE address of described monitoring module monitors to described device
PTMP back message when, determine whether the response test data that carries in described PTMP back message asks report with described PTMP
The test data carrying in literary composition is identical, and when being defined as identical, determines current PC IE of described target device and described device
Address of cache is correct, by the next PCIE address offset of the target device carrying in described PTMP back message and described device
Next PCIE address offset, be compared with default PCIE address offset respectively, described mesh determined according to comparative result
Marking device and the next PCIE address of described device, using it as current PC IE of described target device and described device
Address, returns the step writing described PTMP request message in the current PC IE address of described target device, until determining
The next PCIE address offset of the target device carrying in described PTMP back message, and the next PCIE ground of described device
Detection of end when location skew is described default PCIE address offset.
7. device as claimed in claim 6, it is characterised in that described device, also includes：
Setup module, for when described device is for source device, described device being set to busy state；
Determining module, is additionally operable to, after described device is set to busy state by described setup module, whether to determine target device
It is in idle condition；
Said write module, specifically for when described determining module determines that described target device is in idle condition, to institute
Described PTMP request message is write in the current PC IE address stating target device.
8. device as claimed in claims 6 or 7 is it is characterised in that described determining module, specifically for compare described
The next PCIE address offset of the target device carrying in PTMP back message is not default PCIE address offset, and described dress
The next PCIE address offset put be described default PCIE address offset when, the PCIE base address according to described target device and
The next PCIE address offset of the target device carrying in described PTMP back message determines next of described target device
Individual PCIE address；And the PCIE base address according to described device and current PC IE address offset determine next of described device
Individual PCIE address；The next PCIE address offset of the target device carrying in comparing described PTMP back message is default
PCIE address offset, and when the next PCIE address offset of described device is not described default PCIE address offset, according to institute
State the PCIE base address of target device and current PC IE address offset determines the next PCIE address of described target device；With
And the PCIE base address according to described device and next PCIE address offset determine the next PCIE address of described device；
And the next PCIE address offset of the target device carrying in comparing described PTMP back message is not default PCIE
Address offset, and when the next PCIE address offset of described device is not described default PCIE address offset, according to described mesh
The next PCIE address offset of the target device carrying in the PCIE base address of marking device and described PTMP back message determines
Go out the next PCIE address of described target device；And the PCIE base address according to described device is inclined with next PCIE address
Move the next PCIE address determining described device.
9. device as claimed in claims 6 or 7, it is characterised in that said write module, is additionally operable to exist in described monitoring modular
The PTMP having described target device write in the current PC IE address not monitoring described device in described Preset Time responds
During message, in the current PC IE address of described target device, again write described PTMP request message；
Described determining module, the number of times of PTMP request message being additionally operable to re-write in said write module reaches the first setting
Number of times, and when described monitoring modular does not monitor described PTMP back message yet, determine that the current PC IE address of target device is reflected
Penetrate mistake, and detection of end.
10. device as claimed in claim 9, it is characterised in that said write module, is additionally operable to determine in described determining module
Go out the response test data carrying in described PTMP back message, differ with the test data in described PTMP request message
When, again write described PTMP request message to the current PC IE address of described target device；
Described determining module, the number of times of PTMP request message being additionally operable to re-write in said write module reaches the second setting
Number of times, and determine the response test data carrying in described PTMP back message, with the test in described PTMP request message
When data still differs, determine the current PC IE address mapping error of described device, and detection of end.
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| CN101339810A (en) * | 2007-07-06 | 2009-01-07 | 群康科技(深圳)有限公司 | Shift register and LCD device using the same |
| CN102662808A (en) * | 2012-03-21 | 2012-09-12 | 北京星网锐捷网络技术有限公司 | Method and device for realizing hardware fault detection on PCIE (peripheral component interconnect express) |
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| CN101339810A (en) * | 2007-07-06 | 2009-01-07 | 群康科技(深圳)有限公司 | Shift register and LCD device using the same |
| CN102662808A (en) * | 2012-03-21 | 2012-09-12 | 北京星网锐捷网络技术有限公司 | Method and device for realizing hardware fault detection on PCIE (peripheral component interconnect express) |
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