CN103730496B - Semiconductor structure and manufacture method thereof - Google Patents
Semiconductor structure and manufacture method thereof Download PDFInfo
- Publication number
- CN103730496B CN103730496B CN201210388874.XA CN201210388874A CN103730496B CN 103730496 B CN103730496 B CN 103730496B CN 201210388874 A CN201210388874 A CN 201210388874A CN 103730496 B CN103730496 B CN 103730496B
- Authority
- CN
- China
- Prior art keywords
- conductive structure
- drain electrodes
- substrate
- source
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000009413 insulation Methods 0.000 claims description 45
- 230000004888 barrier function Effects 0.000 claims description 33
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 230000012447 hatching Effects 0.000 description 21
- 239000010410 layer Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 17
- 230000008569 process Effects 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of semiconductor structure and manufacture method thereof.Semiconductor structure includes a substrate, a gate dielectric, a grid structure, a source conductive structure, a Drain Electrodes Conductive structure and a gate conductive structure.Substrate has a channel region, and channel region has a length, and gate dielectric is formed on channel region, and grid structure is formed on gate dielectric.Source conductive structure and Drain Electrodes Conductive structure through grid structure and are electrically connected on substrate, and source conductive structure insulate with grid structure mutually with Drain Electrodes Conductive structure.Gate conductive structure is formed on grid structure.The distance being separated by between source conductive structure and Drain Electrodes Conductive structure and the length of channel region are identical.
Description
Technical field
The invention relates to a kind of semiconductor structure and manufacture method thereof, and in particular to a kind of semiconductor structure for logic process and manufacture method thereof.
Background technology
It is typically in typical semiconductor processes, first define active region (activeregion) and channel width (channelwidth), this stage i.e. shallow trench isolation (STI) technique, then in grid technology, define passage length (channellength), then define and make N-/P-region with this grid.Afterwards, assist to produce grid spacer (gatespacer) with the fluctuating of the structure of this grid, then assist definition N+/P+ region with this sept.Finally, after forming interlayer dielectric (interlayerdielectric, ILD) insulating barrier, contact hole must be aimed at when making contact hole (contact) technique this N+/P+ region and make.In typical process, STI/ grid/contact hole all follows the design specification the tightest with technique, and therefore process costs and difficulty are all at a relatively high.
Summary of the invention
The invention relates to a kind of semiconductor structure and manufacture method thereof, can be applicable to logic process and storage device.Drain Electrodes Conductive structure and source conductive structure is defined, consequently, it is possible to simplification is produced by the length of source conductive structure/Drain Electrodes Conductive structure and channel region in same module through grid structure.This not only simplifies originally complicated fabrication schedule, and the program of this simplification relaxes the design criteria of grid simultaneously, contributes to reducing manufacturing cost.Additionally, when formation grid structure completes in one-time process with definition active region scope, it is possible to reach the effect that integrated artistic simplifies.
According to an aspect of the present invention, it is propose a kind of semiconductor structure.Semiconductor structure includes a substrate, a gate dielectric, a grid structure, a source conductive structure, a Drain Electrodes Conductive structure and a gate conductive structure.Substrate has a channel region, and gate dielectric is formed on channel region, and grid structure is formed on gate dielectric.Source conductive structure and Drain Electrodes Conductive structure through grid structure and are electrically connected on substrate, and source conductive structure insulate with grid structure mutually with Drain Electrodes Conductive structure.Gate conductive structure is formed on grid structure.The distance being separated by between source conductive structure and Drain Electrodes Conductive structure is identical with a length of channel region.
According to a further aspect in the invention, it is the manufacture method proposing a kind of semiconductor structure.The manufacture method of semiconductor structure comprises the following steps: form a gate dielectric on a substrate；Form a grid structure on gate dielectric；Forming a source conductive structure and a Drain Electrodes Conductive structure on substrate, wherein source conductive structure through grid structure with Drain Electrodes Conductive structure and is electrically connected on substrate and insulate mutually with grid structure；And form a gate conductive structure on grid structure.Substrate has a channel region, and the distance being separated by between source conductive structure and Drain Electrodes Conductive structure is identical with a length of channel region.
In order to the above-mentioned and other aspect of the present invention being had understanding more preferably, special embodiment below, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Figure 1A is shown according to the schematic top plan view of the semiconductor structure of the first embodiment of the present invention.
Figure 1B illustrates the generalized section of the hatching 1B-1B ' along Figure 1A.
Fig. 2 A is shown according to the schematic top plan view of the semiconductor structure of the second embodiment of the present invention.
Fig. 2 B illustrates the generalized section of the hatching 2B-2B ' along Fig. 2 A.
Fig. 3 A is shown according to the schematic top plan view of the semiconductor structure of the third embodiment of the present invention.
Fig. 3 B illustrates the generalized section of the hatching 3B-3B ' along Fig. 3 A.
Fig. 3 C illustrates the electric lines of force schematic diagram between Drain Electrodes Conductive structure 130 as shown in Figure 3A and source conductive structure 140.
Fig. 4 is shown according to the schematic top plan view of the semiconductor structure of the fourth embodiment of the present invention.
Fig. 5 A is shown according to the schematic top plan view of the semiconductor structure of the fifth embodiment of the present invention.
Fig. 5 B illustrates the generalized section of the hatching 5B-5B ' along Fig. 5 A.
Fig. 6 A is shown according to the schematic top plan view of the semiconductor structure of the sixth embodiment of the present invention.
Fig. 6 B illustrates the generalized section of the hatching 6B-6B ' along Fig. 6 A.
Fig. 7 A to Fig. 7 C is shown according in the semiconductor structure of one embodiment of the invention grid structure, the schematic top plan view of the configuration of Drain Electrodes Conductive structure, source conductive structure and gate conductive structure.
Fig. 8 is shown according to the schematic top plan view of the semiconductor device of one embodiment of the invention.
Fig. 9 is shown according to the schematic top plan view of the semiconductor device of another embodiment of the present invention.
Figure 10 to Figure 17 B is shown according to the manufacture method schematic diagram of a kind of semiconductor structure of one embodiment of the invention.
Figure 18 to Figure 22 B is shown according to the manufacture method schematic diagram of a kind of semiconductor structure of another embodiment of the present invention.
[main element symbol description]
100,200,300,400,500,600a, 600b, 600c, 700a, 700b, 800a, 800b, 1300,2000: semiconductor structure
110,210: substrate
110a, 210a: surface
111,211,211 ', 311,511,1311: channel region
113: drain region
113a, 115a: the first type doped region
113b, 115b: Second-Type doped region
115: source area
120: grid structure
120a, 130a, 140a, 150a: sidewall
130: Drain Electrodes Conductive structure
140: source conductive structure
150: gate conductive structure
160: gate dielectric
170: insulating barrier
175: barrier layer
180: sept
190: insulation system
215: substrate bulk
217: silicon oxide layer
219: silicon layer
700,800: semiconductor device
A, A ': active region
1B-1B ', 2B-2B ', 3B-3B ', 5B-5B ', 6B-6B ', 12B-12B ', 13B-13B ', 14B-14B ', 15B-15B ', 16B-16B ', 17B-17B ', 19B-19B ', 20B-20B ', 21B-21B ', 21B-21B ': hatching
C1～C3: hole
D1～D8: distance
D11, D51, D61, D71, W1～W7, W2 ': width
EL: electric lines of force
L1～L8, L2 ': length
GND: earth terminal
ML: metal wire
PR1, PR2: photoresist
VCC、VDD:Running voltage input
VIn:Voltage input end
Vout: voltage output end
Detailed description of the invention
In the embodiment of present invention, it is propose a kind of semiconductor structure and manufacture method thereof.With the length of definition channel region separated by a distance between Drain Electrodes Conductive structure and the source conductive structure of semiconductor structure, and, form grid structure and complete in one-time process with definition active region scope, it is possible to reach the effect that integrated artistic simplifies.But, thin portion structure that embodiment is proposed and processing step use by way of example only, the scope that the present invention is not intended to protection does limit.Those steps use by way of example only, and it is not used to the limit present invention.Tool usually intellectual when can according to reality implement aspect need those steps are modified or are changed.
Figure 1A is shown according to the schematic top plan view of the semiconductor structure of the first embodiment of the present invention.Figure 1B illustrates the generalized section of the hatching 1B-1B ' along Figure 1A.Refer to Figure 1A to Figure 1B.Semiconductor structure 100 include substrate 110, gate dielectric 160, grid structure 120, Drain Electrodes Conductive structure 130, source conductive structure 140, with gate conductive structure 150.Substrate 110 has channel region 111, and channel region 111 has length L1.Gate dielectric 160 is formed on channel region 111, and grid structure 120 is formed on gate dielectric 160.Drain Electrodes Conductive structure 130 and source conductive structure 140 are formed on substrate 110, Drain Electrodes Conductive structure 130 and source conductive structure 140 are tied 120 structures through grid and are electrically connected on substrate 110, and Drain Electrodes Conductive structure 130 insulate with grid structure 120 mutually with source conductive structure 140.Gate conductive structure 150 is formed on grid structure 120.Between Drain Electrodes Conductive structure 130 and source conductive structure 140, D1 separated by a distance is identical with the length L1 of channel region 111.It is to say, D1 separated by a distance defines the length L1 of channel region 111 between Drain Electrodes Conductive structure 130 and source conductive structure 140.
Generally traditional mode, it is that first defining passage with shallow trench isolation (STI) goes out the width (channelwidth) of element, define pass element length (channellength) with grid technology again, then make drain electrode and source electrode again with gold-tinted/ion implanting mode/clearance wall (spacer) technique.Finally, then form interlayer dielectric layer material (ILD), and carry out contact hole technique.The present invention defines the length L1 of channel region 111 with D1 separated by a distance between Drain Electrodes Conductive structure 130 and source conductive structure 140, thus, it is possible to the length L1 of definition Drain Electrodes Conductive structure 130 and source conductive structure 140 and control channel region 111 simultaneously.
In embodiment, as shown in Figure 1A, on bigger grid structure 120, Drain Electrodes Conductive structure 130 and source conductive structure 140 is defined through grid structure 120, therefore, can defining N-/P-region in the technique making contact hole (Drain Electrodes Conductive structure 130/ source conductive structure 140), after then forming sept 180, autoregistration again (self-aligned) defines N+/P+ region and contact hole simultaneously.Consequently, it is possible to simplification is produced by the length L1 of Drain Electrodes Conductive structure 130, source conductive structure 140 and channel region 111 in same module.This not only simplifies originally complicated fabrication schedule, and the technique of this simplification relaxes the design criteria of grid simultaneously, contributes to reducing manufacturing cost.
In embodiment, as shown in Figure 1A to Figure 1B, grid structure 120 is positioned at Drain Electrodes Conductive structure 130 and the same side of source conductive structure 140.Semiconductor structure 100 can include insulation system 190.Insulation system 190 is formed on substrate 110, and insulation system 190 is around substrate 110 and the part surface exposing substrate 110.In embodiment, as shown in Figure 1A, the width W1 of channel region 111 is exposed to the width D 11 of the part surface of insulation system 190 equal to substrate 110.In other words, the width W1 of the scope definition channel region 111 that insulation system 190 surrounds.
As shown in Figure 1A to Figure 1B, in embodiment, semiconductor structure 100 can include insulating barrier 170.Insulating barrier 170 is formed on substrate 110, and between gate conductive structure 150, Drain Electrodes Conductive structure 130 and source conductive structure 140.In one embodiment, as shown in Figure 1A to Figure 1B, insulating barrier 170 all around gate conductive structure 150, Drain Electrodes Conductive structure 130 and source conductive structure 140 are around.
As shown in Figure 1A to Figure 1B, in embodiment, semiconductor structure 100 can include sept (spacer) 180.Sept 180 is formed on the sidewall 130a of Drain Electrodes Conductive the structure 130 and sidewall 140a of source conductive structure 140.In embodiment, sept 180 is also formed on the sidewall 150a of gate conductive structure 150.In one embodiment, as shown in Figure 1A, sept 180 all around gate conductive structure 150, Drain Electrodes Conductive structure 130 and source conductive structure 140 are around.The material of sept 180 is insulant, for instance include silicon nitride or silicon oxide.
In embodiment, as shown in Figure 1B, sept 180 is such as formed between grid structure 120 and Drain Electrodes Conductive structure 130, with between grid structure 120 and source conductive structure 140.
In one embodiment, as shown in Figure 1B, sept 180 is such as directly contact grid structure 120, Drain Electrodes Conductive structure 130 and source conductive structure 140.In embodiment, sept 180 is such as the sidewall 140a of sidewall 130a and the source conductive structure 140 that Drain Electrodes Conductive structure 130 is completely covered, the sidewall 130a of sept 180 and Drain Electrodes Conductive the structure 130 and sidewall 140a conformal (conformal) of source conductive structure 140.In embodiment, as shown in Figure 1B, with only spaced apart with sept 180 with grid structure 120 and source conductive structure 140 between grid structure 120 and Drain Electrodes Conductive structure 130, sept 180 is possible to prevent the electrical interference between grid structure 120 and Drain Electrodes Conductive structure 130 and source conductive structure 140.
In one embodiment, as shown in Figure 1A, the cross sectional shape of gate conductive structure 150, Drain Electrodes Conductive structure 130 and source conductive structure 140 is such as rectangle.In embodiment, the cross sectional shape of gate conductive structure 150, source conductive structure 130 and Drain Electrodes Conductive structure 140 is rectangle, and the length in Drain Electrodes Conductive structure 130 and the source conductive structure 140 width W1 direction that is parallel to channel region 111 is such as greater than or equal to the width D 11 that substrate 110 is exposed to the part surface of insulation system 190.The width W1 of channel region 111 is determined by width D 11, and the length L1 of channel region 111 is determined by contact hole (Drain Electrodes Conductive structure 130/ source conductive structure 140) technique.The width W1 of channel region 111 and length L1 all explicitly defines, and semiconductor structure 100 as shown in Figure 1A has the characteristic curve similar to the semiconductor structure made with typical process.In embodiment, those cross sectional shapes can also be oval, line style or other shapes.During right practical application, those cross sectional shapes are also looked application feature and are made suitably to select, and are not shaped as limit with aforementioned.In one embodiment, as shown in Figure 1B, substrate 110 is such as multicrystalline silicon substrate.
As shown in Figure 1B, in an embodiment, semiconductor structure 100 can include drain region 113 and source area 115.Drain region 113 and source area 115 are formed in substrate 110, and drain region 113 is adjacent to Drain Electrodes Conductive structure 130, and source area 115 is adjacent to source conductive structure 140.In embodiment, drain region 113 and source area 115 can respectively include one first type doped region 113a, 115a and Second-Type doped region 113b, a 115b respectively.First type doped region 113a, 115a lays respectively under Drain Electrodes Conductive structure 130 and source conductive structure 140, first type doped region 113a, 115a is such as N-/P-doped region, and its regional extent is determined by the periphery (before namely not forming sept 180, being intended to form Drain Electrodes Conductive structure 130 and source conductive structure 140 in hole scope therein) of sept 180.Second-Type doped region 113b, 115b lay respectively between Drain Electrodes Conductive structure 130 and the first type doped region 113a and between source conductive structure 140 and the first type doped region 115a, Second-Type doped region 113b, 115b are such as N+/P+ doped regions, and its regional extent is determined by sept 180 inner edge (namely the scope of Drain Electrodes Conductive structure 130 and source conductive structure 140).
Fig. 2 A is shown according to the schematic top plan view of the semiconductor structure of the second embodiment of the present invention.Fig. 2 B illustrates the generalized section of the hatching 2B-2B ' along Fig. 2 A.In one embodiment, as shown in Figure 2 A, gate conductive structure 150 is such as arranged between Drain Electrodes Conductive structure 130 and source conductive structure 140.In one embodiment, as shown in Figure 2 A, the cross sectional shape of the gate conductive structure 150 of semiconductor structure 200, source conductive structure 130 and Drain Electrodes Conductive structure 140 is such as rectangle.Embodiment as shown in aforementioned Figure 1A, in semiconductor structure 200, width and the length of channel region 211 all explicitly define, and semiconductor structure 200 as shown in Figure 2 A has the characteristic curve similar to the semiconductor structure made with typical process.In embodiment, those cross sectional shapes can also be oval, line style or other shapes.During right practical application, those cross sectional shapes are also looked application feature and are made suitably to select, and are not shaped as limit with aforementioned.
In embodiment, as shown in Fig. 2 A to Fig. 2 B, between Drain Electrodes Conductive structure 130 and source conductive structure 140, D2 separated by a distance is identical with the length L2 of channel region 211.It is to say, D2 separated by a distance defines the length L2 of channel region 211 between Drain Electrodes Conductive structure 130 and source conductive structure 140.
In one embodiment, as shown in Fig. 2 A to Fig. 2 B, semiconductor structure 200 is such as metal-oxide semiconductor (MOS) (metaloxidesemiconductor, MOS), and the region that grid structure 120 is contained can as active region (activeregion) A.In other words, the active region A of the scope definition semiconductor structure 200 of grid structure 120.
Refer to Fig. 2 B, in an embodiment, substrate 210 is such as silicon-on-insulator (silicononinsulator, SOI) substrate, including substrate bulk 215, silicon oxide layer 217 and silicon layer 219.During right practical application, substrate is also looked application feature and is made suitably to select, and is not limited with aforementioned type.
Fig. 3 A is shown according to the schematic top plan view of the semiconductor structure of the third embodiment of the present invention.Fig. 3 B illustrates the generalized section of the hatching 3B-3B ' along Fig. 3 A.In one embodiment, as shown in Figure 3A, the cross sectional shape of the gate conductive structure 150 of semiconductor structure 300, Drain Electrodes Conductive structure 130 and source conductive structure 140 is such as circular.
Fig. 3 C illustrates the electric lines of force schematic diagram between Drain Electrodes Conductive structure 130 as shown in Figure 3A and source conductive structure 140.When the cross sectional shape of Drain Electrodes Conductive structure 130 and source conductive structure 140 is circle, the length L2 ' and width W2 ' of channel region 211 ' define less clear.As shown in Figure 3 C, electric lines of force EL, being straight line near Drain Electrodes Conductive structure 130 and source conductive structure 140 mid portion, is then curve toward both sides, and the more past both sides away from Drain Electrodes Conductive structure 130 and source conductive structure 140 is more toward outside sweep.Under this kind of situation, the characteristic curve that semiconductor structure 300 as shown in Figure 3 C has can be different with the characteristic curve of the semiconductor structure made with typical process.To a certain degree, the characteristic curve that semiconductor structure 300 has can be similar to the produced characteristic curve that is formed in parallel by multiple semiconductor structures different from width for the length of channel region.Therefore, the characteristic curve that semiconductor structure 300 has should be more more complicated than the characteristic curve of the semiconductor structure made with typical process.Although having more complicated characteristic curve, semiconductor structure 300 has Simplified flowsheet and the advantage of manufacturing cost reduction, and after fine qualitative (characterization) processes, semiconductor structure 300 is equally applicable in the logic process being suitable for.
Fig. 4 is shown according to the schematic top plan view of the semiconductor structure of the fourth embodiment of the present invention.Refer to Fig. 4, in an embodiment, gate conductive structure 150 is not placed between Drain Electrodes Conductive structure 130 and source conductive structure 140, and gate conductive structure 150 is such as disposed on Drain Electrodes Conductive structure 130 and the same side of source conductive structure 140.As shown in Figure 4, Drain Electrodes Conductive structure 130 is such as arranged between gate conductive structure 150 and source conductive structure 140.In embodiment, channel region 311 is arranged in silicon layer 219.Between Drain Electrodes Conductive structure 130 and source conductive structure 140, D3 separated by a distance is identical with the length L3 of channel region 311.It is to say, D3 separated by a distance defines the length L3 of channel region 311 between Drain Electrodes Conductive structure 130 and source conductive structure 140.
Fig. 5 A is shown according to the schematic top plan view of the semiconductor structure of the fifth embodiment of the present invention.Fig. 5 B illustrates the generalized section of the hatching 5B-5B ' along Fig. 5 A.Refer to Fig. 5 A to Fig. 5 B, in an embodiment, semiconductor structure 400 can include insulation system 190.Insulation system 190 is formed on substrate 110, and all around gate structure 120.In embodiment, insulation system 190 and insulating barrier 170 can be formed in different technique, and having different materials, insulation system 190 and insulating barrier 170 can also be formed in same technique and have identical material.In one embodiment, semiconductor structure 400 is such as metal-oxide semiconductor (MOS), and the region that insulation system 190 surrounds can as active region A '.In other words, insulation system 190 defines the active region A ' of semiconductor structure 400.In one embodiment, it is such as (conformal) conformal with the surrounding of grid structure 120 that insulation system 190 is adjacent to the side around grid structure 120.
Fig. 6 A is shown according to the schematic top plan view of the semiconductor structure of the sixth embodiment of the present invention.Fig. 6 B illustrates the generalized section of the hatching 6B-6B ' along Fig. 6 A.Refer to Fig. 6 A to Fig. 6 B, in an embodiment, Drain Electrodes Conductive structure 130 and source conductive structure 140 are arranged on the both sides of grid structure 120, are adjacent to insulation system 190 and arrange.In embodiment, as shown in Fig. 6 A to Fig. 6 B, sept 180 is such as formed between insulation system 190 and Drain Electrodes Conductive structure 130, and between insulation system 190 and source conductive structure 140.Sept 180 is such as directly contact insulation system 190, Drain Electrodes Conductive structure 130 and source conductive structure 140.In embodiment, channel region 511 is arranged in silicon layer 219.Between Drain Electrodes Conductive structure 130 and source conductive structure 140, D4 separated by a distance is identical with the length L4 of channel region 511.It is to say, D4 separated by a distance defines the length L4 of channel region 511 between Drain Electrodes Conductive structure 130 and source conductive structure 140.
In embodiment, as shown in Figure 6A, the channel region 511 of semiconductor structure 500 is positioned under grid structure 120, and the width W4 of the width of grid structure 120 and channel region 511 is identical.It is to say, the width W4 of the width definition channel region 511 of grid structure 120.
Fig. 7 A to Fig. 7 C is shown according in the semiconductor structure of one embodiment of the invention grid structure, the schematic top plan view of the configuration of Drain Electrodes Conductive structure, source conductive structure and gate conductive structure.
In one embodiment, as shown in Figure 7 A, the channel region of semiconductor structure 600a is positioned under grid structure 120, and between Drain Electrodes Conductive structure 130 and source conductive structure 140, D5 separated by a distance is identical with the length L5 of channel region.Insulation system 190 is adjacent to the side around grid structure 120 and all around gate structure 120 around, and the width D 51 of grid structure 120 is identical with the width W5 of channel region.In other words, between Drain Electrodes Conductive structure 130 and source conductive structure 140, D5 separated by a distance defines the length L5 of channel region, and insulation system 190 defines the width W5 of channel region.
In one embodiment, as shown in Figure 7 B, the channel region of semiconductor structure 600b is positioned under grid structure 120, and between Drain Electrodes Conductive structure 130 and source conductive structure 140, D6 separated by a distance is identical with the length L6 of channel region.The width W6 of channel region and Drain Electrodes Conductive structure 130 and source conductive structure 140 are perpendicular to the width D 61 in the length L6 direction of channel region for identical.In other words, between Drain Electrodes Conductive structure 130 and source conductive structure 140, D6 separated by a distance defines the length L6 of channel region, and the width D 61 of Drain Electrodes Conductive structure 130 and source conductive structure 140 defines the width W5 of channel region.
In one embodiment, as seen in figure 7 c, the channel region of semiconductor structure 600c is positioned under grid structure 120, and between Drain Electrodes Conductive structure 130 and source conductive structure 140, D7 separated by a distance is identical with the length L7 of channel region.It is noted that the scope of the length L7 Yu grid structure 120 in order to explicitly indicate that channel region, the grid structure 120 in Fig. 7 C is to indicate with oblique line.It is identical that Drain Electrodes Conductive structure 130 and source conductive structure 140 are overlapped in the width D 71 of the grid structure 120 of part with the width W7 of channel region.In other words, between Drain Electrodes Conductive structure 130 and source conductive structure 140, D7 separated by a distance defines the length L7 of channel region, and Drain Electrodes Conductive structure 130 and source conductive structure 140 are overlapped in the width D 71 of grid structure 120 of part and define the width W5 of channel region.
Fig. 8 is shown according to the schematic top plan view of the semiconductor device of one embodiment of the invention.Fig. 9 is shown according to the schematic top plan view of the semiconductor device of another embodiment of the present invention.Refer to Fig. 8, semiconductor device 700 includes two semiconductor structure 700a and 700b being disposed adjacent, and 130, two source conductive structure 140 of two Drain Electrodes Conductive structures in two semiconductor structures 700a, 700b and two gate conductive structure 150 are electrical connected with many metal line ML.Semiconductor structure 700a and 700b is spaced apart with insulation system 190, it is possible to avoid electrical interference each other.As shown in Figure 8, the metal wire ML connecting source conductive structure 140 has a voltage input end VIn,The metal wire ML connecting Drain Electrodes Conductive structure 130 has a voltage output end Vout, voltage input end VinWith voltage output end VoutIt is arranged on insulation system 190 place between two semiconductor structures 700a, 700b.Gate conductive structure 150 in two semiconductor structures 700a, 700b is respectively connecting to running voltage input VCCAnd earth terminal GND.
As it is shown in figure 9, in semiconductor device 800a and 800b, the metal wire ML connecting source conductive structure 140 has a voltage input end Vin, the metal wire ML connecting Drain Electrodes Conductive structure 130 has a voltage output end Vout, voltage input end VinWith voltage output end VoutIt is separately positioned on the both sides of two semiconductor structure 800a and 800b.Gate conductive structure 150 in two semiconductor structures 800a, 800b is respectively connecting to running voltage input VDDAnd earth terminal GND.
In one embodiment, semiconductor structure 700a/800a and semiconductor structure 700b/800b is such as N-type metal-oxide semiconductor (MOS) (ntypemetaloxidesemiconductor respectively, and P-type mos (ptypemetaloxidesemiconductor NMOS), PMOS), semiconductor device 700/800 is such as phase inverter (inverter), can be applicable to static random access memory (staticrandomaccessmemory, SRAM).
The following is the manufacture method of a kind of semiconductor structure proposing embodiment, so those steps use by way of example only, and be not used to the limit present invention.Tool usually intellectual when can according to reality implement aspect need those steps are modified or are changed.
Figure 10 to Figure 17 B is shown according to the manufacture method schematic diagram of a kind of semiconductor structure of one embodiment of the invention.Refer to Figure 10, it is provided that substrate 210.In embodiment, substrate 210 is such as silicon-on-insulator substrate, including substrate bulk 215, silicon oxide layer 217 and silicon layer 219.During right practical application, substrate is also looked application feature and is made suitably to select, and is not limited with aforementioned type.
Refer to Figure 11, form gate dielectric 160 on substrate 210, form grid structure 120 on gate dielectric 160.In embodiment, for instance be form grid structure 120 with a light shield etching technics.Then, forming insulating barrier 170 on substrate 210, in embodiment, insulating barrier 170 is formed on grid structure 120.In embodiment, the material of gate dielectric 160 and insulating barrier 170 is such as silicon oxide, and the material of grid structure 120 is such as polysilicon, and during right practical application, above-mentioned material is looked application feature and made suitably to select, and is not limited with aforementioned type.
Then, refer to Figure 12 A to Figure 15 B, form source conductive structure 140 and Drain Electrodes Conductive structure 130 on substrate 210, wherein Drain Electrodes Conductive structure 130 through grid structure 120 with source conductive structure 140 and is electrically connected on substrate 110 and insulate mutually with grid structure 120, and forms gate conductive structure 150 on grid structure 120.
In embodiment, the manufacture method forming source conductive structure 140, Drain Electrodes Conductive structure 130 and gate conductive structure 150 such as comprises the following steps.As shown in Figure 12 A to Figure 12 B the generalized section of the hatching 12B-12B ' along Figure 12 A (Figure 12 B illustrate), form hole C1, C2 and C3 in insulating barrier 170, hole C1, C2 and C3 height extend to the interface of insulating barrier 170 and grid structure 120 from the upper surface of insulating barrier 170.In embodiment, for instance be form hole C1, C2 and C3 with etching mode.Then, as shown in Figure 13 A to Figure 13 B the generalized section of the hatching 13B-13B ' along Figure 13 A (Figure 13 B illustrate), photoresist PR1 is set on hole C2, and etching the grid structure 120 below hole C1 and C3 and gate dielectric 160 so that hole C1 and C3 highly extends to gate dielectric 160 and the interface of substrate 210.In one embodiment, as shown in Figure 13 B, hole C1 and C3 may extend in silicon layer 219.
Then, as shown in Figure 14 A to Figure 14 B the generalized section of the hatching 14B-14B ' along Figure 14 A (Figure 14 B illustrate), formed sept 180 in hole C1, C2 and C3 sidewall on.In embodiment, as shown in Figure 14 A to Figure 14 B, sept 180 is completely covered the sidewall of hole C1, C2 and C3.Then, as shown in Figure 15 A to Figure 15 B the generalized section of the hatching 15B-15B ' along Figure 15 A (Figure 15 B illustrate), insert conductive material in hole C1, C2 and C3, to form Drain Electrodes Conductive structure 130, gate conductive structure 150 and source conductive structure 140 respectively in hole C1, C2 and C3.Consequently, it is possible to Drain Electrodes Conductive structure 130 and source conductive structure 140 are through grid structure 120, and insulate with grid structure 120 phase with sept 180.In embodiment, the material of sept 180 is such as silicon nitride, and conductive material is such as tungsten metal, and during right practical application, above-mentioned material is looked application feature and made suitably to select, and is not limited with aforementioned type.So far, semiconductor structure 1300 is formed.
In one embodiment, as shown in Figure 15 A to Figure 15 B, semiconductor structure 1300 is such as metal-oxide semiconductor (MOS), the active region A of the scope definition semiconductor structure 1300 of grid structure 120.The step forming grid structure 120 of the present invention and the step defining active region A scope just can complete in one-time process, thus, do not need to arrange insulation isolation structure still further to form grid after defining active region, source contact (sourcecontact), drain contact (draincontact) and gate contact (gatecontact) could be formed also without arranging insulation isolation structure, therefore can reach the effect that integrated artistic simplifies, and improve the elasticity of integrated artistic.
In embodiment, as shown in Figure 15 A to Figure 15 B, substrate 210 has channel region 1311, and between source conductive structure 140 and Drain Electrodes Conductive structure 130, D8 separated by a distance is identical with the length L8 of channel region 1311.In embodiment, sept 180 is positioned on the sidewall 140a of the source conductive structure 140 and sidewall 130a of Drain Electrodes Conductive structure 130.In embodiment, sept 180 is formed between grid structure 120 and source conductive structure 140 with between grid structure 120 and Drain Electrodes Conductive structure 130, and sept 180 is completely covered the sidewall 140a of the source conductive structure 140 and sidewall 130a of Drain Electrodes Conductive structure 130.
In embodiment, as shown in Figure 15 A to Figure 15 B, after Drain Electrodes Conductive structure 130, gate conductive structure 150 and source conductive structure 140 are formed, insulating barrier 170 is between gate conductive structure 150, source conductive structure 140 and Drain Electrodes Conductive structure 130.
Then, refer to Figure 16 A to Figure 17 B, form insulation system 190 on substrate 210, and insulation system 190 all around gate structure 120.The manufacture method forming insulation system 190 such as comprises the following steps.As shown in Figure 16 A to Figure 16 B the generalized section of the hatching 16B-16B ' along Figure 16 A (Figure 16 B illustrate), etching grid structure 120 and substrate 210 are to expose the surface 210a of substrate 210.In embodiment, it is such as that photoresist PR2 is set on Drain Electrodes Conductive structure 130, gate conductive structure 150 and source conductive structure 140, then etch the insulating barrier 170, grid structure 120, gate dielectric 160, silicon layer 215 and the silicon oxide layer 217 that are not photo-etched glue PR2 and cover, and the surface 210a exposed is the some of silicon oxide layer 217.The region arranging photoresist PR2 is namely predefined for the region of active region.Then, as shown in Figure 17 A to Figure 17 B the generalized section of the hatching 17B-17B ' along Figure 17 A (Figure 17 B illustrate), insulation system 190 is formed on the surface 210a of substrate 210.In embodiment, insulation system 190 and insulating barrier 170 can have identical material or unlike material, and the region that insulation system 190 surrounds can as active region A '.So far, the semiconductor structure 400 as shown in Fig. 5 A to Fig. 5 B is formed.
Figure 18 to Figure 22 B is shown according to the manufacture method schematic diagram of a kind of semiconductor structure of another embodiment of the present invention.Referring to Figure 12 A to Figure 15 B and Figure 18 to Figure 22 B.
Refer to Figure 18, form gate dielectric 160 on substrate 110, form grid structure 120 on gate dielectric 160.Then, form insulating barrier 170 on grid structure 120, and form barrier layer 175 on insulating barrier 170.In embodiment, substrate 110 is such as the multicrystalline silicon substrate of the p-well region (Pwell) with ion implanting, and the material of barrier layer 175 is such as silicon nitride, and during right practical application, above-mentioned material is looked application feature and made suitably to select, and is not limited with aforementioned type.
Then, refer to Figure 19 A to Figure 20 B, form insulation system 190 on substrate 110, and insulation system 190 all around gate structure 120.The manufacture method forming insulation system 190 such as comprises the following steps.As shown in Figure 19 A to Figure 19 B the generalized section of the hatching 19B-19B ' along Figure 19 A (Figure 19 B illustrate), etching grid structure 120 and substrate 110 are to expose the surface 110a of substrate 110.In embodiment, it is such as that photoresist PR2 is set on the part surface of barrier layer 175, then etch the barrier layer 175, insulating barrier 170, grid structure 120, gate dielectric 160 and the substrate 110 that are not photo-etched glue PR2 and cover, and expose the surface 110a of substrate 110.The region arranging photoresist PR2 is namely predefined for the region of active region.Then, as shown in Figure 20 A to Figure 20 B the generalized section of the hatching 20B-20B ' along Figure 20 A (Figure 20 B illustrate), insulation system 190 is formed on the surface 110a of substrate 110.Afterwards, it is possible to remove photoresist PR2 and barrier layer 175, and planarize insulation system 190 and the integral surface of insulating barrier 170 in such as chemically mechanical polishing (chemicalmechanicalpolishing, CMP) mode.In embodiment, insulation system 190 and insulating barrier 170 can have identical material or unlike material, and the region that insulation system 190 surrounds can as predetermined active region.
Then, refer to Figure 21 A to Figure 22 B, form source area 115 and drain region 113 in substrate 110.
In embodiment, form source area 115 and the drain region 113 manufacture method in substrate 110 such as comprises the following steps.As shown in Figure 12 A to Figure 13 B and Figure 21 A to Figure 21 B the generalized section of the hatching 21B-21B ' along Figure 21 A (Figure 21 B illustrate), form hole C1, C2 and C3 in insulating barrier 170, the height of hole C2 extends to the interface of insulating barrier 170 and grid structure 120 from the upper surface of insulating barrier 170, and hole C1 and C3 highly extends to gate dielectric 160 and the interface of substrate 110.Then, respectively the substrate 110 below hole C1 and C3 is carried out ion implanting to form first type doped region 113a, 115a.The regional extent of first type doped region 113a, 115a is determined by the scope of hole C1 and C3.Then, as shown in Figure 22 A to Figure 22 B the generalized section of the hatching 22B-22B ' along Figure 22 A (Figure 22 B illustrate), formed sept 180 in hole C1, C2 and C3 sidewall on, and respectively the substrate 110 below hole C1 and C3 is carried out ion implanting to form Second-Type doped region 113b, 115b.The regional extent of Second-Type doped region 113b, 115b is determined by sept 180 inner edge.In embodiment, the first type doped region 113a and Second-Type doped region 113b below hole C1 form drain region 113, and the first type doped region 115a and Second-Type doped region 115b below hole C3 form source area 115.In embodiment, the width range of drain region 113 and source area 115 width less than hole C1 and hole C3 respectively.
Then, refer to Figure 22 A to Figure 22 B, form source conductive structure 140 and Drain Electrodes Conductive structure 130 on substrate 110, and form gate conductive structure 150 on grid structure 120.Source area 115 is adjacent to source conductive structure 140, and drain region 113 is adjacent to Drain Electrodes Conductive structure 130.
In embodiment, the manufacture method forming source conductive structure 140, Drain Electrodes Conductive structure 130 and gate conductive structure 150 such as comprises the following steps.As shown in Figure 14 A to Figure 15 B and Figure 22 A to Figure 22 B, insert conductive material in hole C1, C2 and C3, to form Drain Electrodes Conductive structure 130, gate conductive structure 150 and source conductive structure 140 respectively in hole C1, C2 and C3.Drain Electrodes Conductive structure 130 and source conductive structure 140 are through grid structure 120, and insulate with grid structure 120 phase with sept 180.So far, semiconductor structure 2000 is formed.
In one embodiment, as shown in Figure 22 A to Figure 22 B, semiconductor structure 2000 is such as metal-oxide semiconductor (MOS), and insulation system 190 defines the active region A ' of semiconductor structure 2000.The step of the etching grid structure 120 of the present invention and etched substrate 110 just can complete in one-time process with the step defining active region A ' scope, thus, do not need first to arrange insulation isolation structure still further to form grid after defining active region, source contact, drain contact and gate contact could be formed also without arranging insulation isolation structure, therefore can reach the effect that integrated artistic simplifies, and improve the elasticity of integrated artistic.
Additionally, compared to, in traditional mode, first making in ion implanting mode after drain electrode and source electrode, just form interlayer dielectric layer material and carry out contact hole technique；Relatively, in the embodiment of the present invention, after forming insulating barrier 170 (interlayer dielectric layer material) and forming hole C1, C2 and C3 (contact hole technique), just form source area 115 and drain region 113.Thus, processing step (being such as heat treatment step) after ion implantation technology reduces, the scope (namely the scope of source area 115 and drain region 113) making ion implanting is subject to the impact of subsequent technique and reduces, and can accurately control the scope of source area 115 and drain region 113, and then optimize the usefulness of semiconductor structure 2000.
In sum, although the present invention is disclosed above with embodiment, and so it is not limited to the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when depending on being as the criterion that appended claims scope defines.
Claims (10)
1. a semiconductor structure, including:
One substrate, has a channel region；
One gate dielectric, is formed on this channel region；
One grid structure, is formed on this gate dielectric；
One source conductive structure and a Drain Electrodes Conductive structure, this grid structure of traverse is also electrically connected on this substrate, this source conductive structure insulate with this grid structure mutually with this Drain Electrodes Conductive structure, and this source conductive structure and this Drain Electrodes Conductive structure are surrounded by this grid structure；And
One gate conductive structure, is formed on this grid structure；
The distance being wherein separated by between this source conductive structure and this Drain Electrodes Conductive structure is identical with a length of this channel region.
2. semiconductor structure according to claim 1, more includes a sept (spacer), is formed on a sidewall of this source conductive structure and a sidewall of this Drain Electrodes Conductive structure.
3. semiconductor structure according to claim 1, more includes an insulation system, is formed on this substrate, and around this grid structure.
4. semiconductor structure according to claim 1, more includes an insulation system, is formed on this substrate, and this insulation system is around this substrate and a part of surface exposing this substrate.
5. semiconductor structure according to claim 1, wherein this gate conductive structure is arranged at the same side of this Drain Electrodes Conductive structure and this source conductive structure.
6. a manufacture method for semiconductor structure, including:
Form a gate dielectric on a substrate；
Form a grid structure on this gate dielectric；
Form a source conductive structure and a Drain Electrodes Conductive structure on this substrate, wherein this source conductive structure through this grid structure with this Drain Electrodes Conductive structure and is electrically connected on this substrate and insulate mutually with this grid structure, and this source conductive structure and this Drain Electrodes Conductive structure are surrounded by this grid structure；And
Form a gate conductive structure on this grid structure；
Wherein this substrate has a channel region, and the distance being separated by between this source conductive structure and this Drain Electrodes Conductive structure is identical with a length of this channel region.
7. the manufacture method of semiconductor structure according to claim 6, more includes:
Form a sept on a sidewall of this source conductive structure and a sidewall of this Drain Electrodes Conductive structure.
8. the manufacture method of semiconductor structure according to claim 6, more includes:
Form an insulating barrier on this substrate, and this insulating barrier is between this gate conductive structure, this source conductive structure and this Drain Electrodes Conductive structure.
9. the manufacture method of semiconductor structure according to claim 6, more includes:
Form an insulation system on this substrate, and this insulation system is around this grid structure.
10. the manufacture method of semiconductor structure according to claim 6, more includes:
Forming source region and a drain region in this substrate, wherein this source area is adjacent to this source conductive structure, and this drain region is adjacent to this Drain Electrodes Conductive structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210388874.XA CN103730496B (en) | 2012-10-15 | 2012-10-15 | Semiconductor structure and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210388874.XA CN103730496B (en) | 2012-10-15 | 2012-10-15 | Semiconductor structure and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103730496A CN103730496A (en) | 2014-04-16 |
| CN103730496B true CN103730496B (en) | 2016-07-13 |
Family
ID=50454509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210388874.XA Active CN103730496B (en) | 2012-10-15 | 2012-10-15 | Semiconductor structure and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103730496B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735710B (en) * | 2017-04-14 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Anti-fuse structure circuit and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518133B1 (en) * | 2002-04-24 | 2003-02-11 | Chartered Semiconductor Manufacturing Ltd | Method for fabricating a small dimensional gate with elevated source/drain structures |
| TW200531282A (en) * | 2004-01-09 | 2005-09-16 | Elpida Memory Inc | Method for Manufacturing a semiconductor device having a low junction leakage current |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100702029B1 (en) * | 2005-09-22 | 2007-03-30 | 삼성전자주식회사 | Non-volatile memory devices including a high voltage MOS transistors with a floated drain-side auxiliary gate and methods of fabricating the same |
-
2012
- 2012-10-15 CN CN201210388874.XA patent/CN103730496B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518133B1 (en) * | 2002-04-24 | 2003-02-11 | Chartered Semiconductor Manufacturing Ltd | Method for fabricating a small dimensional gate with elevated source/drain structures |
| TW200531282A (en) * | 2004-01-09 | 2005-09-16 | Elpida Memory Inc | Method for Manufacturing a semiconductor device having a low junction leakage current |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103730496A (en) | 2014-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113506809B (en) | Method for forming three-dimensional memory device with backside source contact | |
| TWI590457B (en) | Semiconductor device and fabrication method thereof | |
| JP5154347B2 (en) | Superjunction semiconductor device and method of manufacturing superjunction semiconductor device | |
| KR100442881B1 (en) | High voltage vertical double diffused MOS transistor and method for manufacturing the same | |
| CN105720058A (en) | BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY | |
| JP5517291B2 (en) | Microelectronic assembly with improved isolation voltage performance and method of forming the same | |
| CN102376763B (en) | Semiconductor assembly | |
| CN111900164B (en) | Semiconductor structure and preparation method thereof | |
| CN102339830A (en) | Semiconductor device and method for fabricating the same | |
| TWI541944B (en) | Non-volatile memory structure and method for manufacturing the same | |
| US9496333B2 (en) | Resurf high voltage diode | |
| US8907382B2 (en) | Semiconductor device and fabrication method thereof | |
| US20210005599A1 (en) | Internally stacked npn with segmented collector | |
| TWI594376B (en) | Method of forming split gate memory cells with 5 volt logic devices | |
| CN210110768U (en) | Antifuse device and antifuse cell structure | |
| CN103165428B (en) | Make the method for semiconductor device | |
| US11532741B2 (en) | Semiconductor device having vertical DMOS and manufacturing method thereof | |
| CN114122136A (en) | Device for expanding operating voltage | |
| US20100276810A1 (en) | Semiconductor device and fabrication method thereof | |
| CN103730496B (en) | Semiconductor structure and manufacture method thereof | |
| US7382030B1 (en) | Integrated metal shield for a field effect transistor | |
| US8970004B2 (en) | Electrostatic discharge devices for integrated circuits | |
| TWI535017B (en) | Semiconductor structure and manufacturing method of the same | |
| US7183155B2 (en) | Non-volatile memory device and fabricating method thereof | |
| JP2007067249A (en) | Semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |