CN103730376A - Packaging test method - Google Patents
Packaging test method Download PDFInfo
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- CN103730376A CN103730376A CN201210389784.2A CN201210389784A CN103730376A CN 103730376 A CN103730376 A CN 103730376A CN 201210389784 A CN201210389784 A CN 201210389784A CN 103730376 A CN103730376 A CN 103730376A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
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Abstract
The invention discloses a packaging test method. The packaging test method includes the following steps that a semiconductor packaging unit is provided, wherein the semiconductor packaging unit comprises a packaging adhesive body, a lead frame and a plurality of cutting lines, and a plurality of semiconductor packaging components are defined by the cutting lines on the semiconductor packaging unit and are respectively provided with a plurality of external connection terminals; the lead frame is cut along the cutting lines to electrically insulate the semiconductor packaging components; the semiconductor packaging unit is placed on a bearing wafer; a probe card is made close to the semiconductor packaging unit placed on the bearing wafer and a plurality of probe terminals of the probe card are made to make contact with the external connection terminals respectively so that the semiconductor packaging components can be tested; semiconductor packaging components with abnormal test results are marked; the semiconductor packaging components are made monomeric, and the semiconductor packaging components marked as abnormal are removed.
Description
Technical field
The invention relates to a kind of method of testing, and particularly relevant for a kind of packaging and testing method of semiconductor element.
Background technology
For in semiconductor encapsulated element manufacture process, obtain at any time the information of technique quality, therefore can be on semiconductor encapsulated element a plurality of feeler switchs of special design (test key), and these feeler switchs pick out and accept various detections again via calibrating terminal, to monitor the quality of each stage process.
Semiconductor element is after covering packing colloid and before not electroplating, it is short circuit on electrically for each wafer on its lead frame, if therefore want to test with the semiconductor packages unit of singulation (Singulation) not yet, must first complete the electrical isolation (electrical isolation) between its each wafer.
The test mode of semiconductor packages unit has the advantage on cost compared to the test mode of the wafer after singulation, but must use special-purpose test macro at present.Existing test macro is applicable to the encapsulating structure of pin more, for example: small-sized package (Small Outline Package) and cubic pin flat packaging (Quad Flat Package, QFP) etc., but for non-leaded package, for example: without pin small-sized package (Small Outline No-Lead, SON) and four directions without pin flat packaging (Quad FlatNo-lead, QFN) etc., in the technique of its wafer electric sexual isolation, but have any problem.In addition, in traditional packaging and testing, its test macro need be prepared corresponding pick device and bearing fixture for different encapsulating structure sizes, and it needs extra technique or purchases expensive device and tool, and this is all a kind of waste to production cost and time.
Summary of the invention
For solving the aforementioned problems in the prior, the invention provides a kind of packaging and testing method, it can save production cost and process time.
The present invention proposes a kind of packaging and testing method, is suitable for semiconductor encapsulation unit to test.Packaging and testing method comprises the following steps.Semiconductor packages unit is provided, and it comprises packing colloid, lead frame and a plurality of Cutting Road.Cutting Road defines a plurality of semiconductor encapsulated elements on semiconductor packages unit.Each semiconductor encapsulated element has a plurality of external connection terminals.Cut-out is positioned at the lead frame on Cutting Road, so that semiconductor encapsulated element is electrically insulated each other.Semiconductor packages unit is loaded on carrying wafer.Carrying wafer is sent to a tester table by semiconductor packages unit.Tester table has a probe.Make probe near the semiconductor packages unit loading on carrying wafer, a plurality of probe terminals that probe possesses are contacted respectively, so that each semiconductor encapsulated element is tested with external connection terminals.Labeled test result is abnormal semiconductor encapsulated element.Singulation semiconductor encapsulated element also removes and is marked as abnormal semiconductor encapsulated element.
Based on above-mentioned, the present invention utilizes first and cuts off lead frame along Cutting Road, so that be electrically insulated each other between each semiconductor encapsulated element of semiconductor packages unit, but incomplete each semiconductor encapsulated element of singulation, with this, whole semiconductor packages unit can be loaded on carrying wafer, and utilize the probe of test wafer to test semiconductor encapsulation unit, to learn that test result is shown as the address of abnormal semiconductor encapsulated element, and it is removed.Therefore, the present embodiment has not only been simplified the flow process of packaging and testing, the cost that reduces packaging and testing, more can utilize the tester table of test wafer to test other without encapsulating structures such as pin small-sized package and small-sized packages, thereby improve the use elasticity of its tester table.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet according to a kind of packaging and testing method of one embodiment of the invention.
Fig. 2 is a kind of semiconductor packages unit partial schematic diagram according to one embodiment of the invention.
Fig. 3 is the generalized section according to a kind of semiconductor packages unit of one embodiment of the invention.
Fig. 4 is a kind of semiconductor packages unit according to one embodiment of the invention generalized section after being electrically insulated.
Fig. 5 is that a kind of semiconductor packages unit according to one embodiment of the invention is arranged at the schematic top plan view on carrying wafer.
Fig. 6 carries out the generalized section of testing electrical property according to a kind of semiconductor packages unit of one embodiment of the invention.
Fig. 7 is a kind of semiconductor packages unit according to one embodiment of the invention generalized section after singulation.
Fig. 8 is a kind of semiconductor packages unit partial schematic diagram according to another embodiment of the present invention.
Fig. 9 is the generalized section according to a kind of semiconductor packages unit of another embodiment of the present invention.
Figure 10 is a kind of semiconductor packages unit according to another embodiment of the present invention generalized section after being electrically insulated.
Figure 11 carries out the generalized section of testing electrical property according to a kind of semiconductor packages unit of another embodiment of the present invention.
Wherein, description of reference numerals is as follows:
100,100a: semiconductor packages unit
110: packing colloid
120: lead frame
122,122a: external connection terminals
124: connecting rod
130: Cutting Road
140,140a: semiconductor encapsulated element
150: location hole
200,200a: carrying wafer
210: reference column
300: probe
310: probe terminal
320: compress post
Embodiment
Fig. 1 is the schematic flow sheet according to a kind of packaging and testing method of one embodiment of the invention.Fig. 2 is a kind of semiconductor packages unit partial schematic diagram according to one embodiment of the invention.Fig. 3 is the generalized section according to a kind of semiconductor packages unit of one embodiment of the invention.Referring to Fig. 1, Fig. 2 and Fig. 3, the packaging and testing method of the present embodiment is suitable for semiconductor encapsulation unit 100 to carry out yield test, first its packaging and testing method comprises the following steps:, execution step S110, semiconductor encapsulation unit 100 is as shown in Figures 2 and 3 provided, and it comprises packing colloid 110, lead frame 120 and a plurality of Cutting Road 130.Cutting Road 130 defines a plurality of semiconductor encapsulated elements 140 on semiconductor packages unit 100.Each semiconductor encapsulated element 140 has a plurality of external connection terminals 122, and external connection terminals 122 is positioned on lead frame 120.In the present embodiment, semiconductor encapsulated element 140 is without pin small-sized package (Small Outline No-Lead package, SON package), and its external connection terminals 122 is in order to make the connection pad of testing electrical property.
Fig. 4 is a kind of semiconductor packages unit according to one embodiment of the invention generalized section after being electrically insulated.Fig. 5 is that a kind of semiconductor packages unit according to one embodiment of the invention is arranged at the schematic top plan view on carrying wafer.Then, execution step S120, as shown in Figure 4, cuts off lead frame 120 along Cutting Road 130, so that semiconductor encapsulated element 140 is mutually electrically insulated.The semiconductor encapsulated element 140 cutting off after lead frame 120 along Cutting Road 130 is connected to each other with the packing colloid 110 being positioned on Cutting Road 130.Then, execution step S130, as shown in Figure 5, loads semiconductor packages unit 100 on a carrying wafer 200.In the present embodiment, carrying wafer 200 only carries a semiconductor packages unit 100, but in other embodiments of the invention, carrying wafer 200 also can once carry a plurality of semiconductor packages unit 100.The quantity of the semiconductor packages unit 100 that carrying wafer 200 can carry is determined according to the actual size of carrying wafer 200 and semiconductor packages unit 100, and the present invention is not as limit.
In the present embodiment, semiconductor packages unit 100 has at least one location hole 150, and carrying wafer 200 has at least one reference column 210 corresponding with location hole 150.When semiconductor packages unit 100 loads on carrying wafer 200, reference column 210 enters corresponding location hole 150, so that semiconductor packages unit 100 is positioned to carry on wafer 200.In the present embodiment, location hole 150 and reference column 210 have more respectively corresponding error-proof structure, and this means, location hole 150 and location hole 150 chimeric has directivity, in order to fixing semiconductor packages unit 100, load the mounting direction on carrying wafer 200, prevent artificial loading anisotropy.For example, location hole 150 can be D type perforation, and reference column 210 can be the D type post corresponding with it.Or, carrying wafer 200 can have a plurality of reference columns 210, its arrangement mode has directivity, is made with directivity ground chimeric with the location hole corresponding with semiconductor packages unit 100 150, with fixing semiconductor packages unit 100, loads the mounting direction on carrying wafer 200.Above embodiment is only for illustrating, and the present invention does not limit the design of the error-proof structure of location hole 150 and reference column 210.
Fig. 6 carries out the generalized section of testing electrical property according to a kind of semiconductor packages unit of one embodiment of the invention.Then, execution step S140, is sent to a tester table to carry wafer 200 by semiconductor packages unit 100.As shown in Figure 6, tester table has a probe 300, and wherein, probe 300 has a plurality of probe terminals 310.In the present embodiment, tester table is a wafer sort board.While testing, probe 300 moves toward the direction near semiconductor packages unit 100, probe 300 is approached and load the semiconductor packages unit 100 on carrying wafer 200, and, as shown in Figure 6, the probe terminal 310 of probe 300 is contacted respectively, so that each semiconductor encapsulated element 140 is tested to (step S160) with external connection terminals 122.
In addition; because packing colloid 110 is very large with the thermal expansion coefficient difference (thermalexpansion coefficient mismatch) of lead frame 120; therefore; when semiconductor encapsulation unit 100 is carried out to different high-temperature technologies; often can make because operating temperature raises semiconductor packages unit 100 produce warpage, and then cause probe 300 and its external connection terminals 122 loose contacts.In view of this, in the present embodiment, probe 300 more can have a plurality of posts 320 that compress, it lays respectively at the center of semiconductor encapsulated element 140, when probe terminal 310 is contacted with external connection terminals 122, compress post 320 and can compress each semiconductor encapsulated element 140 center, reduce the degree of its warpage, to avoid the situation that above-mentioned probe 300 and its external connection terminals 122 may loose contact.
Fig. 7 is a kind of semiconductor packages unit according to one embodiment of the invention generalized section after singulation.Execution step S160, labeled test result is abnormal semiconductor encapsulated element 140.Then, as shown in Figure 7, execution step S170, singulation semiconductor encapsulated element 140, and perform step S180, remove and be marked as abnormal semiconductor encapsulated element 140.Because semiconductor encapsulated element 140 is without pin small-sized package (SON package), its semiconductor encapsulated element 140 after being electrically insulated is connected to each other with the packing colloid 110 being positioned on Cutting Road 130.Therefore, in the present embodiment, the method for singulation semiconductor encapsulated element 140 is positioned at the packing colloid 110 on Cutting Road 130 for cutting off, with separated each semiconductor encapsulated element 140.
Due to the present embodiment use carrying wafer 200 with and 300 pairs of semiconductor encapsulation units 100 of probe test, therefore, after carrying out survey formula, tester table is divided into a normal group and an abnormal group by semiconductor encapsulated element 140, and read the coordinate address of each semiconductor encapsulated element 140 on carrying wafer 200, to be depicted as a wafer figure.Then,, according to the coordinate address that belongs to the semiconductor encapsulated element 140 of abnormal group on wafer figure, on marking wafer figure, belong to the semiconductor encapsulated element 140 of abnormal group.In another embodiment of the present invention, also can, after drawing wafer figure, wafer figure be sent to another board, to remove the semiconductor encapsulated element 140 that belongs to abnormal group.
Hold above-mentionedly, its test result of mark is that the method for abnormal semiconductor encapsulated element 140 is for example ink annotation.In the present embodiment, the ink that ink annotation is used is general ink.Yet, in other embodiments of the invention, also can come mark to belong to the semiconductor encapsulated element 140 of abnormal group by a constrictive type ink, wherein, constrictive type ink be such as being heat fixed type ink (thermal curing ink) or UV cured type ink (UV curing ink) etc.Only use this kind of ink need increase the technique of the semiconductor encapsulated element after mark 140 being sent to baking box baking, so that constrictive type ink hardens and determining on semiconductor encapsulated element 140.
Packaging and testing method described above, the present embodiment only first cuts off and is positioned at the lead frame 120 on Cutting Road 130, so that 140 of each semiconductor encapsulated elements of semiconductor packages unit 100 are electrically insulated each other, but incomplete each semiconductor encapsulated element 140 of singulation, therefore whole semiconductor packages unit 100 can be loaded on carrying wafer 200, and utilize 300 pairs of semiconductor encapsulation units 100 of probe of test wafer to test.So, saved existing after singulation semiconductor encapsulated element 140, need pick up respectively each semiconductor encapsulated element 140 to the complicated technique of testing again on pallet with special pick device, more can save and existingly need purchase and meet the pick device of its size and the cost of pallet for various semiconductor encapsulated elements 140.Therefore, the present embodiment not only can be simplified the flow process of packaging and testing, reduces the cost of packaging and testing, more can utilize the probe of test wafer to test without pin small-sized package structure, thereby improve the use elasticity of tester table.
Fig. 8 to Figure 11 is the schematic diagram according to the packaging and testing method of another embodiment of the present invention.The present embodiment is continued to use element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and it is no longer repeated for the present embodiment.
Fig. 8 is a kind of semiconductor packages unit partial schematic diagram according to another embodiment of the present invention.Fig. 9 is the generalized section according to a kind of semiconductor packages unit of another embodiment of the present invention.Figure 10 is a kind of semiconductor packages unit according to another embodiment of the present invention generalized section after being electrically insulated.Please first simultaneously with reference to figure 8 and Fig. 9, the packaging and testing method of the present embodiment can adopt the production method roughly the same with the flow process of the packaging and testing method of previous embodiment, only in the present embodiment, each semiconductor encapsulated element 140a is a small-sized package (Small Outline Package, SOP), therefore each external connection terminals 122a is a pin, and as shown in Figure 9 in the direction of Cutting Road 130, connect semiconductor encapsulated element 140a.As shown in Figure 8, the lead frame of semiconductor packages unit 100a also has a plurality of connecting rods 124, to connect semiconductor encapsulated element 140a in the direction in parallel Cutting Road 130.
Therefore, the semiconductor packages unit 100a of the present embodiment, when being electrically insulated, as shown in figure 10, is to cut off to be positioned at the pin 122a on Cutting Road 130, so that semiconductor encapsulated element 140 is mutually electrically insulated.Semiconductor encapsulated element 140a after being electrically insulated is connected to each other in the direction that is parallel to Cutting Road 130 with connecting rod 124 respectively.Therefore, the step of the singulation semiconductor encapsulated element 140a of the present embodiment is to cut off connecting rod 124 along the direction perpendicular to Cutting Road 130, so can singulation semiconductor encapsulated element 140a.
Figure 11 carries out the generalized section of testing electrical property according to a kind of semiconductor packages unit of another embodiment of the present invention.Referring again to Figure 11, hold above-mentioned, because the external connection terminals 122a of the present embodiment is pin, and its below there is no any support, therefore, carrying wafer 200a in order to bearing semiconductor encapsulation unit 100a in the present embodiment also has a plurality of support portion 210a, is positioned at the pin 122a on Cutting Road 130 respectively, pin 122a is provided support when probe terminal 310 contacts with pin 122a in order to support.
In sum, the lead frame being positioned on Cutting Road is first cut off in utilization of the present invention, so that be electrically insulated each other between each semiconductor encapsulated element of semiconductor packages unit, but incomplete each semiconductor encapsulated element of singulation, therefore whole semiconductor packages unit can be loaded on carrying wafer, and utilize the probe of test wafer to test semiconductor encapsulation unit.Finally, then draw a wafer figure according to test result, with further labeled test result, be shown as the address of abnormal semiconductor encapsulated element, and it is removed.
So, the present invention has saved and existingly after singulation semiconductor encapsulated element, need pick up respectively each semiconductor encapsulated element to the complicated technique of testing again on pallet with special pick device, more can save existingly need purchase and meet the pick device of its size and the cost of pallet for various semiconductor encapsulated elements.Therefore, the present embodiment not only can be simplified the flow process of packaging and testing, the cost that reduces packaging and testing, more can utilize the tester table of test wafer to test other without encapsulating structures such as pin small-sized package and small-sized packages, thereby improve the use elasticity of its tester table.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (15)
1. a packaging and testing method, is suitable for semiconductor encapsulation unit to test, and comprising:
This semiconductor packages unit is provided, this semiconductor packages unit comprises a packing colloid, a lead frame and a plurality of Cutting Road, described a plurality of Cutting Road defines a plurality of semiconductor encapsulated elements on semiconductor packages unit, each semiconductor encapsulated element has a plurality of external connection terminals, is positioned on this lead frame;
Along described a plurality of Cutting Roads, cut off this lead frame, so that described a plurality of semiconductor encapsulated element is electrically insulated each other;
This semiconductor packages unit is loaded on a carrying wafer;
With this carrying wafer, this semiconductor packages unit is sent to a tester table, this tester table has a probe;
Make probe near loading this semiconductor packages unit on this carrying wafer, a plurality of probe terminals that this probe possesses are contacted with this external connection terminals respectively, so that this semiconductor encapsulated element is respectively tested;
Labeled test result is abnormal described a plurality of semiconductor encapsulated elements;
A plurality of semiconductor encapsulated elements described in singulation; And
Remove and be marked as abnormal described a plurality of semiconductor encapsulated elements.
2. packaging and testing method as claimed in claim 1, wherein respectively this semiconductor encapsulated element is that a small size is without pin package element.
3. packaging and testing method as claimed in claim 2, wherein respectively this external connection terminals is a connection pad.
4. packaging and testing method as claimed in claim 2, wherein cuts off after this lead frame along described a plurality of Cutting Roads, and described a plurality of semiconductor encapsulated elements are connected to each other with this packing colloid being positioned on this Cutting Road.
5. packaging and testing method as claimed in claim 4, wherein described in this singulation, the step of a plurality of semiconductor encapsulated elements comprises:
Cut-out is positioned at this packing colloid on described a plurality of Cutting Road, with a plurality of semiconductor encapsulated elements described in singulation.
6. packaging and testing method as claimed in claim 1, wherein respectively this semiconductor encapsulated element is a small-sized package element.
7. packaging and testing method as claimed in claim 6, wherein respectively this external connection terminals is a pin.
8. packaging and testing method as claimed in claim 7, the step of wherein cutting off this lead frame along described a plurality of Cutting Roads comprises:
Along described a plurality of Cutting Roads, cut off described a plurality of pins of this lead frame, with respectively this semiconductor encapsulated element that is electrically insulated.
9. packaging and testing method as claimed in claim 6, wherein this lead frame of this semiconductor packages unit also has a plurality of connecting rods, to connect described a plurality of semiconductor encapsulated element in the direction in parallel this Cutting Road, and the described a plurality of semiconductor encapsulated elements after being electrically insulated are connected to each other with described a plurality of connecting rods respectively.
10. packaging and testing method as claimed in claim 9, wherein described in this singulation, the step of a plurality of semiconductor encapsulated elements comprises:
Along the direction perpendicular to this Cutting Road, cut off described a plurality of connecting rods, with a plurality of semiconductor encapsulated elements described in singulation.
11. packaging and testing methods as claimed in claim 7, wherein this carrying wafer has a plurality of support portions, supports and is positioned at the described a plurality of pins on described a plurality of Cutting Road respectively, to provide support when described a plurality of probe terminals contact with described a plurality of pins respectively.
12. packaging and testing methods as claimed in claim 1, wherein this probe also has a plurality of posts that compress, and when described a plurality of probe terminals contact with this external connection terminals respectively, described a plurality of posts that compress compress respectively the respectively center of this semiconductor encapsulated element.
13. packaging and testing methods as claimed in claim 1, also comprise:
After respectively this semiconductor encapsulated element is tested, draw a wafer figure, described a plurality of semiconductor encapsulated elements are divided into a normal group and an abnormal group; And
The described a plurality of semiconductor encapsulated elements that belong to this abnormal group on this wafer of mark figure.
14. packaging and testing methods as claimed in claim 1, also comprise:
After respectively this semiconductor encapsulated element is tested, draw a wafer figure, described a plurality of semiconductor encapsulated elements are divided into a normal group and an abnormal group; And
This wafer figure is sent to a board, to remove the described a plurality of semiconductor encapsulated elements that belong to this abnormal group.
15. packaging and testing methods as claimed in claim 1, wherein labeled test result is that the method for abnormal described a plurality of semiconductor encapsulated elements comprises general ink annotation.
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| CN201210389784.2A CN103730376B (en) | 2012-10-15 | 2012-10-15 | Packaging and testing method |
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| CN201210389784.2A CN103730376B (en) | 2012-10-15 | 2012-10-15 | Packaging and testing method |
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| CN103730376B CN103730376B (en) | 2018-04-03 |
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| CN105742199A (en) * | 2014-12-30 | 2016-07-06 | 震扬集成科技股份有限公司 | Test method |
| CN106800272A (en) * | 2017-02-17 | 2017-06-06 | 烟台睿创微纳技术股份有限公司 | A kind of MEMS wafer cutting and wafer scale release and method of testing |
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| CN106800272A (en) * | 2017-02-17 | 2017-06-06 | 烟台睿创微纳技术股份有限公司 | A kind of MEMS wafer cutting and wafer scale release and method of testing |
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| CN103730376B (en) | 2018-04-03 |
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