CN103729449B - Reference data access management method and device - Google Patents
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- CN103729449B CN103729449B CN201310751654.3A CN201310751654A CN103729449B CN 103729449 B CN103729449 B CN 103729449B CN 201310751654 A CN201310751654 A CN 201310751654A CN 103729449 B CN103729449 B CN 103729449B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
The invention discloses a reference data access management method and device suitable for H.264/AVC parallel encoding devices. The reference data access management device comprises a plurality of first-stage buffering units respectively connected with a coding core, the first-stage buffering units are connected to a second-stage buffering unit through a bus, and the second-stage buffering unit is further connected with an external storage device. Only when data accessed by the coding core does not exist in the first-stage buffering units and the second-stage buffering unit, the data are required to be obtained from the external storage device. According to the reference data access management method and device, the relativity of macro block multi-core parallel H.264 encoder to visit reference data can be sufficiently used, and the access amount of the external storage device to the reference data is sufficiently reduced. Repeated buffering block storage in each buffer memory is eliminated as much as possible, and the hardware cost of the reference data access management device is ultra low.
Description
Technical field
The present invention relates to coding and decoding video field, more particularly, to a kind of ginseng being applied to H.264/AVC parallel encoding device
Examine data administrator it is adaptable to macro-block line（Marco-Block Row）Reference data for the parallel encoding of ultimate unit is visited
Ask management method and device.
Background technology
H.264/AVC standard is accepted by industry with its remarkable compression of images performance, however as need encode
Image form rise to D1,720P, 1080P or even 4kx2k from CIF（Ultra high-definition）, H.264 encode higher operand one
The field that a little low-power consumption have high demands just becomes a subject matter.Industry reduces H.264 coding power consumption and adopts in algorithm implementation phase
With means be to reduce the clock frequency of the hardware/processor in cataloged procedure by parallel processing, and then reduce hardware fortune
Row voltage is reducing system power dissipation.
On the other hand, need to refer to frame image data (hereinafter referred to as reference when H.264 predicting between encoder conducting frame
Data) information.And because the size of reference frame image is difficult to greatly in encoder chip storage inside, therefore generally they are deposited
Storage is in outside DDR.It is generally the largest portion of H.264 encoder external memory access to the access of reference frame image.Subtract
The visit capacity of few reference data will play an important role to the external memory access cutting down H.264 encoder, and and then drops
The overall power of low encoder.
H.264/AVC coded method based on macro-block line by picture frame be decomposed into multiple macro-block line submit to respectively multiple solely
Vertical coding core, thus only need to increase the quantity of coding core the lifting coding throughput it becomes possible to near-linear, therefore
The design reaching high-throughput becomes simple.This makes to design the encoder of a high-throughput and reduce voltage and reduce work
Frequency is possibly realized with reducing power consumption.
Simultaneously as it is multiple grand by multiple core parallel encodings based on the parallel H.264/AVC coded method of macro-block line
Block row.Not only there is overlap in each Macroblock Motion hunting zone of each core processing.The motion search range of its each core
There is also overlap.The locality of reference of therefore its reference data compares common single core encoder or frame/slice level coding
Device is more prominent.Under good reference data access control management, its reference data access bandwidth is less than and is commonly based on
The single core encoder of levelC data reusing or the parallel multi-core parallel encoder of frame/slice level.Answer for typical
With configuring, its theoretical reference data access bandwidth can reduce by more than 50% relative to single core encoder.
But on the other hand, compare the data access of single core encoder, the parallel data of multiple parallel encoding cores is visited
Ask and its access dependency so that reference data Access Management Access becomes increasingly complex.And compare the single core of maturation H.264
The reference data Access Management Access technology of encoder, macro-block line parallel H.264 the reference data access problem of encoder do not have
To perfect solution.
Intuitively way is to provide reference number using a Multiport-RAM or cache for all of coding core simultaneously
According to as shown in Figure 1.But the reference frame by each core inner accesses had high bandwidth characteristic（Often reach every clock
Cycle bit up to a hundred, the coding of each macro block needs to access the reference data of ten a few to tens of macro blocks）, estimation is multiple in addition
Data access features that are miscellaneous and being misaligned to memory boundary make this design difficulty from framework to back end design all very big, especially
It is in the more occasion of coding core number.Its high complexity is unfavorable with power consumption control to hardware spending.
One simple and feasible way is that each core all designs according to common single core coder mode.As Fig. 2
Shown, each coding core has the reference frame data access administration module of oneself, and each independent access external memory storage
In reference data.The reference data access control of single core encoder in the industry cycle have passed through substantial amounts of exploration and research, often
The Access Management Access mechanism based on sliding window or based on cache seen can efficient reuse reference frame data access（Li-Fu
Ding, Multiview Video Coding:Algorithms, VLSI Architectures, and System Design,
Graduate Institute of Electronics Engineering College of Electrical
Engineering&Computer Science National Taiwan University Doctoral
Dissertation）, the design difficulty of therefore this scheme is low.But this way can only be using each in same macro-block line
The reference data of individual macro block accesses dependency.And the dependency that each macro block in the ranks accesses to reference data does not obtain profit
With.Namely mean that the data reusing grade of macro-block line parallel encoder remains in levelC, low theory access bandwidth
Advantage has no way of embodying.
In order to eliminate the repeated accesses to reference data between each coding core, intuitively way is the data in the first order
The data access control device being further added by the second level between access control apparatus and external memory storage is to provide each coding core
Data reusing in the ranks, data reusing grade is promoted to levelC+ or levelD from levelC.Any one coding core
Reference frame data after the repeated accesses reusing elimination of level direction by local first order data access control device, then
Unified access external RAM is controlled by second level data access control device.The also big portion of reference data repeated accesses so in the ranks
Get elimination, further reduce the access bandwidth to external memory storage for the overall situation.Test shows bandwidth under typical scene
More than 50% can be reduced, outside access bandwidth reuses close to levelD but hardware spending is far below levelD.But certainly,
Increase second level data access control module and increased extra hardware spending.Under typical application scenarios, due to ginseng
Examining data needs to repeat to store in first and second DBMS access control apparatus, and local RAM expense generally can be made to double.
By the local buffer within first order data access control device, such as sliding window or cache are considered as distributed RAM simultaneously
Contribute to reducing RAM expense using NUMA (non-uniform memory access, Non Uniform Memory Access accesses) architecture management
Problem, however common cache consistency protocol such as MOESI for H.264 coding core excessively complicated it is difficult to design with
Checking.And make the data management within data access control module of each coding core be required for considering that other encode core
The heart, this makes to design complication especially.So far do not adopt the report of the H.264 macro block parallel encoder of this design.
Content of the invention
The technical problem to be solved is to provide one kind to have high-throughput, low-power consumption and low hardware spending advantage concurrently
And the reference data management method and the device that are applied to H.264/AVC parallel encoding device of the simply easily designed checking of structure.
For realizing above-mentioned technique effect, the invention discloses a kind of reference being applied to H.264/AVC parallel encoding device
Data access management method, described reference data access management method includes implemented below step：
Coding core initiates an access request to level cache unit；
Described level cache unit inquires about its internal first multiport 2D buffer, and to described coding core referring back to
Data；
When no mating reference data in described first multiport 2D buffer, described level cache unit pass through bus to
L2 cache unit initiates to refill request；
Described L2 cache unit inquires about its internal second multiport 2D buffer, and returns to described level cache unit
Refill reference data；
When no coupling refills reference data in described second multiport 2D buffer, send reference to external memory storage
Request of data, and the reference data returning from described external memory storage is sent to level cache unit by bus.
Described reference data access management method is further improved by, when nothing in described second multiport 2D buffer
When coupling refills reference data, described L2 cache unit first inquires about the entry of its internal snoop filter, and to described bar
The level cache unit that mesh is located initiates request, and described level cache unit takes out asked ginseng according to described request from internal
Examine data, when no matching item in described internal snoop filter, described L2 cache unit is again to described external memory storage
Send reference data request.
The invention also discloses a kind of reference data access management apparatus being applied to H.264/AVC parallel encoding device,
Described reference data access management apparatus include multiple level cache units connecting a coding core respectively, described level cache
Unit is connected to a L2 cache unit by a bus, and described L2 cache unit connects external memory storage further.
Described reference data access management apparatus are further improved by, and described bus includes bus control unit and control
System is connected to the interconnection structure of described bus control unit, and described interconnection structure includes refilling request for transmitting reference data
Refill request（refilling_req）Passage assists with refilling request（refilling_ast）Passage and be used for transmitting
Reference data retain data（victim）Passage and refill value evidence（refilling）Passage.
Described reference data access management apparatus are further improved by, and described level cache unit includes the first multiterminal
Mouth 2D buffer, described level cache unit is connected by described bus to the motion estimation module of affiliated coding core, institute
State level cache unit be provided with refill request auxiliary（refilling_ast）Passage with retain data（victim）Passage.
Described reference data access management apparatus are further improved by, and described L2 cache unit includes the second multiterminal
Mouthful 2D buffer, bus snooping module, snoop filter, retain buffering and external reference Data access module, described retain
Buffering connects described second multiport 2D buffer and described bus snooping module respectively, and described second multiport 2D buffer enters
One step connects described snoop filter, and described bus snooping module also connects described snoop filter further, described tries to find out
Filter connects described external reference Data access module further, and described external reference Data access module connects outside described
Portion's memorizer.
Described reference data access management apparatus are further improved by, and described level cache unit passes through described retaining
Data（victim）Passage retains buffering described in connecting；Described snoop filter passes through described refilling asks auxiliary
（refilling_ast）Passage connects described level cache unit.
Described reference data access management apparatus are further improved by, and one or more described refill request
（refilling_req）Passage connects to described bus snooping module with described second multiport 2D buffer to transmit reference number
According to access；Described snoop filter connects asks auxiliary to described refilling（refilling_ast）Passage is to transmit reference number
According to access.
Described reference data access management apparatus are further improved by, and described external reference Data access module connects
To described refill value evidence（refilling）Passage is to transmit reference data.
The present invention is due to employing above technical scheme so as to having the advantages that and being：
Only when the data that coding core accesses all does not exist in all of level cache unit with L2 cache unit
Just need to obtain in external memory storage.Data in level cache unit can be considered as hot data and (refer to the number being used recently
According to), the data visualization in L2 cache unit is cold data（Refer to the data being not used by recently）, therefore the present invention realize
Overall buffer stopper replacement policy is class LIRS (Low Interreference Recency Set, a Song Jiang＆
Xiaodong Zhang《LIRS:an efficient low inter-reference recency set replacement
to improve buffer cache performance》) algorithm, all there is under various scenes good performance.Thus this
Invention can sufficiently utilize macro-block line multi-core parallel concurrent, and H.264 encoder accesses the dependency of reference data, fully reduces its ginseng
Examine data external number of memory accesses.
Due to eliminating the buffer stopper storage repeating in each caching as far as possible, the hardware spending of the present invention is also very low.
The parallel H.264 encoder for typical 4 core macro-block line, the outside access bandwidth of reference data just corresponds to
The levelC of similar search scope reuses the 1/3 of H.264 monokaryon encoder.On internal piece, RAM size is also only equivalent to this list
The 1/2 of the reference data management module of core encoder, and there is not the defect that sliding window limits motion vector range.
With respect to the simple scheme increasing a second layer reference data access control module, the present invention has similar
Outside access bandwidth characteristic, but on piece, RAM expense can reduce 1/3.
And with respect to the complicated and non-homogeneous memory access model (Non Uniform Memory Access) of tightly coupled NUMA,
The level cache unit of the present invention couple with L2 cache unit very loose it is easy to be separately optimized design, and the present invention do not need multiple
Miscellaneous cache consistency protocol, significantly reduces the difficulty of checking and design.
Brief description
Fig. 1 is the structure of the managing device being provided reference data by single multiport sliding window/cache for all coding core
Schematic diagram.
Fig. 2 is that multiple independent reference data management modules provide the managing device of reference data for each coding core
Structural representation.
Fig. 3 is the structural representation of two-stage reference data access control apparatus.
Fig. 4 is the structural representation of reference data access management apparatus of the present invention.
Fig. 5 is the structural representation of the L2 cache unit of reference data access management apparatus of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawings and specific embodiment the present invention is further detailed explanation.
Referring initially to shown in Fig. 4, the present invention is by the exclusive multiple level cache units 101 of each coding core 100
（L1cache）, the L2 cache unit 102 shared by all coding core（L2cache）And connect 103 groups of both buses
Become.
Level cache unit 101 is the first multiport 2D buffer.Level cache unit 101 by bus 103 connect to
L2 cache unit 102, and connect to the motion estimation module of affiliated coding core 100.It is directly affiliated coding core
100 motion estimation module provides reference data, and in the form of the two dimensional image block caching specified buffering block size to
Its external request reference data.Therefore, inside level cache unit self-encoding encoder in 101 future, the access of reference data is converted to
Homogeneous and the buffering block size of alignment external image accesses, and eliminates the correlation that in row, each macro block accesses to reference data
Property.The structure of level cache unit 101 common monokaryon encoder reference managing device structure based on caching similar with realization,
But for matching bus interconnection, increased and refill request auxiliary（refilling_ast）Passage with retain data（victim）
Passage.Increased passage allows L2 cache unit 102 to initiate request and read buffer stopper from level cache unit 101.Increase
The increasedd access bandwidth demand of access path can be balanced by the port number increasing level cache unit 101.
Shown in cooperation Fig. 5, L2 cache unit 102 comprises the second multiport 2D buffer 105, a bus snooping module
106th, snoop filter 107 (snoop filter), retain buffering 108 (victim buffer) and external reference data and visit
Ask module 109.L2 cache unit 102 connects each level cache unit 101 by bus 103, and is connected to external storage
Device 200.Bus 103 retain data（victim）Passage is connected to and retains buffering 108 to transmit reference data, retains buffering
108 companies of permission are multiple to retain data（victim）Passage is with the parallel reference data receiving multiple coding core；Retain buffering
108 are connected to the second multiport 2D buffer 105 to transmit reference data；Retain buffering 108 connect bus snooping modules 106 with
Transmission reference data transmission state；Second multiport 2D buffer 105 connects the refill value evidence of bus（refilling）Passage
To transmit reference data, multiport characteristic allows the second multiport 2D buffer 105 to connect multiple refilling passages with simultaneously
Transmit reference data for multiple and buffer unit 101；Second multiport 2D buffer 105 be connected to snoop filter 107 with
Transmission reference data accesses；One or more refills request（refilling_req）Passage connects to bus snooping and
Two multiport 2D buffers 105 are to transmit reference data access.Retain buffering 108 and bus refilling_req passage connects
It is connected to bus snooping module 106 and asked with reference data with transmitting reference data；Bus snooping module 106 connects to snoop filtering
Device 107 is to transmit reference data access；Snoop filter 107 connects asks auxiliary to refilling of bus（refiiling_
ast）Passage with transmit reference data access, snoop filter 107 may be connected to multiple refilling_ast passages with simultaneously to
Multiple and buffer unit 101 sends request；The externally connected reference data access modules 109 of snoop filter 107 are to transmit
Reference data accesses；External reference Data access module 109 connects to bus refilling passage to transmit reference data；Outward
Externally connected memorizer 200 interface of portion's reference data access modules 109, initiates reference data and accesses and receive reference data.
L2 cache unit 102 monitors all bus data transfer by bus snooping module 106, and follows the trail of whole level cache units
101 label (tag) updates and internally sets up snoop filter 107 to avoid increasing the label to level cache unit 101
(tag) probe requests thereby.L2 cache unit 102 uses as the victim of whole level cache units 101, and caching delays from one-level
The buffer stopper that memory cell 101 is replaced.Retain the speed that buffering 108 is used for matching bus and L2 cache unit 102 operation, keep away
Exempt from victim data to overflow.The external reference Data access module 109 of L2 cache unit 102 is responsible for passing through external memory storage
Reference data in 200 access interface reading external memories 200.
Bus 103 connects each level cache unit 101 and L2 cache unit 102.It include bus control unit with
And interconnection structure.Bus control unit controls the information on interconnection structure to exchange；Interconnection structure by refilling_req,
Tetra- passages of refilling_ast, refilling and victim are constituted.Refilling_req and refilling_ast uses
Refill request in transmission reference data；Victim and refilling passage are then used for transmitting reference data.Wherein
Refilling is L2 cache unit 102 to each level cache unit 101 with the transmission direction of refilling_ast passage；
Refilling_req and victim passage is each level cache unit 101 to L2 cache unit 102.L2 cache list
Unit 102 and bus 103 have multiple connections, multiple are connected to improve access bandwidth.
A kind of operating process of the reference data access management method being applied to H.264/AVC parallel encoding device of the present invention
As follows：
When coding core 100 needs to access reference data, it initiates an access request to level cache unit 101.
Level cache unit 101 checks to access whether hit inner buffer.If hit, return the number of its request to coding core 100
According to.The refilling_req passage otherwise passing through bus 103 initiates to refill request to L2 cache unit 102.
L2 cache unit 102 first checks whether in locally stored hit after being connected to request, locally stored hit refers to please
The reference data asked in the second local multiport 2D buffer 105 of L2 cache unit 102 or retains presence in buffering 108.
If in locally stored hit, the reference data hit is returned by level cache unit 101 by refilling passage.If not existing
Locally stored hit, then check the entry in snoop filter 107, if hit snoop filter 107, passes through refilling_
Ast passage initiates request to the level cache unit 101 that entry is located.Level cache unit 101 receives refilling_ast and passes
Take out asked reference data from inner buffer after the request coming, and bus is returned to by victim passage.Bus
This reference data is sent to the level cache unit 101 initiating refiling request by refilling passage.If refilling
Reference data request L2 cache unit 102 is locally stored and snoop filter 107 in all miss, then L2 cache list
Unit 102 sends request reference data to external memory storage 200, and the data returning from external memory storage 200 is passed through bus 103
Refilling passage send to initiate refilling request level cache unit 101.
When the level cache unit 101 initiating to refill request receives the caching from bus refilling channel transfer
After block number evidence, it is loaded into internal RAM and updates internal tag table, subsequently the reference data that coding core is asked is returned.When
When cache blocks that this refills enter level cache unit 101, may replace in level cache unit 101 one original slow
Counterfoil, can adopt various replacement policies, including but not limited to PLRU (Pseudo-Least Recently Used, puppet-nearest
Minimum use) or random replacement etc..Now this cache blocks is sent to two grades by level cache unit 101 by victim passage
Buffer unit 102 simultaneously temporarily stores in retaining buffering 108.L2 cache unit 102 checks at one's leisure and retains in buffering 108
Cache blocks whether exist in local cache, if having existed, being abandoned, being otherwise deposited into local cache.This
May need during individual to replace the internal original cache blocks of L2 cache unit 102, various replacement policies can be adopted, including
But it is not limited to PLRU or random replacement etc..
Above in association with accompanying drawing embodiment, the present invention is described in detail, those skilled in the art can be according to upper
State and bright the present invention is made with many variations example.Thus, some details in embodiment should not constitute limitation of the invention, this
Invention is by the scope being defined using appended claims as protection scope of the present invention.
Claims (8)
1. a kind of reference data access management method being applied to H.264/AVC parallel encoding device is it is characterised in that described ginseng
Examine data access management method and include implemented below step：
Coding core initiates an access request to level cache unit；
Described level cache unit inquires about its internal first multiport 2D buffer, and to described coding core referring back to number
According to；
When no mating reference data in described first multiport 2D buffer, described level cache unit passes through bus to two grades
Buffer unit initiates to refill request；
Described L2 cache unit inquires about its internal second multiport 2D buffer, and fills out to the return of described level cache unit again
Fill reference data；
When no coupling refills reference data in described second multiport 2D buffer, send reference data to external memory storage
Request, and the reference data returning from described external memory storage is sent to level cache unit by bus.
2. reference data access management method as claimed in claim 1 it is characterised in that：When described second multiport 2D caching
When in device, no coupling refills reference data, described L2 cache unit first inquires about the entry of its internal snoop filter, and to
The level cache unit that described entry is located initiates request, and described level cache unit is asked from internal taking-up according to described request
The reference data asked, when no matching item in described internal snoop filter, described L2 cache unit is again to described outside
Memorizer sends reference data request.
3. a kind of reference data access management apparatus being applied to H.264/AVC parallel encoding device it is characterised in that：Described ginseng
Examine data access managing device and include multiple level cache units connecting a coding core respectively, described level cache unit leads to
Cross a bus and be connected to a L2 cache unit, described L2 cache unit connects external memory storage further；Described bus
It is connected to the interconnection structure of described bus control unit including bus control unit and control, described interconnection structure is included for transmitting
Reference data refills refilling request channel and refilling request accessory channel and for transmitting reference data of request
Retain data channel and refill data channel.
4. reference data access management apparatus as claimed in claim 3 it is characterised in that：Described level cache unit includes
One multiport 2D buffer, described level cache unit is connected by described bus to the estimation mould of affiliated coding core
Block, described level cache unit is provided with and refills request accessory channel and retain data channel.
5. reference data access management apparatus as claimed in claim 4 it is characterised in that：Described L2 cache unit includes
Two multiport 2D buffers, bus snooping module, snoop filter, retain buffering and external reference Data access module, institute
State to retain to buffer and connect described second multiport 2D buffer and described bus snooping module respectively, described second multiport 2D delays
Storage connects described snoop filter further, and described bus snooping module also connects described snoop filter further, described
Snoop filter connects described external reference Data access module further, and described external reference Data access module connects
Described external memory storage.
6. reference data access management apparatus as claimed in claim 5 it is characterised in that：Described level cache unit passes through institute
State to retain and retain buffering described in data channel connection；Described snoop filter passes through the described request accessory channel that refills and connects institute
State level cache unit.
7. reference data access management apparatus as claimed in claim 6 it is characterised in that：One or more described refilling please
Passage is asked to connect to described bus snooping module with described second multiport 2D buffer to transmit reference data access；Described spy
Filter is listened to connect to the described request accessory channel that refills to transmit reference data access.
8. reference data access management apparatus as claimed in claim 7 it is characterised in that：Described external reference data access mould
Block connects to the described data channel that refills to transmit reference data.
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| CN110321997B (en) * | 2018-03-31 | 2021-10-19 | 赛灵思公司 | High-parallelism computing platform, system and computing implementation method |
| CN115174916A (en) * | 2021-04-01 | 2022-10-11 | Oppo广东移动通信有限公司 | Video data storage method and device, electronic equipment and readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080090238A (en) * | 2007-04-02 | 2008-10-08 | 삼성전자주식회사 | Apparatus and method for bandwidth aware motion compensation |
| CN101287126A (en) * | 2008-06-12 | 2008-10-15 | 四川虹微技术有限公司 | Rapid reading method of motion compensating data based on H.264 standard |
| CN102025992A (en) * | 2010-11-23 | 2011-04-20 | 浙江大学 | Reference-image management method for interframe predicting process in H.264 video decoding system |
| CN102710940A (en) * | 2012-06-04 | 2012-10-03 | 公安部第三研究所 | Digital signal processor (DSP) platform-based method for realizing optimization of video coding by utilizing motion estimation algorithm |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070008323A1 (en) * | 2005-07-08 | 2007-01-11 | Yaxiong Zhou | Reference picture loading cache for motion prediction |
| JP5020391B2 (en) * | 2010-02-22 | 2012-09-05 | パナソニック株式会社 | Decoding device and decoding method |
-
2013
- 2013-12-31 CN CN201310751654.3A patent/CN103729449B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080090238A (en) * | 2007-04-02 | 2008-10-08 | 삼성전자주식회사 | Apparatus and method for bandwidth aware motion compensation |
| CN101287126A (en) * | 2008-06-12 | 2008-10-15 | 四川虹微技术有限公司 | Rapid reading method of motion compensating data based on H.264 standard |
| CN102025992A (en) * | 2010-11-23 | 2011-04-20 | 浙江大学 | Reference-image management method for interframe predicting process in H.264 video decoding system |
| CN102710940A (en) * | 2012-06-04 | 2012-10-03 | 公安部第三研究所 | Digital signal processor (DSP) platform-based method for realizing optimization of video coding by utilizing motion estimation algorithm |
Non-Patent Citations (2)
| Title |
|---|
| SIMD并行运算的参考图像组织方法;李学渊;《传感器技术学报》;20060228;第19卷(第1期);第183-186页 * |
| 基于2D Cache结构的H．2***补偿访存带宽优化方法;汪文祥;《计算机研究与发展》;20120131;第49卷(第1期);第55-63页 * |
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