CN103716060B - Clock data recovery circuit - Google Patents
Clock data recovery circuit Download PDFInfo
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- CN103716060B CN103716060B CN201410020957.2A CN201410020957A CN103716060B CN 103716060 B CN103716060 B CN 103716060B CN 201410020957 A CN201410020957 A CN 201410020957A CN 103716060 B CN103716060 B CN 103716060B
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Abstract
The present invention relates to a kind of clock data recovery circuit. This clock data recovery circuit comprises: sampling module and clock recovery module; Described sampling module comprises: controlling of sampling unit and multiple sampling unit; Described multiple sampling unit, for serial data is sampled, obtains sampled data; Described controlling of sampling unit is used for controlling described multiple sampling unit and successively serial data is sampled, after described multiple sampling units are all sampled to serial data, control described multiple sampling unit and described sampling data transmitting is delivered to described clock recovery module simultaneously; The described sampled data recovered clock that described clock recovery module receives for basis.
Description
Technical field
The present invention relates to a kind of clock data recovery circuit.
Background technology
At present, in serial communication system, clock data recovery circuit (CDR) plays pass in receiverThe effect of key. Clock recovery module in clock data recovery circuit is often operated under high speed.In realization, for making clock data recovery circuit realize high transfer rate, normally by clock and data recovery mouldAfter piece is placed on the modular converter of going here and there and change. As shown in Figure 1, it is for realizing high biography in prior artThe structural representation of the clock data recovery circuit of defeated speed. Sampling module 110 is by the serial data of samplingBe sent to modular converter 130, through modular converter 130, the serial data of high transfer rate gone here and there and turned alsoAfterwards, the transfer rate of data can decrease, and so the parallel data after conversion is carried out to clock recoveryThe also corresponding reduction of operating rate of clock recovery module 120, thereby avoid clock recovery module high workloadThe realization difficulty of speed.
But because clock recovery module is to realize after modular converter, therefore whole clock data is extensiveThe system delay of compound circuit is larger, the shake in intrinsic noise, data to transmitting terminal and noise, transmissionThe degrees of tolerance of numerous unfavorable factors such as the frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of pathLower.
Summary of the invention
The object of the invention is in making clock data recovery circuit realize high transfer rate, reduceThe system delay of above-mentioned clock data recovery circuit, improves trembling in intrinsic noise to transmitting terminal, dataThe unfavorable factors such as the frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of moving and noise, transmission channelDegrees of tolerance.
The embodiment of the present invention provides a kind of clock data recovery circuit, and described clock data recovery circuit comprises:Sampling module and clock recovery module;
Described sampling module comprises: controlling of sampling unit and multiple sampling unit;
Described multiple sampling unit, for serial data is sampled, obtains sampled data;
Described controlling of sampling unit is used for controlling described multiple sampling unit and successively serial data is adoptedSample, after described multiple sampling units are all sampled to serial data, controls described multiple sampling unitDescribed sampling data transmitting is delivered to described clock recovery module simultaneously;
The described sampled data recovered clock that described clock recovery module receives for basis.
Further, described clock data recovery circuit also comprises: modular converter; Described controlling of sampling listUnit also, for after all serial data being sampled when described multiple sampling unit samplings, controls described multipleSampling unit is delivered to described modular converter by described sampling data transmitting simultaneously; Described modular converter will be for connecingThe described sampled data of receiving is converted to parallel data.
Further, the quantity of described multiple sampling units is less than the string of described modular converter and changes multiple.
Further, described clock data recovery circuit also comprises: pretreatment module; Described pretreatment mouldPiece comprises: difference input coupling circuit and transmission line balanced unit; Described pretreatment module is for receivingThe serial data that outside transmitting apparatus sends, balanced single by described difference input coupling circuit and transmission lineUnit carries out pretreatment to the serial data receiving, to the pretreated string of described sampling module output processRow data, so that described multiple sampling unit is sampled to the serial data of described pretreatment module output.
By utilizing clock data recovery circuit provided by the invention, multiple sampling units are successively to serial numberAccording to sampling, after the plurality of sampling unit is all sampled to serial data, simultaneously by sampled dataBe sent to clock recovery module, to avoid clock recovery module to be operated under two-forty. Due to clock recoveryModule is before serial-parallel conversion circuit, and therefore this clock data recovery circuit is being realized the same of high transfer rateTime, can effectively reduce the system delay of clock data recovery circuit, improve intrinsic noise to transmitting terminal,The frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of the shake of data and noise, transmission channel etc.The degrees of tolerance of unfavorable factor.
Brief description of the drawings
Fig. 1 is the structural representation of a kind of clock data recovery circuit of the prior art;
The structural representation of a kind of clock data recovery circuit that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the another kind of clock data recovery circuit that Fig. 3 provides for the embodiment of the present invention;
The structural representation of another clock data recovery circuit that Fig. 4 provides for the embodiment of the present invention.
Detailed description of the invention
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to thisInvention is described in further detail, and obviously, described embodiment is only a part of enforcement of the present inventionExample, instead of whole embodiment. Based on the embodiment in the present invention, those of ordinary skill in the art existDo not make all other embodiment that obtain under creative work prerequisite, all belong to the present invention protectionScope.
Describe the clock data recovery circuit that the embodiment of the present invention provides below in detail as an example of Fig. 2 example. As Fig. 2Shown in, the structural representation of its a kind of clock data recovery circuit providing for the embodiment of the present invention.
This clock data recovery circuit comprises: sampling module 210, clock recovery module 220 and modular converter230。
Sampling module 210 comprises: controlling of sampling unit 211 and multiple sampling unit 212.
The input of controlling of sampling unit 211 is connected with clock recovery module 220 outputs, controlling of samplingThe output of unit 211 is connected with the first input end of multiple sampling units 212 respectively. Multiple samplings are singleThe output of unit 212 is connected with modular converter 230 with clock recovery module 220 respectively.
Wherein, each sampling unit 212 in multiple sampling units 212 is identical. EachSampling unit 212 all, for serial data is sampled, obtains sampled data.
Sample to serial data successively for controlling multiple sampling units 212 in controlling of sampling unit 211,After multiple sampling units 212 are all sampled to serial data, control multiple sampling units 212 simultaneouslySampling data transmitting is delivered to clock recovery module 220 and modular converter 230.
The sampled data recovered clock that clock recovery module 220 receives for basis.
Modular converter 230 is for being converted to parallel data by the sampled data receiving.
Preferably, the quantity of multiple sampling units 212 is less than the string of modular converter 230 and changes multiple,Large to ensure the operating rate of the clock recovery module 220 in the clock data recovery circuit shown in Fig. 2The operating rate of the clock recovery module in the clock data recovery circuit shown in Fig. 1.
In a concrete example, the transfer rate of sampled data is 1.5GHz, if adopt Fig. 1 instituteThe string of the modular converter in the clock data recovery circuit showing and this clock data recovery circuit conversion are doublyNumber is 10, and clock recovery module will be operated in 150MHz so. If the clock number shown in employing Fig. 2Number according to restoring circuit and hypothesis sampling unit 212 is 3, and the string of modular converter 230 conversion are doublyNumber is 10, and clock recovery module will be operated in 500MHz so. This shows, adopting identical stringAnd while changing the modular converter of multiple, the clock data recovery circuit that the embodiment of the present invention provides is not only passableAvoid the clock recovery module to be operated in the transfer rate of sampled data, and compared to shown in Fig. 1Clock recovery module in clock data recovery circuit, its operating rate also increases.
In addition, as shown in Figure 3, the clock data recovery circuit that the embodiment of the present invention provides can also comprise:Pretreatment module 240.
The output of pretreatment module 240 is connected with the second input of multiple sampling units 212 respectively.
The serial data that this pretreatment module 240 sends for receiving external equipment, to the string receivingRow data are carried out pretreatment, to the pretreated serial data of sampling module 210 output process, so thatMultiple sampling units 212 are sampled to the serial data of pretreatment module output.
Wherein, as shown in Figure 4, pretreatment module 240 comprises: difference input coupling circuit 241 HesTransmission cable balanced unit 242. By difference input coupling circuit 241 and transmission cable balanced unit242 pairs of serial datas are carried out pretreatment, to strengthen the physics of serial data after the transmission of physical channelCharacteristic uniformity, is beneficial to post processing.
By utilizing clock data recovery circuit provided by the invention, multiple sampling units are successively to serialData are sampled, and after the plurality of sampling unit is all sampled to serial data, will sample simultaneouslyData are sent to clock recovery module, to avoid clock recovery module to be operated in the transmission speed of sampled dataUnder rate. Because clock recovery module is before serial-parallel conversion circuit, therefore this clock data recovery circuit existsWhen realizing high transfer rate, can effectively reduce the system delay of clock data recovery circuit, it is right to improveThe non-ideal factor of the intrinsic noise of transmitting terminal, the shake of data and noise, transmission channel, transmitting terminal andThe degrees of tolerance of the unfavorable factors such as the frequency difference of receiving terminal.
Above-described detailed description of the invention, carries out object of the present invention, technical scheme and beneficial effectFurther description, institute it should be understood that the foregoing is only the specific embodiment of the present invention and, the protection domain being not intended to limit the present invention, within the spirit and principles in the present invention all, institute doesAny amendment, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (2)
1. a clock data recovery circuit, is characterized in that, described clock data recovery circuit comprises:Sampling module and clock recovery module;
Described sampling module comprises: controlling of sampling unit and multiple sampling unit;
Described multiple sampling unit, for serial data is sampled, obtains sampled data;
Described controlling of sampling unit is used for controlling described multiple sampling unit and successively serial data is adoptedSample, after described multiple sampling units are all sampled to serial data, controls described multiple sampling unitDescribed sampling data transmitting is delivered to described clock recovery module simultaneously;
The described sampled data recovered clock that described clock recovery module receives for basis;
Described clock data recovery circuit also comprises: modular converter;
Described controlling of sampling unit is also for all adopting serial data when described multiple sampling unit samplingsAfter sample, control described multiple sampling unit and described sampling data transmitting is delivered to described modular converter simultaneously;
Described modular converter is for being converted to parallel data by the described sampled data receiving;
The quantity of described multiple sampling units is less than the string of described modular converter and changes multiple.
2. clock data recovery circuit according to claim 1, is characterized in that, described clock numberAlso comprise according to restoring circuit: pretreatment module;
Described pretreatment module comprises: difference input coupling circuit and transmission line balanced unit;
The serial data that described pretreatment module sends for receiving outside transmitting apparatus, defeated by described differenceEnter coupling circuit and transmission line balanced unit carries out pretreatment to the serial data receiving, adopt to describedThe output of original mold piece is through pretreated serial data, so that described multiple sampling unit is to described pretreatmentThe serial data of module output is sampled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020957.2A CN103716060B (en) | 2014-01-15 | 2014-01-15 | Clock data recovery circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020957.2A CN103716060B (en) | 2014-01-15 | 2014-01-15 | Clock data recovery circuit |
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| CN103716060A CN103716060A (en) | 2014-04-09 |
| CN103716060B true CN103716060B (en) | 2016-05-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114337708A (en) * | 2021-12-31 | 2022-04-12 | 苏州兆芯半导体科技有限公司 | Data transmission circuit, method and chip |
Citations (5)
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|---|---|---|---|---|
| WO2011004580A1 (en) * | 2009-07-06 | 2011-01-13 | パナソニック株式会社 | Clock data recovery circuit |
| CN103036670A (en) * | 2011-12-27 | 2013-04-10 | 龙迅半导体科技(合肥)有限公司 | Clock recovery circuit and parallel output circuit |
| CN103078667A (en) * | 2013-01-23 | 2013-05-01 | 杭州电子科技大学 | Low voltage differential signaling (LVDS) high-speed data transmission method based on cat-5 |
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN203708231U (en) * | 2014-01-15 | 2014-07-09 | 英特格灵芯片(天津)有限公司 | Clock data recovery circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7929644B2 (en) * | 2008-02-01 | 2011-04-19 | Panasonic Corporation | Instant-acquisition clock and data recovery systems and methods for serial communications links |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011004580A1 (en) * | 2009-07-06 | 2011-01-13 | パナソニック株式会社 | Clock data recovery circuit |
| CN103036670A (en) * | 2011-12-27 | 2013-04-10 | 龙迅半导体科技(合肥)有限公司 | Clock recovery circuit and parallel output circuit |
| CN103078667A (en) * | 2013-01-23 | 2013-05-01 | 杭州电子科技大学 | Low voltage differential signaling (LVDS) high-speed data transmission method based on cat-5 |
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN203708231U (en) * | 2014-01-15 | 2014-07-09 | 英特格灵芯片(天津)有限公司 | Clock data recovery circuit |
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| CN103716060A (en) | 2014-04-09 |
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Effective date of registration: 20190709 Address after: 100176 Beijing Daxing District Beijing Economic and Technological Development Zone Ronghua Road No. 10 Building A 9-storey 915 Patentee after: Xin Chuangzhi (Beijing) Microelectronics Co., Ltd. Address before: Room 2701-1, Building 2, Teda Service Outsourcing Park, 19 Xinhuan West Road, Binhai New Development Zone, Tianjin, 300457 Patentee before: International Green Chip (Tianjin) Co.,Ltd. |