CN103715064A - 用于防范utbb上的与接触有关的短接的方法 - Google Patents
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Abstract
经过在衬底上的掩埋氧化物上面的有源硅层向衬底中并且经过有源硅层上的任何焊盘电介质蚀刻隔离沟槽。有源硅层的横向外延向隔离沟槽中形成突出物至至少约5纳米的横向距离,并且用电介质填充隔离沟槽的在突出物周围的部分。在有源硅层的包括电介质的部分上形成凸起源极/漏极区域。作为结果,在凸起源极/漏极区域的周围穿过的未对准接触在隔离沟槽中保持从衬底的侧壁间隔开。
Description
技术领域
本发明主要地涉及制作绝缘体上硅集成电路,并且更具体地涉及避免与半导体绝缘体上硅集成电路中的衬底的与接触有关的短接。
背景技术
由于典型的基于绝缘体上硅(SOI)的晶体管制作工艺需要有限的氢氟(HF)酸预算,因此在薄掩埋氧化物(BOX)的情况下,尤其对于超薄本体和BOX(UTBB)衬底而言,可能在断片(divot)完全或者部分暴露衬底。这可能经过在浅沟槽隔离(STI)之上穿过的并且连接源极/漏极(S/D)与衬底的未对准接触引起SOI/衬底短接。由于薄BOX,因此接触蚀刻具有很有限度的余地。
因此在本领域中需要改进对由于未对准接触经过掩埋氧化物穿透所致的从源极/漏极区域到衬底的短接的防范。
发明内容
经过在衬底上的掩埋氧化物上面的有源硅层向衬底中并且经过有源硅层上的任何焊盘电介质蚀刻隔离沟槽。有源硅层的横向外延生长向隔离沟槽中形成突出物至至少约5纳米的横向距离,并且用电介质填充隔离沟槽的在突出物周围的部分。在有源硅层的包括电介质的部分上形成凸起源极/漏极区域。作为结果,在凸起源极/漏极区域的边缘周围穿过的未对准接触在隔离沟槽中保持从衬底的侧壁间隔开。
在进行以下具体描述之前,阐述贯穿本专利文献使用的某些字眼和短语的定义可以是有利的:术语“包括”及其派生词意味着包括而不限于;术语“或者”为包含意义,这意味着和/或;短语“与......关联”和“与之关联”及其派生短语可以意味着包括、在......内包括、与......互连、包含、在......内包含、连接到或者与......连接、耦合到或者与......耦合、与......可连通、与......配合、交织、并置、与......邻近、限制于或者由......限制、具有、具有......性质等;并且术语“控制器”意味着控制至少一个操作的任何设备、***或者其部分,可以在硬件、固件或者软件或者它们中的至少两项的某一组合中实施这样的设备。应当注意,无论本地还是远程都可以集中或者分布与任何特定控制器关联的功能。贯穿本专利文献提供用于某些字眼和短语的定义,本领域普通技术人员应当理解,在如果不是多数则为许多实例中,这样的定义适用于这样定义的字眼和短语的先前以及将来使用。
附图说明
为了更完整理解本公开内容及其优点,现在参照结合附图进行的以下描述,在附图中,相似标号代表相似部分。
图1描绘集成电路结构的截面图,该图示出与UTBB衬底的接触短接;
图2是根据本公开内容的一个实施例的半导体集成电路结构的部分的截面图,该结构使用侧向外延来避免与衬底的与接触有关的短接;并且
图3A至图3K是根据本公开内容的一个实施例的在使用侧向外延以避免与衬底的与接触有关的短接期间半导体集成电路的部分的截面图;并且
图4是图示根据本公开内容的一个实施例的使用侧向外延以避免与衬底的与接触有关的短接的工艺的高级流程图。
具体实施方式
本专利文献中的以下讨论的图1至图4以及用来描述本公开内容的原理的各种实施例仅为举例说明而不应以任何方式解释为限制公开内容的范围。本领域技术人员将理解,可以在任何适当布置的***中实施本公开内容的原理。
图1描绘集成电路结构的截面图,该图示出与UTBB衬底的接触短接。在图像中,竖直接触与源极/漏极区域中未对准,并且穿透薄BOX以接触在薄BOX以下的STI和衬底的侧壁二者,从而使源极/漏极与衬底短接。
图2是根据本公开内容的一个实施例的半导体集成电路结构的部分的截面图,该结构使用侧向外延来避免与衬底的与接触有关的短接。集成电路结构200包括形成有薄BOX层202和STI区域203的衬底(例如p型区域)201。在BOX层202上形成半导体(例如硅)层204,并且通过侧向外延来生长突出物205以延伸穿过BOX层202的边缘并且在STI区域203的部分之上悬置。在半导体层204上(包括在突出物205上)形成与栅极(在图2的示例中包括栅极电极、阻挡层和栅极绝缘体)和相接侧壁间隔物208(在图2中图示为包括多层)相邻的凸起源极/漏极区域206。
在接触209与相应源极/漏极区域206未对准时,接触的向下延伸至(或者甚至进入)STI区域203的部分210未接触衬底210。突出物205提供在源极/漏极区域206的边缘与衬底201的侧壁之间的横向间隔(在与STI区域203的界面)。作为结果,未出现从源极/漏极区域到衬底的短接。突出物205通过侧向外延而产生的横向距离即使对于薄BOX层202仍然允许数量随着侧向外延而显著增加的接触反应离子蚀刻(RIE)过蚀刻。
图3A至图3K是根据本公开内容的一个实施例的在使用侧向外延以避免与衬底的与接触有关的短接的工艺期间半导体集成电路的部分的截面图。图4是图示根据本公开内容的一个实施例的使用侧向外延以避免与衬底的与接触有关的短接的工艺的高级流程图。尽管仅图示晶体管区域,但是本领域技术人员将理解,在集成电路裸片上和在晶片内的许多不同裸片上为许多不同晶体管使用相同工艺并行形成相同结构。
本领域技术人员将认识到,图3A至图3K的结构尽管一般被绘制用于图示近似相对尺寸或者尺度、但是未按比例绘制。本领域技术人员还将认识到,在附图中未图示或者这里未描述用于形成集成电路的完全工艺和关联结构。取而代之,为了简化和清楚,仅描绘和描述如本公开内容特有的或者为了理解本公开内容而必需的用于形成集成电路和关联结构的工艺这么多。此外,虽然在附图中图示并且这里描述各种步骤,但是未暗示关于这样的步骤的顺序或者存在或者不存在居间步骤的限制。除非明确指定,仅出于说明的目的而而这样完成被描绘或者描述为依次的步骤而未排除如果未完全则至少部分以并行或者重叠方式实际执行相应步骤这样的可能性。
首先参照图3A,工艺400始于集成电路结构300包括掺杂半导体区域301(例如p型半导体材料)、在半导体区域301上的BOX层302、在BOX层302上形成的有源半导体层303(例如未掺杂硅)以及在有源半导体层303上形成的焊盘氧化物304和焊盘氮化物305。如图3B中所示,运用光刻和优选定向蚀刻(例如RIE)形成用于STI区域的沟槽(步骤401)。然后如图3C中所示在沟槽中沉积保形衬垫306(步骤402)。
如图3D中所示,用有机电介质层(ODL)307填充蚀刻的沟槽的剩余未填充部分(步骤403)。然后如图3E中所示,去除ODL至有源半导体层303的下边界以下(步骤404)。如图3F中所示,
去除衬垫306的在ODL307的水平面上方的部分(步骤405),并且如图3G中所示,剥离剩余ODL材料(步骤406)。然后如图3H中所示,执行侧向或者横向硅外延(步骤407)以从有源半导体层303向沟槽中生长突出物308。生长突出物308至充分横向距离以引起悬置,该悬置排除向下穿过突出物308的末端的任何传导材料与衬底301的侧壁的物理接触。然后如图3I中所示,执行沟槽内的剩余衬垫材料的可选去除(步骤408)。
然后如图3J中所示,用电介质309填充STI沟槽并且执行化学机械抛光(CMP)以平坦化集成电路结构300的上表面(步骤409)。然后如图3K中所示,从有源半导体材料303的表面去除焊盘氧化物304和焊盘氮化物305(步骤410)。然后可以如以上描述的那样形成栅极结构、侧壁间隔物和凸起源极/漏极区域、继而为与凸起源极/漏极区域中的至少一个区域的接触。
本公开内容运用有源图案化和RIE以在与STI区域的界面掩蔽硅。硅的横向外延仅在未掩蔽区域上、在这一情况下仅在有源区域周围形成。仅约5纳米(nm)的横向外延足以防范在源极/漏极区域与衬底之间的接触短接。本公开内容的解决方案提供良好均匀性和厚度控制,并且在仍然保持相同隔离性质之时用外延扩大有源区域。如果有则仅需现有制作工艺的少量修改。
虽然已经用一个示例实施例描述本公开内容,但是可以让本领域技术人员想到各种改变和修改。旨在于本公开内容涵盖如落入所附权利要求的范围内的这样的改变和修改。
Claims (20)
1.一种方法,包括:
经过在衬底上的薄掩埋氧化物上面的有源半导体层形成隔离沟槽;并且
执行所述有源半导体层的横向外延生长以形成所述有源半导体层的向所述隔离沟槽中延伸的突出物。
2.根据权利要求1所述的方法,其中向所述隔离沟槽中形成所述突出物至如下横向距离,所述横向距离足以防止在沿着所述突出物穿过的传导材料与所述衬底的侧壁之间的接触。
3.根据权利要求2所述的方法,其中形成所述突出物至约5纳米(nm)的横向距离。
4.根据权利要求1所述的方法,还包括:
在生长所述突出物之后,用电介质填充所述隔离沟槽。
5.根据权利要求1所述的方法,还包括:
经过所述有源半导体层上的焊盘氧化物和焊盘氮化物形成所述隔离沟槽;并且
在所述有源半导体层的被所述隔离沟槽暴露的边缘生长所述突出物。
6.根据权利要求1所述的方法,还包括:
在所述有源半导体层的包括所述突出物的部分上形成源极/漏极区域。
7.根据权利要求1所述的方法,还包括:
在所述隔离沟槽中形成保形衬垫;
用有机电介质填充所述隔离沟槽的未填充部分;
去除所述有机电介质至所述有源半导体层以下的水平面;
蚀刻所述衬垫至所述有机电介质的所述水平面;并且
从所述隔离沟槽剥离任何剩余有机电介质。
8.根据权利要求7所述的方法,还包括:
在生长所述突出物之后,去除所述衬垫的在所述隔离沟槽中剩余的任何部分。
9.一种集成电路结构,包括:
经过在衬底上的薄掩埋氧化物上面的有源半导体层形成的隔离沟槽;以及
所述有源半导体层的向所述隔离沟槽中延伸的横向外延生长区域。
10.根据权利要求9所述的集成电路结构,其中所述横向外延生长区域向所述隔离沟槽中突出至如下横向距离,所述横向距离足以防止在沿着所述横向外延生长区域穿过的传导材料与所述衬底的侧壁之间的接触。
11.根据权利要求10所述的集成电路结构,其中所述横向外延生长区域突出至约5纳米(nm)的横向距离。
12.根据权利要求9所述的集成电路结构,还包括:
电介质,所述电介质填充所述隔离沟槽的在所述横向外延生长区域周围的部分。
13.根据权利要求12所述的集成电路结构,其中填充所述隔离沟槽的在所述横向外延生长区域周围的部分的所述电介质接触所述衬底的侧壁。
14.根据权利要求9所述的集成电路结构,还包括:
在所述有源半导体层上的焊盘氧化物和焊盘氮化物,所述隔离沟槽经过所述焊盘氧化物和所述焊盘氮化物延伸,其中所述横向外延生长从所述有源半导体层的被所述隔离沟槽暴露的边缘突出。
15.根据权利要求9所述的集成电路结构,还包括:
在所述有源半导体层的包括所述横向外延生长区域的部分上形成的源极/漏极区域。
16.根据权利要求9所述的集成电路结构,还包括:
在所述隔离沟槽中的保形衬垫;以及
有机电介质,所述有机电介质填充所述隔离沟槽的未填充部分至所述有源半导体层以下的水平面。
17.一种方法,包括:
经过在衬底上的薄掩埋氧化物上面的有源硅层并且经过所述有源硅层上的电介质形成多个隔离沟槽;并且
使用横向外延从所述隔离沟槽暴露的边缘生长所述有源硅层以向所述隔离沟槽中的每个隔离沟槽中突出。
18.根据权利要求17所述的方法,还包括:
生长所述有源硅层以向所述隔离沟槽中的每个隔离沟槽中突出至至少约5纳米(nm)的横向距离。
19.根据权利要求17所述的方法,还包括:
在所述有源硅层的包括向所述隔离沟槽中的每个隔离沟槽中的突出物的部分上形成源极/漏极区域。
20.根据权利要求17所述的方法,还包括:
用电介质填充所述隔离沟槽的在所述有源硅层的所述突出物周围的部分。
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CN110211882A (zh) * | 2014-12-31 | 2019-09-06 | 意法半导体公司 | 制作增强utbb fdsoi器件的方法和结构 |
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US8987070B2 (en) * | 2012-09-12 | 2015-03-24 | International Business Machines Corporation | SOI device with embedded liner in box layer to limit STI recess |
JP6867188B2 (ja) | 2017-02-27 | 2021-04-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US10943814B1 (en) | 2019-08-21 | 2021-03-09 | Globalfoundries U.S. Inc. | Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through |
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US20140099769A1 (en) | 2014-04-10 |
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