CN103701376A - Current attenuation mode control circuit of motor drive chip - Google Patents
Current attenuation mode control circuit of motor drive chip Download PDFInfo
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- CN103701376A CN103701376A CN201310603683.5A CN201310603683A CN103701376A CN 103701376 A CN103701376 A CN 103701376A CN 201310603683 A CN201310603683 A CN 201310603683A CN 103701376 A CN103701376 A CN 103701376A
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Abstract
A current attenuation mode detection circuit of a motor drive chip comprises a current attenuation time control circuit, an external parallel connection circuit and a digital logic control circuit, wherein the current attenuation time control circuit comprises a plurality of NMOS (N-channel Metal Oxide Semiconductor) transistors, a plurality of PMOS (P-channel Metal Oxide Semiconductor) transistors, a core circuit and a current mirror structure, wherein the external parallel connection circuit includes a capacitor CT and a resistor RT, and is connected with the current attenuation time control circuit; the digital logic control circuit includes a comparer, a latch, and a logic gate circuit; the input signal of the digital logic control circuit is the output signals of both the current attenuation time control circuit and the external parallel connection circuit; the output switch signal of the digital logic control circuit is still fed back to the current attenuation time control circuit; the current attenuation time depends on the CT and the RT; the fast attenuation time and the slow attenuation time are controlled by the current attenuation time control circuit and the digital logic control circuit together. The current attenuation mode detection circuit provided by the invention realizes switching in intelligent control between current rise process and current attenuation process according to motor operating speed.
Description
Technical field
The present invention relates to the Current Control of motor drive ic, relate in particular to a kind of control of decay mode of motor drive ic.
Background technology
Stepping motor is that first stepping motor part is controlled in a kind of open loop that changes electric impulse signal into angular displacement or displacement of the lines.When step actuator receives after pulse signal, with regard to Driving Stepping Motor, by the direction of setting, rotate a fixing angle, i.e. step angle, the rotation of stepping motor is that the angle of fixing is moved step by step.Stepping motor can pass through control impuls number pilot angle displacement, to reach the object of accurate location, can pass through speed and the acceleration of control impuls FREQUENCY CONTROL electric machine rotation, to reach the object of speed governing simultaneously.
At present, stepping motor adopts electric current close classification to segment to step angle substantially.The current point obtaining after electric current in motor coil is discrete according to sine wave, as segmentation point, when the electric current of motor coil has reached after the segmentation point of setting, is controlled motor coil electric current by circuit and is entered attenuation process.Otherwise stepping motor will angle of arrival overshoot consequence, cause the bad phenomenon such as stepping motor location is inaccurate, and running is not steady.And different according to the speed of service of stepping motor, the decay mode of taking is respective change also.Decay mode is divided three classes: fast evanescent mode, slow evanescent mode and mixing evanescent mode.
The stepping motor that fast evanescent mode is applicable to run up; And slow evanescent mode is applicable to the stepping motor of low-speed running.Compared to fast evanescent mode and slow evanescent mode, when requiring, stepping motor operation vibrations are little, noise is when low, need to adopt and mix evanescent mode, and fast evanescent mode and slow evanescent mode form jointly.Therefore stepper motor driving circuit needs to detect in real time the speed of motor operation, otherwise by telling, is reduced to after low speed when the motor speed of service, still adopts fast evanescent mode can cause motor unable, in the time of seriously, there will be and loses step, step-out phenomenon; When the stepping motor speed of service is increased at a high speed by low speed after, still adopt slow evanescent mode will cause motor strenuous vibration simultaneously, send the situation of a large amount of noises.
Therefore, those skilled in the art is devoted to develop a kind of current detection circuit that stepping motor drives chip that is applicable to, to reach rising, the attenuation process of electric current in better control motor coil, according to the fast evanescent mode of selection of the speed of service intelligence of stepping motor, slow evanescent mode and mixing evanescent mode, improved the particularly performance of stepping motor operation of motor simultaneously.
Summary of the invention
Because the above-mentioned defect of prior art, technical problem to be solved by this invention is to provide a kind of decay mode testing circuit of motor drive ic, to reach rising and the attenuation process of electric current in control step motor coil, the evanescent mode of while intelligent selection electric current.
For achieving the above object, the invention provides a kind of decay mode testing circuit of motor drive ic, it is characterized in that, comprise down slope time control circuit, Digital Logic control circuit and external parallel circuits;
Described down slope time control circuit comprises some PMOS pipes, some NMOS pipes, core circuit and current-mirror structure;
Described core circuit comprises bipolar transistor (Q0), bipolar transistor (Q1), bipolar transistor (Q2), bipolar transistor (Q3), resistance (R0), resistance (R1), resistance (R2) and resistance (R3); The collector electrode of described bipolar transistor (Q0) is connected to power supply V
dDupper, a side of described bipolar transistor (Q0) base stage is by described resistance (R0) and described PMOS pipe (MP5) and described power supply V
dDbe connected, the opposite side of described bipolar transistor (Q0) base stage is managed (MN1) with described NMOS and is connected with the emitter of described bipolar transistor (Q0) by described resistance (R1), described resistance (R2); The base stage of described bipolar transistor (Q1) is connected with the emitter of described bipolar transistor (Q2), and the emitter of described bipolar transistor (Q1) is connected with the emitter of described bipolar transistor (Q3) by described resistance (R3); Between the base stage of described bipolar transistor (Q2) and collector electrode, by described resistance (R2), be connected; Between the base stage of described bipolar transistor (Q3) and collector electrode, by some NMOS pipes, be connected; Enable signal
grid by described PMOS pipe (MP5) accesses described down slope time control circuit;
Described current-mirror structure comprises PMOS pipe (MP0), PMOS pipe (MP1), PMOS pipe (MP2), PMOS pipe (MP3) and PMOS pipe (MP4), and the grid of the grid of described PMOS pipe (MP0), the grid of described PMOS pipe (MP1), the grid of described PMOS pipe (MP2), described PMOS pipe (MP3) and the grid of described PMOS pipe (MP4) are all connected on bias current Ibias; The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of described PMOS pipe (MP0), described PMOS pipe (MP1), described PMOS pipe (MP2), described PMOS pipe (MP3) and described PMOS pipe (MP4) is all connected to described power supply V
dDon; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described PMOS pipe (MP0), described PMOS pipe (MP1), described PMOS pipe (MP2), described PMOS pipe (MP3) is connected with described core circuit with the drain electrode that described PMOS manages (MP4); And output voltage V between the drain electrode of managing (MN4) at drain electrode and the described NMOS of described PMOS pipe (MP3)
a, at drain electrode and the described NMOS of described PMOS pipe (MP4), manage output voltage V between (MN5)
b;
Described external parallel circuits is connected between the drain electrode and source electrode of described NMOS pipe (MN6), comprises resistance (R
t) and electric capacity (C
t), described resistance (R
t) and described electric capacity (C
t) be parallel join, in drain electrode and the described external parallel circuits junction output voltage V of described NMOS pipe (MN6)
c;
Described Digital Logic control circuit comprises comparator, latch and logic gates, and the input signal of described Digital Logic control circuit is respectively deamplification, external voltage V
pFDwith described output voltage V
a, V
band V
c, described output voltage V
cby described comparator and external voltage V
pFDrelatively, result is outputed to driver module; Described output voltage V
abe input in described latch described input voltage V
bfirst pass through described logic gates with described deamplification, then be input in described latch; From a signal part for described latch output, as exchange signal (switch) output, a part is exported to described Drive module in addition; Described exchange signal (switch) is by described PMOS(MP8) grid accesses described down slope time control circuit.
Further, the resistance (R in described external parallel circuits
t) resistance value between 12k Ω-100k Ω.
Further, the electric capacity (C in described external parallel circuits
t) capacitance between 470pF-1500pF.
Further, when described output voltage V
awhen low level, the coil current of motor is in ascent stage, when the output voltage V of described down slope time control circuit
awhen high level, the coil current of motor is in the decling phase.
Further, when described output voltage V
bwhen low level, described deamplification is kept; When described output voltage V
bin high level, be that described deamplification is shielded.
Further, when described output voltage V
cwhen low level, motor coil electric current is in the slow decling phase, when described output voltage V
cwhen high level, motor coil electric current is in the fast decling phase.
Further, the down slope time of motor is t
decay=R
tc
t, described down slope time comprises that decline soon time and electric current of electric current declines the time slowly.
Further, as described external voltage V
pFD?
scope in time, according to the output of described Digital Logical Circuits, the decay mode of described driver module motor is set to mix evanescent mode, and the time of declining soon of described electric current is t
fD=R
tc
tln (0.6V
dD/ V
pFD), the time of declining slowly of described electric current is t
sD=t
decay-t
fD.
Further, as described external voltage V
pFD?
scope in be that according to the output of described Digital Logical Circuits, the decay mode of described driver module motor is set to fast evanescent mode, and the time of declining soon of described electric current is t
fD=t
decay.
Further, as described external voltage V
pFD?
scope time, according to the output of described Digital Logical Circuits, the decay mode of described driver module motor is set to slow evanescent mode, and the time of declining slowly of described electric current is t
sD=t
decay.
Further, the PTAT electric current that described bias current Ibias is band-gap reference (Proportional To Absolute Temperature electric current).
The decay mode control circuit of a kind of motor drive ic of the present invention has been controlled motor, particularly rising, the attenuation process of electric current in stepping motor coil; Completed according to the control Current rise of motor speed of service intelligence and the switching of current decay process the selection of carrying out intelligently fast evanescent mode, slow evanescent mode and mixing three kinds of patterns of evanescent mode.
Below with reference to accompanying drawing, the technique effect of design of the present invention, concrete structure and generation is described further, to understand fully object of the present invention, feature and effect.
Accompanying drawing explanation
Fig. 1 is down slope time control circuit and the external parallel circuits schematic diagram of the decay mode testing circuit of a kind of motor drive ic of the present invention;
Fig. 2 is the Digital Logic control circuit schematic diagram of the decay mode testing circuit of a kind of motor drive ic of the present invention.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are elaborated: the present embodiment is implemented under with technical solution of the present invention prerequisite, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
The decay mode testing circuit of a kind of motor drive ic of the present invention comprises: down slope time control circuit, external parallel circuits and Digital Logic control circuit three parts, wherein specifically as shown in Figure 1, Digital Logic control circuit specifically as shown in Figure 2 for down slope time control circuit and external parallel circuits.
As shown in Figure 1, down slope time control circuit comprises some PMOS pipes, some NMOS pipes, core circuit and current-mirror structure.Enable signal
by the grid access down slope time control circuit of described PMOS pipe MP5; Exchange signal switch passes through PMOS(MP8) grid access down slope time control circuit.External parallel circuits comprises capacitor C
tand resistance R
t, capacitor C
tand resistance R
tbe connected in parallel.
The core circuit of down slope time control circuit comprises: bipolar transistor Q0, bipolar transistor Q1, bipolar transistor Q2, bipolar transistor Q3, resistance R 0, resistance R 1, resistance R 2 and resistance R 3.The collector electrode of bipolar transistor Q0 is connected to power supply V
dDupper, base stage one side is by resistance R 0 and PMOS pipe MP5 and power supply V
dDconnect, the opposite side of base stage is connected with the emitter of oneself by resistance R 1, resistance R 2 and NMOS pipe MN1.The base stage of bipolar transistor Q1 is connected with the emitter of bipolar transistor Q2, and emitter is connected with the emitter of bipolar transistor Q3 by resistance R 3, and collector electrode is connected with the current-mirror structure that MP7 forms with PMOS pipe MP6.The base stage of bipolar transistor Q2 is connected by resistance R 2 with collector electrode, and emitter is connected with the drain electrode of PMOS pipe MP2 with the base stage of bipolar transistor Q1 respectively.Between the base stage of bipolar transistor Q3 and collector electrode, by some NMOS pipes, be connected, emitter is connected with the emitter of bipolar transistor Q1 by R3.
Current-mirror structure comprises PMOS pipe MP0, PMOS pipe MP1, PMOS pipe MP2, PMOS pipe MP3 and PMOS pipe MP4, and the grid of the grid of PMOS pipe MP0, PMOS pipe MP1, the grid of PMOS pipe MP2, the grid of PMOS pipe MP3 and the grid of PMOS pipe MP4 are all connected on bias current Ibias; The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of PMOS pipe MP0, PMOS pipe MP1, PMOS pipe MP2, PMOS pipe MP3 and PMOS pipe MP4 is all connected to power supply V
dDon; The drain electrode of the drain electrode of the drain electrode of the drain electrode of PMOS pipe MP0, PMOS pipe MP1, PMOS pipe MP2, PMOS pipe MP3 is connected with core circuit with the drain electrode of PMOS pipe MP4.In a preferred embodiment of the present invention, bias current adopts the PTAT electric current of band-gap reference.
External parallel circuits comprises capacitor C in parallel
tand resistance R
t, external parallel circuits is connected between the drain electrode and source electrode of the NMOS pipe MN6 in down slope time control circuit.In a preferred embodiment of the present invention, resistance R
tresistance value between 12k Ω-100k Ω, capacitor C
tcapacitance between 470pF-1500pF.
In down slope time control circuit and external parallel circuits, output voltage V between the drain electrode of PMOS pipe MP3 and the drain electrode of NMOS pipe MN4
a, at drain electrode and the NMOS of PMOS pipe MP4, manage output voltage V between MN5 drain electrode
b, in the NMOS pipe drain electrode of MN6 and the junction output voltage V of external parallel circuits
c.
Digital Logic control circuit specifically as shown in Figure 2, comprises comparator, latch and logic gates.V
a, V
b, V
c, deamplification and external voltage V
pFDit is the input signal of Digital Logic control circuit.V
abe input in latch V
bfirst through logic gates, process with deamplification, then be input in latch, from a signal part for latch output, as exchange signal switch output, a part is exported to Drive module in addition.V
cand V
pFDcommon input comparator compares, and finally comparative result is outputed to Drive module after treatment.The exchange signal switch of Digital Logic control circuit output is exactly the PMOS(MP8 that is input to down slope time control circuit) the exchange signal switch of grid.
The present invention is the resistance R according to external parallel circuits
tand capacitor C
tsize, decide current of electric t die-away time
decay, t wherein
decay=R
tc
t.T die-away time of electric current
decayaccording to evanescent mode, be divided into the time t that declines soon
fDslowly time t declines
sD.
As shown in Figure 1, work as enable signal
be set to low level, PMOS pipe MP5 conducting so, so resistance R 0, resistance R 1 and 2 couples of voltage V of resistance R
ddcarry out dividing potential drop, the base voltage of bipolar transistor Q0 is
the base voltage of bipolar transistor Q2 is
When bipolar transistor Q1 conducting, the collector current of Q1, through PMOS pipe MP6, MP7 current mirror and NMOS pipe MN3, MN4 current mirror mirror image, makes voltage V
aby the collector current of Q1, drawn as low level, now, the coil current of motor is in ascent stage.Otherwise NMOS manages MN4 in cut-off state, V
afor high level, now the coil current of motor is in the decling phase.In like manner can obtain, when bipolar transistor Q3 conducting, V
bvoltage by the collector current of bipolar transistor Q3, drawn as low level, now keep deamplification; Otherwise, V
bfor high level, shielding attenuation signal now.
When exchange signal switch becomes low level, PMOS pipe MP8 conducting, power supply V
dDby PMOS, manage MP8 to the capacitor C on external parallel circuits
tcharge, i.e. V now
craise gradually, work as V
crise to
time, bipolar transistor Q3 conducting, V
bfor low level, keep deamplification, and V
adue to not conducting of bipolar transistor Q1, V
afor high level, coil current is in the decling phase.Otherwise, work as V
cdrop to
time, bipolar transistor Q1 conducting, V
astep-down level, coil current is in ascent stage, and now not conducting of bipolar transistor Q3, V
bfor high level, shielding attenuation signal.
In Digital Logic control circuit, V
cby comparator and external voltage V
pFDvoltage is compared, and finally exports to the turn-on and turn-off that driver module is controlled motor drive ic power tube.V
abe input in latch V
balso be input in latch through gate with deamplification, finally control exchange signal switch, and exchange signal switch is turned back in down slope time control circuit.
By as above analyzing, can draw:
When
time, decay mode is slow evanescent mode, the time of declining is t to electric current slowly
sD=t
decay;
When
time, decay mode is fast evanescent mode, the time of declining is t to electric current soon
fD=t
decay;
When
time, decay mode is for mixing evanescent mode, and the time of declining soon of electric current is t
fD=R
tc
tln (0.6V
dD/ V
pFD), the time of declining slowly of electric current is t
sD=t
decay-t
fD.
Further, using and mix evanescent mode and analyze as embodiment:
The initial value of exchange signal switch in down slope time control circuit is made as to low level, V
ainitial value be high level, V
binitial value be low level, V
cinitial value be high level.Work as deamplification, when high level pulse signal arrives, through Digital Logic control circuit, exchange signal switch becomes high level, and now PMOS pipe MP8 pipe cut-off, due to the capacitor C of external parallel circuits
ton electric charge pass through resistance R
tdischarge V
ccurrent potential start to decline, the emitter voltage of bipolar transistor Q3 reduces simultaneously, Q3 cut-off, V
bcurrent potential rises, and becomes high level; And bipolar transistor Q1 is because the voltage of emitter is greater than base voltage, Q1 is also in cut-off state, V
abe still high level, during this period of time,
the decay of electric current is in the quick decling phase, and the time of declining is t to electric current soon
fD=R
tc
tln (0.6V
dD/ V
pFD).
Work as V
cdrop to and compare V
pFDafter low, comparator output switching activity, becomes high level from low level, and process Digital Logic control circuit is to driver module output signal with power ratio control switching tube, and now coil current will enter the pattern that declines slowly, V
akeep high level, V
bkeep high level, exchange signal switch keeps high level.During this period of time,
the decay of electric current is in decling phase at a slow speed, and the time of declining slowly of electric current is t
sD=t
decay-t
fD.
Work as V
ccontinue to drop to
after, bipolar transistor Q1 conducting, V
abecome low level, exchange signal switch becomes low level, PMOS pipe MP8 conducting again, V
cpoint voltage starts to rise.Represent that coil current decays process finishes.
At V
cbetween the rising stage, in order to prevent that the burr signal producing from carrying out false triggering to circuit, need to shield deamplification when power transistor switch state switches.Shown in Fig. 2, voltage V
cv between the rising stage
bkeep high level, deamplification is played to shielding action.
Work as V
crise to
after, circuit completes one-period operation, and each signal condition is returned to initial value, waits for the arrival of next deamplification.
More than describe preferred embodiment of the present invention in detail.The ordinary skill that should be appreciated that this area just can design according to the present invention be made many modifications and variations without creative work.Therefore, all technical staff in the art, all should be in the determined protection range by claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (9)
1. a decay mode testing circuit for motor drive ic, is characterized in that, comprises down slope time control circuit, Digital Logic control circuit and external parallel circuits;
Described down slope time control circuit comprises some PMOS pipes, some NMOS pipes, core circuit and current-mirror structure; Enable signal
grid by described PMOS pipe (MP5) accesses described down slope time control circuit;
Described core circuit comprises bipolar transistor (Q0), bipolar transistor (Q1), bipolar transistor (Q2), bipolar transistor (Q3), resistance (R0), resistance (R1), resistance (R2) and resistance (R3); The collector electrode of described bipolar transistor (Q0) is connected to power supply V
dDupper, a side of described bipolar transistor (Q0) base stage is by described resistance (R0) and described PMOS pipe (MP5) and described power supply V
dDbe connected, the opposite side of described bipolar transistor (Q0) base stage is managed (MN1) with described NMOS and is connected with the emitter of described bipolar transistor (Q0) by described resistance (R1), described resistance (R2); The base stage of described bipolar transistor (Q1) is connected with the emitter of described bipolar transistor (Q2), and the emitter of described bipolar transistor (Q1) is connected with the emitter of described bipolar transistor (Q3) by described resistance (R3); Between the base stage of described bipolar transistor (Q2) and collector electrode, by described resistance (R2), be connected; Between the base stage of described bipolar transistor (Q3) and collector electrode, by some NMOS pipes, be connected;
Described current-mirror structure comprises PMOS pipe (MP0), PMOS pipe (MP1), PMOS pipe (MP2), PMOS pipe (MP3) and PMOS pipe (MP4), and the grid of the grid of described PMOS pipe (MP0), the grid of described PMOS pipe (MP1), the grid of described PMOS pipe (MP2), described PMOS pipe (MP3) and the grid of described PMOS pipe (MP4) are all connected on bias current Ibias; The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of described PMOS pipe (MP0), described PMOS pipe (MP1), described PMOS pipe (MP2), described PMOS pipe (MP3) and described PMOS pipe (MP4) is all connected to described power supply V
dDon; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described PMOS pipe (MP0), described PMOS pipe (MP1), described PMOS pipe (MP2), described PMOS pipe (MP3) is connected with described core circuit with the drain electrode that described PMOS manages (MP4); And output voltage V between the drain electrode of managing (MN4) at drain electrode and the described NMOS of described PMOS pipe (MP3)
a, output voltage V between the drain electrode of described PMOS pipe (MP4) and the drain electrode of described NMOS pipe (MN5)
b;
The described NMOS that described external parallel circuits is connected to described down slope time control circuit manages between the drain electrode and source electrode of (MN6), comprises resistance (R
t) and electric capacity (C
t), described resistance (R
t) and described electric capacity (C
t) be parallel join, the drain electrode of described NMOS pipe (MN6) with described in the parallel circuits junction output voltage V that finishes
c; Resistance (R in described external parallel circuits
t) resistance value between 12k Ω-100k Ω; Electric capacity (C in described external parallel circuits
t) capacitance between 470pF-1500pF;
Described Digital Logic control circuit comprises comparator, latch and logic gates, and the input signal of described Digital Logic control circuit is respectively deamplification, external voltage V
pFDwith described output voltage V
a, V
band V
c, described output voltage V
cby described comparator and external voltage V
pFDrelatively, result is outputed to driver module; Described output voltage V
abe input in described latch described input voltage V
bfirst pass through described logic gates with described deamplification, then be input in described latch; From a signal part for described latch output, as exchange signal (switch) output, a part is exported to described Drive module in addition; Described exchange signal (switch) is by described PMOS(MP8) grid accesses described down slope time control circuit.
2. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 1, wherein, when described output voltage V
awhen low level, the coil current of motor is in ascent stage, when described output voltage V
awhen high level, the coil current of motor is in the decling phase.
3. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 1, wherein, when described output voltage V
bwhen low level, described deamplification is kept; When described output voltage V
bin high level, be that described deamplification is shielded.
4. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 1, wherein, when described output voltage V
cwhen low level, motor coil electric current is in the slow decling phase, when described output voltage V
cwhen high level, motor coil electric current is in the fast decling phase.
5. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 1, wherein, the down slope time of motor is t
decay=R
tc
t, described down slope time comprises that decline soon time and electric current of electric current declines the time slowly.
6. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 5, wherein, as described external voltage V
pFD?
scope in time, according to the output of described Digital Logical Circuits, the decay mode of described driver module motor is set to mix evanescent mode, and the time of declining is t to described electric current soon
fD=R
tc
tln (0.6V
dD/ V
pFD), the time of declining is t to described electric current slowly
sD=t
decay-t
fD.
7. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 5, wherein, as described external voltage V
pFD?
scope in time, according to the output of described Digital Logical Circuits, the decay mode of described driver module motor is set to fast evanescent mode, and the time of declining is t to described electric current soon
fD=t
decay.
8. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 5, wherein, as described external voltage V
pFD?
scope time, according to the output of described Digital Logical Circuits, the decay mode of described driver module motor is set to slow evanescent mode, and the time of declining is t to described electric current slowly
sD=t
decay.
9. the decay mode testing circuit of a kind of motor drive ic as claimed in claim 1, wherein, the PTAT electric current that described bias current Ibias is band-gap reference.
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Cited By (5)
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| CN106067748A (en) * | 2015-04-24 | 2016-11-02 | 罗姆股份有限公司 | Motor drive and the driving method of motor drive |
| CN104242755B (en) * | 2013-06-06 | 2017-04-12 | 三垦电气株式会社 | Motor driving device and power module |
| CN107834946A (en) * | 2017-10-09 | 2018-03-23 | 深圳市巴丁微电子有限公司 | The PWM current driving methods and device of evanescent mode are mixed using dynamic |
| CN108574445A (en) * | 2017-03-13 | 2018-09-25 | 茂达电子股份有限公司 | Motor driving circuit |
| CN108631664A (en) * | 2017-03-17 | 2018-10-09 | 茂达电子股份有限公司 | Motor driving circuit |
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| CN101246366A (en) * | 2008-03-10 | 2008-08-20 | 芯硕半导体（中国）有限公司 | Three-axis stepping motor control platform |
| CN101741304A (en) * | 2010-01-21 | 2010-06-16 | 西北工业大学 | CPLD-based multi-subdivision high-speed constant-torque controller of two-phase hybrid stepping motor |
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