CN103699358A - Rapid modular square arithmetic circuit applicable to great number - Google Patents
Rapid modular square arithmetic circuit applicable to great number Download PDFInfo
- Publication number
- CN103699358A CN103699358A CN201310653889.9A CN201310653889A CN103699358A CN 103699358 A CN103699358 A CN 103699358A CN 201310653889 A CN201310653889 A CN 201310653889A CN 103699358 A CN103699358 A CN 103699358A
- Authority
- CN
- China
- Prior art keywords
- circuit
- input
- data selector
- output
- alternative data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Complex Calculations (AREA)
Abstract
The invention discloses a rapid modular square arithmetic circuit applicable to great number. The circuit structurally comprises a head and tail-removed displacement value complementing circuit, two bi-input AND gate arrays, a first-level carry save adder (CSA) structure, a first-level full adder (FA) unit and a series of scanning registers. According to the circuit, the square arithmetic is expended according to the polynomial multiplication, the original m partial product summation is compressed into m/2 partial product summation, and the accumulation is preformed from the high order to the low order, so that the square arithmetic time can be reduced into a half as long as that of the original time.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, be specifically related to a kind of Fast Modular square operation circuit that is applicable to large number.
Background technology
At present, the scheme conventionally adopting for the researchs of large several squares is Montgomery algorithm, this algorithm square spent time of calculating process and the length of input data be directly proportional.
In view of this, be necessary to study a kind of new square algorithm, by the optimization to the partial product of calculating process, reduce the number of times of partial product, thereby reduce by the working time of whole square, address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of Fast Modular square operation circuit that is applicable to large number that can effectively reduce the computing module-square time.
In order to achieve the above object, the technical solution adopted in the present invention is: comprising that shift circuit left, m position alternative data selector array, m position two input gate arrays, m bit position are long-pending produces circuit, full adder FA array, m+3 bit scan register, yojan circuit and with the displacement benefit value circuit that leaves out the beginning and the end of the johnson counter of a m/2 position; The square operation input item A that is input as m position of the displacement benefit of leaving out the beginning and the end value circuit, being output as the output Q of m bit register in the displacement benefit value circuit that leaves out the beginning and the end, the output Qc of register in the johnson ring shift counter of m/2 position that leaves out the beginning and the end in displacement benefit value circuit of output simultaneously; The low m/2 position that is input as square input item A of shift circuit left; The long-pending input end that produces circuit of m bit position is connected with the output terminal of m position two input gate arrays, and the long-pending output terminal that produces circuit of m bit position is connected with the input end of full adder FA array, and full adder FA array is connected with brief circuit by m+3 bit scan register; Wherein, 160≤m≤15360.
Described shift circuit left, when each rising edge clock arrives, in shift circuit, the value of register moves to left one left, and low level zero padding, the output terminal of most significant digit register is drawn simultaneously, is defined as AL.
Described m position alternative data selector array comprises m position alternative data selector, and wherein the control signal of the alternative data selector of m position is produced by the Johnson ring shift counter output Qc leaving out the beginning and the end in displacement benefit value circuit; Wherein, the second numerical value that the control signal of first alternative data selector and second alternative data selector is Qc, the 3rd bit value that the control signal of the 3rd alternative data selector and the 4th alternative data selector is Qc, by that analogy, the m/2 bit value that the signal processed of m-3 position alternative data selector and m-2 position alternative data selector is Qc, the signal processed of m-1 position alternative data selector and m position alternative data selector is set to 1; " 0 " termination of m position alternative data selector is the output AL of shift circuit left, the leave out the beginning and the end most significant digit of output Q of displacement benefit value circuit of " 1 " termination.
Port in the input end of two inputs of described m position and door and corresponding being connected of m position of m position alternative data selector array, another input end connects as follows:
First lowest order that is connected the output Q of the displacement benefit value circuit that leaves out the beginning and the end with door, second is connected the second of Q with door, and by that analogy, m-1 position is connected the radix-minus-one complement of an inferior high position of Q with door, m position and an inferior high position that is connected Q; M position gate array is output as the long-pending output of final m bit position.
The long-pending circuit that produces of described m bit position, after partial product produces, send in m full adder FA as input, wherein, the carry input of the full adder of lowest order connects the output of an alternative data selector, " 0 " end of alternative data selector connects the lowest order Q[0 of the m position output Q of the displacement benefit value circuit that leaves out the beginning and the end], " 1 " end input zero, the control signal of alternative data selector is the second Qc[1 of the output Qc of Johnson ring shift counter in displacement benefit value circuit of leaving out the beginning and the end]; The carry input of all the other full adders is the carry output from low level.
Described m position full adder FA exports with position input end " 0 " end of sending into scan register; " 1 " end of lowest order scan register connects the output terminal of an alternative data selector, the input of alternative data selector " 0 " end connects the lowest order A[0 of square operation input item A], " 1 " end input zero, the control signal of alternative data selector is Sel, and lowest order and the most significant digit phase XOR of this signal output terminal Qc of Johnson counter in the displacement benefit value circuit that leaves out the beginning and the end produce; " 1 " end input zero of second scan register, " 1 " end input one-bit full addres of the 3rd bit scan register be FA's and position, " 1 " end input second full adder of the 4th bit scan register be FA's and position, by that analogy, " 1 " end input m position full adder of m+2 bit scan register be FA's and position, the carry output of " 1 " end input m position full adder FA of m+3 bit scan register.
The output terminal of described m+3 bit scan register is sent into yojan circuit and is carried out yojan.
Compared with prior art, the present invention has following beneficial effect:
It is m/2 by m Partial product compression that partial product of the present invention produces circuit, final square operation adopts from a high position to low bit arithmetic, first partial product produces and backwardly moves to left two, after sending into the yojan of yojan circuit, be added with the second part is long-pending, complete one-accumulate, by that analogy, until m/2 partial product produces, complete m/2 time and add up, finally complete computing module-square.
Further, the present invention presses polynomial multiplication by square operation and launches, and original m partial product summation is compressed into m/2 partial product and sues for peace, and adds up from a high position to low level, so square operation time decreased is original half.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention;
Fig. 2 is the electrical block diagram of the cumulative and yojan of this partial product.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further detailed explanation:
Referring to Fig. 1 and Fig. 2, the present invention includes that shift circuit left, m position alternative data selector array, m position two input gate arrays, m bit position are long-pending produces circuit, full adder FA array, m+3 bit scan register, yojan circuit and with the displacement benefit value circuit that leaves out the beginning and the end of the johnson counter of a m/2 position; The square operation input item A that is input as m position of the displacement benefit of leaving out the beginning and the end value circuit, being output as the output Q of m bit register in the displacement benefit value circuit that leaves out the beginning and the end, the output Qc of register in the johnson ring shift counter of m/2 position that leaves out the beginning and the end in displacement benefit value circuit of output simultaneously; The low m/2 position that is input as square input item A of shift circuit left; Shift circuit left, when each rising edge clock arrives, in shift circuit, the value of register moves to left one left, and low level zero padding, the output terminal of most significant digit register is drawn simultaneously, is defined as AL.The long-pending input end that produces circuit of m bit position is connected with the output terminal of m position two input gate arrays, port in the input end of m position two input and door and corresponding being connected of m position of m position alternative data selector array, another input end connects as follows: first lowest order that is connected the output Q of the displacement benefit value circuit that leaves out the beginning and the end with door, second is connected the second of Q with door, by that analogy, m-1 position is connected time high-order radix-minus-one complement of Q with door, m position is connected the inferior high-order of Q with door; M position gate array is output as the long-pending output of final m bit position.The long-pending output terminal that produces circuit of m bit position is connected with the input end of full adder FA array, and full adder FA array is connected with brief circuit by m+3 bit scan register, and the output terminal of m+3 bit scan register is sent into yojan circuit and carried out yojan; Wherein, 160≤m≤15360.
M position alternative data selector array comprises m position alternative data selector, and wherein the control signal of the alternative data selector of m position is produced by the Johnson ring shift counter output Qc leaving out the beginning and the end in displacement benefit value circuit; Wherein, the second numerical value that the control signal of first alternative data selector and second alternative data selector is Qc, the 3rd bit value that the control signal of the 3rd alternative data selector and the 4th alternative data selector is Qc, by that analogy, the m/2 bit value that the signal processed of m-3 position alternative data selector and m-2 position alternative data selector is Qc, the signal processed of m-1 position alternative data selector and m position alternative data selector is set to 1; " 0 " termination of m position alternative data selector is the output AL of shift circuit left, the leave out the beginning and the end most significant digit of output Q of displacement benefit value circuit of " 1 " termination.
The long-pending circuit that produces of m bit position, after partial product produces, send in m full adder FA as input, wherein, the carry input of the full adder of lowest order connects the output of an alternative data selector, " 0 " end of alternative data selector connects the lowest order Q[0 of the m position output Q of the displacement benefit value circuit that leaves out the beginning and the end], " 1 " end input zero, the control signal of alternative data selector is the second Qc[1 of the output Qc of Johnson ring shift counter in displacement benefit value circuit of leaving out the beginning and the end]; The carry input of all the other full adders is the carry output from low level.
M position full adder FA exports with position input end " 0 " end of sending into scan register; " 1 " end of lowest order scan register connects the output terminal of an alternative data selector, the input of alternative data selector " 0 " end connects the lowest order A[0 of square operation input item A], " 1 " end input zero, the control signal of alternative data selector is Sel, and lowest order and the most significant digit phase XOR of this signal output terminal Qc of Johnson counter in the displacement benefit value circuit that leaves out the beginning and the end produce; " 1 " end input zero of second scan register, " 1 " end input one-bit full addres of the 3rd bit scan register be FA's and position, " 1 " end input second full adder of the 4th bit scan register be FA's and position, by that analogy, " 1 " end input m position full adder of m+2 bit scan register be FA's and position, the carry output of " 1 " end input m position full adder FA of m+3 bit scan register.
The circuit implementation structure that the present invention is applicable to the fast square algorithm of large digital-to-analogue square operation comprises: the displacement benefit value of leaving out the beginning and the end circuit, shift circuit, a series of alternative circuit, two input gate array, full adder FA array and a series of scan register and yojan circuit left.Wherein, the johnson counter that leaves out the beginning and the end and comprise a m/2 position in displacement benefit value circuit.The leave out the beginning and the end square input item A that is input as m position of displacement benefit value circuit, being output as the output Q of m bit register in the displacement benefit value circuit that leaves out the beginning and the end, and exports the output Qc of register in the johnson ring shift counter of m/2 position simultaneously.The low m/2 position that is input as square input item A of shift circuit left, when each rising edge clock arrives, in shift circuit, the value of register moves to left one left, and low level zero padding, the output terminal of most significant digit register is drawn simultaneously, is defined as AL.The control signal of m position alternative array is mainly produced by the Johnson ring shift counter output Qc leaving out the beginning and the end in displacement benefit value circuit.The second numerical value that the control signal of first and second alternative is Qc, the 3rd bit value that the control signal of the 3rd and the 4th alternative is Qc, by that analogy ... the m/2 bit value that the alternative control signal of m-3 position and m-2 position is Qc, the alternative control signal of m-1 position and m position is set to 1." 0 " termination of m position alternative array is the output AL of shift circuit left, the leave out the beginning and the end most significant digit of output Q of displacement benefit value circuit of " 1 " termination.Two inputs and m position corresponding be connected of one of them port of door input end with m position alternative array of m position, another input end connects as follows: first lowest order that is connected the output Q of the displacement benefit value circuit that leaves out the beginning and the end with door, second is connected the second of Q with door, by that analogy ... m-1 position is connected time high-order radix-minus-one complement of Q with door, m position is connected the inferior high-order of Q with door.M position gate array is output as the long-pending output of final m bit position.
After partial product produces, send in m full adder FA as input, wherein, the carry input of the full adder of lowest order connects the output of an alternative, " 0 " end of alternative connects the lowest order Q[0 of the m position output Q of the displacement benefit value circuit that leaves out the beginning and the end], " 1 " end input zero, the control signal of alternative is the second Qc[1 of the output Qc of Johnson ring shift counter in displacement benefit value circuit of leaving out the beginning and the end]; The carry input of all the other full adders is the carry output from low level.M position full adder send into input end " 0 " end of scan register with position output." 1 " end of lowest order scan register connects the output terminal of an alternative, the input of alternative " 0 " end connects the lowest order A[0 of the input item A of square operation], " 1 " end input zero, the control signal of alternative is Sel, and lowest order and the most significant digit phase XOR of this signal output terminal Qc of Johnson counter in the displacement benefit value circuit that leaves out the beginning and the end produce." 1 " end input zero of second scan register, " 1 " end input one-bit full addres of the 3rd bit scan register be FA's and position, " 1 " end input second full adder of the 4th bit scan register be FA's and position, by that analogy, " 1 " end input m position full adder of m+2 bit scan register be FA's and position, the carry output of " 1 " end input m position full adder FA of m+3 bit scan register.The output terminal of m+3 bit scan register is sent into yojan circuit and is carried out yojan.
In the present invention, it is m/2 by m Partial product compression that partial product produces circuit, final square operation adopts from a high position to low bit arithmetic, first partial product produces and backwardly moves to left two, is added after sending into the yojan of yojan circuit with the second part is long-pending, completes one-accumulate, by that analogy, until m/2 partial product produces, complete m/2 time and add up, finally complete computing module-square.
Table 1
With reference to table 1, table 1 is the partial product summation form of the square operation after launching according to polynomial multiplication, and whole process need is sued for peace to m partial product, a whole process need m-1 clock period.
Table 2
With reference to table 2, table 2, for the partial product summation form of the present invention after optimizing, is half in table 1 by Partial product compression, and whole process only needs m/2-1 clock can complete square operation.
Table 3
| ? | ? | ? | ? | ? | ? | A5A4 | A5(!A4) | A7A1 | A6A1 | A5A1 | A4A1 | A3A1 | A2A1+A2 | 0 | A1 |
| ? | ? | ? | ? | A6A5 | A6(!A5) | A6A4 | A6A3 | A6A2 | A5A2 | A4A2 | A3A2+A3 | ? | ? | ? | ? |
| ? | ? | A7A6 | A7(!A6) | A7A5 | A7A4 | A7A3 | A7A2 | A5A3 | A4A3+A4 | ? | ? | ? | ? | ? | ? |
| A8A7 | A8(!A7) | A8A6 | A8A5 | A8A4 | A8A3 | A8A2 | A8A1 | ? | ? | ? | ? | ? | ? | ? | ? |
With reference to table 3, table 3 adopts the long-pending summation of the squared part form of this algorithm for take 8 bits as example, take 8 bits as example, adopts algorithm of the present invention, by Partial product compression, is 4.
Calculating process of the present invention:
Referring to Fig. 1 and Fig. 2, RS=0 during initialization, is all set to 0 by register; During work, RS=1, behind first efficient clock edge, the displacement benefit of leaving out the beginning and the end value circuit output Q=[A
m, A
m-1, A
m-2a
2, A
1], Qc=[11 ... 111]; After second efficient clock edge, partial has added for the first time, the displacement benefit of leaving out the beginning and the end value circuit output Q=[A
m-1, A
m-2a
2, A
m/2+1, A
m/2], Qc=[11 ... 110]; Until m/2 clock along after, complete m/2-1 partial product and add up, exports data simultaneously and move to left and deposit register in, so minimum two of register is 00; M/2+1 clock is when arriving, and all partials have added simultaneously and in two bit registers in the end, deposit 0 and the lowest order of the input item A of square operation in; In the cumulative process of partial product, each rising edge clock is sent the output valve value of m+3 scan register into yojan circuit after arriving, after yojan completes, the next clock of wait is along arrival, cumulative with next partial product, by that analogy ... until after m/2+1 clock edge, register stops displacement, through two clock edges, finally completes computing module-square process at most again.
Claims (7)
1. a Fast Modular square operation circuit that is applicable to large number, is characterized in that: comprising that shift circuit left, m position alternative data selector array, m position two input gate arrays, m bit position are long-pending produces circuit, full adder FA array, m+3 bit scan register, yojan circuit and with the displacement benefit value circuit that leaves out the beginning and the end of the johnson counter of a m/2 position; The square operation input item A that is input as m position of the displacement benefit of leaving out the beginning and the end value circuit, being output as the output Q of m bit register in the displacement benefit value circuit that leaves out the beginning and the end, the output Qc of register in the johnson ring shift counter of m/2 position that leaves out the beginning and the end in displacement benefit value circuit of output simultaneously; The low m/2 position that is input as square input item A of shift circuit left; The long-pending input end that produces circuit of m bit position is connected with the output terminal of m position two input gate arrays, and the long-pending output terminal that produces circuit of m bit position is connected with the input end of full adder FA array, and full adder FA array is connected with brief circuit by m+3 bit scan register; Wherein, 160≤m≤15360.
2. the Fast Modular square operation circuit that is applicable to large number according to claim 1, it is characterized in that: described shift circuit left, when each rising edge clock arrives, in shift circuit, the value of register moves to left one left, and low level zero padding, the output terminal of most significant digit register is drawn simultaneously, be defined as AL.
3. the Fast Modular square operation circuit that is applicable to large number according to claim 1, it is characterized in that: described m position alternative data selector array comprises m position alternative data selector, wherein the control signal of the alternative data selector of m position is produced by the Johnson ring shift counter output Qc leaving out the beginning and the end in displacement benefit value circuit; Wherein, the second numerical value that the control signal of first alternative data selector and second alternative data selector is Qc, the 3rd bit value that the control signal of the 3rd alternative data selector and the 4th alternative data selector is Qc, by that analogy, the m/2 bit value that the signal processed of m-3 position alternative data selector and m-2 position alternative data selector is Qc, the signal processed of m-1 position alternative data selector and m position alternative data selector is set to 1; " 0 " termination of m position alternative data selector is the output AL of shift circuit left, the leave out the beginning and the end most significant digit of output Q of displacement benefit value circuit of " 1 " termination.
4. the Fast Modular square operation circuit that is applicable to large number according to claim 1, it is characterized in that: port in the input end of two inputs of described m position and door and corresponding being connected of m position of m position alternative data selector array, another input end connects as follows:
First lowest order that is connected the output Q of the displacement benefit value circuit that leaves out the beginning and the end with door, second is connected the second of Q with door, and by that analogy, m-1 position is connected the radix-minus-one complement of an inferior high position of Q with door, m position and an inferior high position that is connected Q; M position gate array is output as the long-pending output of final m bit position.
5. according to the Fast Modular square operation circuit that is applicable to large number described in claim 1 or 4, it is characterized in that: the long-pending circuit that produces of described m bit position, after partial product produces, send in m full adder FA as input, wherein, the carry input of the full adder of lowest order connects the output of an alternative data selector, " 0 " end of alternative data selector connects the lowest order Q[0 of the m position output Q of the displacement benefit value circuit that leaves out the beginning and the end], " 1 " end input zero, the control signal of alternative data selector is the second Qc[1 of the output Qc of Johnson ring shift counter in displacement benefit value circuit of leaving out the beginning and the end], the carry input of all the other full adders is the carry output from low level.
6. the Fast Modular square operation circuit that is applicable to large number according to claim 1, is characterized in that: described m position full adder FA exports with position input end " 0 " end of sending into scan register; " 1 " end of lowest order scan register connects the output terminal of an alternative data selector, the input of alternative data selector " 0 " end connects the lowest order A[0 of square operation input item A], " 1 " end input zero, the control signal of alternative data selector is Sel, and lowest order and the most significant digit phase XOR of this signal output terminal Qc of Johnson counter in the displacement benefit value circuit that leaves out the beginning and the end produce; " 1 " end input zero of second scan register, " 1 " end input one-bit full addres of the 3rd bit scan register be FA's and position, " 1 " end input second full adder of the 4th bit scan register be FA's and position, by that analogy, " 1 " end input m position full adder of m+2 bit scan register be FA's and position, the carry output of " 1 " end input m position full adder FA of m+3 bit scan register.
7. the Fast Modular square operation circuit that is applicable to large number according to claim 1, is characterized in that: the output terminal of described m+3 bit scan register is sent into yojan circuit and carried out yojan.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310653889.9A CN103699358B (en) | 2013-12-05 | 2013-12-05 | A kind of Fast Modular square operation circuit being applicable to big number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310653889.9A CN103699358B (en) | 2013-12-05 | 2013-12-05 | A kind of Fast Modular square operation circuit being applicable to big number |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103699358A true CN103699358A (en) | 2014-04-02 |
| CN103699358B CN103699358B (en) | 2016-11-23 |
Family
ID=50360899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310653889.9A Expired - Fee Related CN103699358B (en) | 2013-12-05 | 2013-12-05 | A kind of Fast Modular square operation circuit being applicable to big number |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103699358B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2796555C1 (en) * | 2022-11-30 | 2023-05-25 | федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" | Computing device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030206628A1 (en) * | 2002-05-01 | 2003-11-06 | Sun Microsystems, Inc. | Generic modular multiplier using partial reduction |
| CN1490714A (en) * | 2002-10-02 | 2004-04-21 | 国际商业机器公司 | Circuit method for high-efficiency module reduction and multiplication |
| DE10357661A1 (en) * | 2002-12-30 | 2004-07-15 | Samsung Electronics Co., Ltd., Suwon | Montgomery modular multiplier for public-key cryptographic system, has compressor performing additions required for each bit before additions in carry propagation adder to remove propagation delay time to improve performance |
| JP2009230153A (en) * | 1997-05-04 | 2009-10-08 | Sandisk Il Ltd | Improved apparatus and method for modular multiplication and exponentiation based on montgomery multiplication |
| CN101834712A (en) * | 2010-04-19 | 2010-09-15 | 浙江大学 | Method for realizing accurate time synchronization by utilizing IEEE1588 protocol |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200976579Y (en) * | 2006-07-28 | 2007-11-14 | 东南大学 | Reversed phase shift restricted competition metering code circuit |
-
2013
- 2013-12-05 CN CN201310653889.9A patent/CN103699358B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009230153A (en) * | 1997-05-04 | 2009-10-08 | Sandisk Il Ltd | Improved apparatus and method for modular multiplication and exponentiation based on montgomery multiplication |
| US20030206628A1 (en) * | 2002-05-01 | 2003-11-06 | Sun Microsystems, Inc. | Generic modular multiplier using partial reduction |
| CN1490714A (en) * | 2002-10-02 | 2004-04-21 | 国际商业机器公司 | Circuit method for high-efficiency module reduction and multiplication |
| DE10357661A1 (en) * | 2002-12-30 | 2004-07-15 | Samsung Electronics Co., Ltd., Suwon | Montgomery modular multiplier for public-key cryptographic system, has compressor performing additions required for each bit before additions in carry propagation adder to remove propagation delay time to improve performance |
| CN101834712A (en) * | 2010-04-19 | 2010-09-15 | 浙江大学 | Method for realizing accurate time synchronization by utilizing IEEE1588 protocol |
Non-Patent Citations (2)
| Title |
|---|
| 戴紫彬: "GF(2m)域上可配置ECC算术模块的设计与实现", 《计算机工程》 * |
| 童元满: "高性能公钥密码协处理器的设计与实现", 《中国优秀博硕士学位论文全文数据库（硕士） 信息科技辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2796555C1 (en) * | 2022-11-30 | 2023-05-25 | федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" | Computing device |
| RU2797163C1 (en) * | 2023-02-13 | 2023-05-31 | федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" | Pipeline calculator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103699358B (en) | 2016-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7268996B2 (en) | Systems and methods for computation | |
| CN102681815B (en) | By the method having symbol multiply accumulating algorithm of totalizer tree structure | |
| CN100465877C (en) | High speed split multiply accumulator apparatus | |
| CN110765709A (en) | FPGA-based 2-2 fast Fourier transform hardware design method | |
| CN101847137B (en) | FFT processor for realizing 2FFT-based calculation | |
| CN110362293B (en) | Multiplier, data processing method, chip and electronic equipment | |
| EP4318275A1 (en) | Matrix multiplier and method for controlling matrix multiplier | |
| Chen et al. | A matrix-multiply unit for posits in reconfigurable logic leveraging (open) CAPI | |
| Sen et al. | Low power mac unit for DSP processor | |
| CN100409259C (en) | Scaleable large-scale 2D convolution circuit | |
| CN101840324B (en) | 64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism | |
| Sano et al. | Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster | |
| CN101866278B (en) | Asynchronous iteration 64-bit integer multiplier and computing method thereof | |
| CN103699358A (en) | Rapid modular square arithmetic circuit applicable to great number | |
| CN104503730A (en) | Instruction-based large-number point addition and point multiplication operation circuit and realization method | |
| CN103699729B (en) | Modulus multiplier | |
| CN113033799B (en) | Data processor, method, device and chip | |
| CN102929575B (en) | Modular multiplier | |
| CN210109863U (en) | Multiplier, device, neural network chip and electronic equipment | |
| WO2020108486A1 (en) | Data processing apparatus and method, chip, and electronic device | |
| Kaur et al. | Area-efficient low PDP 8-bit vedic multiplier design using compressors | |
| CN106873941B (en) | A kind of Fast Modular Multiplication and mould squaring circuit and its implementation | |
| Kamp et al. | Multiply accumulate unit optimised for fast dot-product evaluation | |
| CN103605494A (en) | Square operation circuit | |
| CN113031911A (en) | Multiplier, data processing method, device and chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161123 Termination date: 20201205 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |