CN103681542B - 芯片封装和用于制作芯片封装的方法 - Google Patents

芯片封装和用于制作芯片封装的方法 Download PDF

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CN103681542B
CN103681542B CN201310396680.9A CN201310396680A CN103681542B CN 103681542 B CN103681542 B CN 103681542B CN 201310396680 A CN201310396680 A CN 201310396680A CN 103681542 B CN103681542 B CN 103681542B
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chip
intermediate layer
sidewall
carrier
layer
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CN103681542A (zh
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F.布鲁奇
E.格里布尔
R.奥特伦巴
B.勒默尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

芯片封装和用于制作芯片封装的方法。提供一种芯片封装，所述芯片封装包括：包括至少一个腔体的载体；至少部分地设置在至少一个腔体内的芯片；设置在芯片的至少一个侧壁上的至少一个中间层；其中至少一个中间层被配置为将来自芯片的热量热传导到载体。

Description

芯片封装和用于制作芯片封装的方法
技术领域
各实施例总体上涉及芯片封装和用于制作芯片封装的方法。
背景技术
今天，芯片主要通过芯片背面被冷却。例如，如在图5中所示，芯片501可以通过形成在芯片背面上的芯片焊料505被连接到芯片载体503（例如引线框）。芯片可以被有机材料507（例如，将芯片和连接到芯片的电布线509电绝缘的注模填料或者层压体）包围。在没有足够热传播和/或热传导的情况下，具有大约1W/mK的差的热导率的这些传统的有机材料507可能会提供不充足的功率容量（power handling）。
发明内容
不同实施例提供一种芯片封装，其包括：包括至少一个腔体的载体；至少部分地被设置在所述至少一个腔体内的芯片；设置在芯片的至少一个侧壁上的至少一个中间层；其中所述至少一个中间层被配置为将来自芯片的热量热传导到载体。
附图说明
在附图中，贯穿不同的视图，相似的参考标记一般指的是相同的部分。附图不必要按比例，而是通常将重点放在说明本发明的原理上。在下面的描述中，参照下面的附图来描述本发明的各实施例，其中：
图1示出根据实施例的芯片封装；
图2示出根据实施例的用于制作芯片封装的方法；
图3A到3F示出根据不同实施例的用于制作芯片封装的方法；
图4示出根据实施例的芯片封装；
图5示出芯片封装。
具体实施方式
下面的详细描述参照附图，所述附图借助图示示出其中本发明可以被实施的实施例和具体细节。
词“示例性的”在此被用来表示“充当实例，例子，或者例证”的意思。此处被描述为“示例性的”的任何实施例或者设计不必要解释为比其它实施例或者设计优选或者有利。
在此被用来描述在侧面或者表面“上面”形成特征（例如层）的词“上面”，可以被用来表示该特征（例如该层）可以“直接”形成在所暗示的侧面或者表面“上面”，例如与所暗示的侧面或者表面直接接触。在此被用来描述在侧面或者表面“上面”形成特征（例如层）的词“上面”，可以被用来表示该特征（例如该层）可以“间接”形成在所暗示的侧面或者表面“上面”，其中一个或者多个附加层被设置在所暗示的侧面或表面和被形成的层之间。
有机材料（例如，在芯片封装中围绕芯片的注模填料和/或层压体）具有比焊料材料和芯片载体（例如铜引线框）差得多的大约为1W/mK的热导率，所述焊料材料可以具有大约40W/mK的热导率，所述芯片载体可以具有大约300W/mK的热导率。热导率可以被理解为指的是厚度除以热阻和面积的乘积，即热导率=厚度/（热阻×面积）。
不同实施例提供用于目前和将来紧凑芯片技术的芯片封装，其中可以预期较小芯片表面面积。这些可以包括功率半导体芯片的芯片可能经受大量的性能限制（例如电流和温度限制）。因此，尤其对于较小芯片技术和具有较小芯片面积的那些技术，出现了相当大的性能限制。特别地，因为在应用中或者在操作期间芯片的最大温度可以被预期为将来在大约150到175o保持恒定，它们的最大电流（例如由I²最大电流=Δ温度(K)/(Rth (K/W)×Ron(Ω)给出）可被限制。
不同实施例提供三维（3D）热传播，其中芯片可以通过芯片背面和芯片侧壁被冷却。
不同实施例提供用于热传导和/或热耗散的可用面积的增加，并且可以被用于小的芯片，例如，大约1mm2面积芯片和/或具有从大约100μm变动到大约700μm的厚度的芯片。
不同实施例提供3D热传播，其可改善功率封装的芯片冷却，因为冷却的程度目前可能是功率电子部件的限制因素。
不同实施例提供芯片封装，其中薄芯片侧壁可被定目标为用于在功率芯片封装中利用芯片载体腔体和热传导芯片嵌入材料（例如金属）进行冷却。
图2示出根据实施例的用于制作芯片封装的方法200。
方法200可以包括：
设置芯片，所述芯片至少部分地被设置在形成在芯片载体中的至少一个腔体内（在210中）；
在芯片的至少一个侧壁上面设置至少一个中间层；所述至少一个中间层从而将来自芯片的热量热传导到载体（在220中）。
图3A到3F示出根据实施例的用于制作芯片封装的方法300。
如在图3A（310）中示出的，方法300可以包括在载体102中形成至少一个腔体104。
载体102可以包括引线框，例如铜引线框。载体102可以包括来自下面材料组中的至少一种材料，所述材料组由下述构成：铜，镍，铁，银，金，钯，磷，铜合金，镍合金，铁合金，银合金，金合金，钯合金，磷合金。载体102可以包括导电材料。
腔体104可以例如通过蚀刻和/或例如通过激光构造和/或例如通过机械构造形成。腔体104可以被形成为使得腔体104具有深度d。腔体深度d可以从大约100μm到大约800μm变动，但是可以理解腔体深度d可以不被限制到这个深度范围，并且可以根据保持一个芯片和/或多个芯片所需的深度来变化。例如，腔体深度d可以大于芯片106的厚度Ct。
腔体104可以包括腔体侧壁316和腔体底壁318，其可被连接和/或结合到腔体侧壁316。腔体侧壁316和腔体底壁318限定腔体104。腔体104可以被理解为包括从载体顶面形成的凹进。腔体深度d可以被理解成是在载体顶面和腔体底壁318之间测量的距离。腔体侧壁316可以将腔体底壁318结合到载体顶面。
如在图3B中（在320中）示出的，芯片106可以至少部分地被设置在形成在芯片载体102中的至少一个腔体104内。
芯片106可以包括半导体管芯，其可以可选地包括至少一个接触焊盘，例如，芯片背面金属化层108。芯片背面金属化层108可以被形成在芯片背面322上面和/或直接被形成在芯片背面322上。芯片106可以还包括至少一个接触焊盘，例如，形成在芯片正面上面和/或直接形成在芯片正面上的至少一个芯片正面接触焊盘326。芯片背面金属化层108和/或至少一个芯片正面接触焊盘326可以包括来自下面材料组中的至少一种材料，元素或者合金，所述组由下述构成：铜，铝，银，锡，钛，金，钯，锌，镍，铁。
可以理解正面也可以被称作芯片的“第一面”，“顶面”或者“上面”。术语“顶面”，“第一面”，“正面”或者“上面”可以在下文中被互换使用。背面也可以被称作芯片的“第二面”或者“底面”。术语“第二面”，“背面”或者“底面”可以在下文中被互换使用。
芯片106可以包括半导体功率器件。如此处关于一些半导体功率器件使用的，术语“顶面”，“第一面”，“正面”或者“上面”可以被理解为指的是芯片的其中可以形成一个或者多个芯片金属化接触焊盘（例如可以形成栅极区域，例如第一源极/漏极区域）的面。术语“第二面”，“背面”或者“底面”可以被理解为指的是芯片的其中可以形成第二源极/漏极区域的面。可以理解，半导体器件（例如半导体功率晶体管）可以支持通过在芯片正面接触焊盘（例如326）和芯片背面接触焊盘（例如芯片背面金属化108）之间的芯片的垂直电流流动。例如，芯片正面接触焊盘326可以被提供有从大约150V变化到大约900V的电压，并且芯片背面金属化108可被连接到基极电势电压，例如地，例如0V。
芯片106可以包括包含碳化硅（SiC）的半导体功率器件。芯片106可以包括包含氮化镓（GaN）的半导体功率器件。芯片106可以包括至少一个半导体功率器件（例如包括SiC，GaN），其中芯片或者管芯可以比用于硅器件的通常的管芯更小，例如小得直到二十分之一。例如，芯片106可以具有从大约0.5mm2到10mm2变化的长度（Cl）×宽度（Cb，未示出）表面面积。芯片106可以包括从大约100μm变化到大约800μm的厚度（Ct），例如大约200μm变化到大约600μm，例如大约300μm变化到大约500μm。芯片106可以包括消散比传统硅芯片大得多的功率的半导体功率器件。例如，芯片106可以包括消散从大约10W变化到30W的功率的半导体功率器件。只从芯片背面322冷却可能不足以散热来将芯片保持在合适的温度范围（例如小于150℃）。
芯片106可以被设置在至少一个腔体104中。芯片106可以通过芯片背面金属化层108被电连接到载体102（例如腔体底壁318）。然而根据其它实施例，芯片106可以不被电连接到载体。至少一个中间层112可以被设置在芯片106的至少一个侧壁114上面。至少一个中间层112可以仅部分地覆盖至少一个侧壁114或者可以基本上完全覆盖至少一个侧壁114。至少一个中间层112可以被电连接到芯片背面金属化层108。至少一个中间层112可以因此将来自芯片106的热量热传导到载体102。可以可能的是，至少一个侧壁的表面面积（Ct×Cb×n）可基本上等于或者大于芯片背面的表面面积（Cl×Cb），其中n是侧壁的数目，其通常可以是4。可以可能的是，至少一个侧壁的表面面积（Ct×Cb×n）可以具有从芯片背面表面面积（Cl×Cb）的大约40%变化到芯片背面表面面积（Cl×Cb）的250%的表面面积。（例如，具有芯片背面表面面积（Cl×Cb=1×1mm2）的芯片可以具有大约200μm的芯片厚度。具有n个侧壁的芯片侧壁面积可以是Ct×Cb=1×0.2×n mm2，如果n=4，其可以是大约0.8mm2。因此，在这个实例中，芯片侧壁面积可以是芯片背面表面面积的大约80%。因此，从侧壁的热消散可以明显地有助于芯片106的冷却。
至少一个中间层112可以包括大于10W/mK的热导率。至少一个中间层112可以包括金属。金属通常可以具有大于300W/mK（例如大约为400W/mK）的热导率。至少一个中间层112可以包括来自下面材料组中的至少一种材料，元素或者合金，所述组由下述构成：铜，铝，银，锡，钛，金，钯，锌，镍，铁。
至少一个中间层112可以包括管芯附着材料328。管芯附着材料328可以包括焊料材料。焊料材料可以包括包含来自下面材料组中的至少一种材料的焊料合金，所述材料组由下述构成：锡，铟，金，银，铜，镍，铅和锑，以及其一种或者多种合金。例如，焊料材料可以包括基于Sn和/或In的焊料，其一个或者两者都可以与下述中的至少一个形成合金：金，银，铜，镍，铅或者锑。焊料材料通常可以具有大于50W/mK的热导率。
至少一个中间层112可以被电短路到芯片背面金属化层108。可以理解的是，然而传统芯片背面金属化层108可以被专门地形成在芯片背面322上。背面接触（例如芯片背面金属化层108）也可以覆盖至少一个侧壁114。换句话说，至少一个中间层112可以被配置为背面接触，如芯片背面金属化层108，其可以被形成在至少一个侧壁114和芯片背面322上面和/或被直接形成在至少一个侧壁114和芯片背面322上。因此，至少一个中间层112和芯片背面金属化层108可以被提供有相同的基极电势电压，例如地电压，例如0V。芯片背面金属化层108可以被电连接到载体102。至少一个中间层112也可以将至少一个侧壁114电连接到载体102，例如到至少一个腔体侧壁316和到至少一个腔体底壁318。芯片背面322（例如芯片背面金属化层108）和至少一个侧壁114可通过管芯附着材料328被连接到载体102。因此，载体102，芯片背面金属化层108和至少一个中间层112可被提供有相同的基极电势电压，例如地电压，例如0V。
可以配置至少一个中间层112以将来自至少一个侧壁114的热量热传导到至少一个腔体侧壁316。至少一个中间层112可以增加与载体102热接触的芯片106的总表面面积。
图3C到3E示出根据不同实施例的用于形成至少一个中间层112的工艺。
根据如在图3C（330）中示出的实施例，至少一个中间层112可被沉积在至少一个侧壁114上面和芯片背面金属化层108上面。至少一个中间层112可以包括管芯附着材料328，例如焊料材料，例如焊料合金。在这种情况下，至少一个中间层112可以通过来自如下的沉积工艺组的至少一个沉积工艺沉积，所述沉积工艺组由下述构成：蒸发，溅射，水电镀（galvanic plating）。可以理解至少一个中间层112可以用作用于芯片背面322和至少一个芯片侧壁114的管芯附着材料。可以进一步理解，因为至少一个中间层112可以被形成在至少一个侧壁和芯片背面322两者的上面，至少一个侧壁和芯片背面322可以被电短路，例如可以被配置以给芯片供应相同的电势电压。在芯片106可至少部分地设置在腔体104内之后，至少一个侧壁114和芯片背面金属化层108可以通过采用焊料材料（例如管芯附着材料328）形式的至少一个中间层112被焊接到载体102。焊接工艺可以包括例如扩散焊接工艺。在前端工艺（例如前道工序（FEOL）工艺）中，至少一个中间层112可以被形成在芯片102的至少一个侧壁114上面和/或在芯片背面322上面，例如在芯片背面金属化层108上面。
根据如在图3D（340）中示出的另一实施例，形成至少一个中间层112可以包括在芯片背面322和至少一个侧壁114上面形成第一金属层112M，并且在第一金属层112M上面形成管芯附着层328。
第一金属层112M可以形成芯片背面金属化层108的至少一部分。换句话说，第一金属层112M和芯片背面金属化层108可以形成在芯片背面322和至少一个侧壁114上面形成的单一连续电极。管芯附着层328也可以将芯片背面322和至少一个侧壁114电连接到载体102，并且可以进一步用作用于将芯片背面322和至少一个侧壁114结合到载体102的结合材料（例如焊料材料）。第一金属层112M和管芯附着层328两者都可以在前端工艺期间沉积形成。至少一个侧壁114和芯片背面金属化层108可以通过采用焊料材料（例如管芯附着材料328）形式的至少一个中间层112被焊接到载体102。
根据如在图3E（350）中示出的另一实施例，取代在芯片背面322和至少一个侧壁114上面沉积管芯附着材料328（例如在前端加工期间），在腔体104中沉积焊料材料332可以是可能的。焊料材料332可以与管芯附着材料328类似，并且可以使用例如溅射或蒸发或水电镀的沉积方法被沉积在腔体104中（例如在腔体底壁318上面）。焊料材料332可以被形成在腔体底壁318上面。芯片106可以被配置在腔体底壁318上面（例如在焊料材料332上面），其中芯片背面322和/或芯片背面金属化层108在焊料材料332上，例如电接触焊料材料332。加热工艺（例如焊接工艺）可以使得焊料材料332从芯片背面322和腔体底壁318之间挤出到至少一个侧壁114上。因此，焊料材料332的挤出可以形成被配置在芯片106的至少一个侧壁114上面并且被电连接到芯片背面金属化层108的至少一个中间层112。
根据在如图3F（360）中示出的另一实施例，至少一个中间层112可以例如通过使用种子层的水电镀被沉积在腔体底壁318和至少一个腔体侧壁316上面。至少一个中间层112可以包括如前面描述的管芯附着材料328（例如焊料材料）。芯片106可以被设置在腔体104内，并且通过至少一个中间层112被结合（例如焊接）到腔体104。至少一个芯片侧壁114可以通过至少一个腔体侧壁316和至少一个中间层112被热连接到载体102。至少一个芯片背面金属化层108可以通过至少至少一个中间层112和腔体底壁318被热连接到载体102。
根据另一实施例，至少一个中间层112可以包括形成在至少一个芯片侧壁114和腔体侧壁316之间的间隙中的中间通路和/或柱（未示出）。中间通路和/或柱可以包括与关于至少一个中间层112描述的那些材料相似的材料，并且可以将至少一个侧壁114热连接和/或电连接到腔体侧壁316，例如具有大于10W/mK的热导率。根据其它实施例，中间通路和/或柱可以包括沉积在至少一个芯片侧壁114和腔体侧壁316之间的间隙中的填充材料，例如纳米管，例如纳米线，例如纳米粒子。例如，使用间隙填充方法和/或例如使用生长方法，例如化学汽相沉积。至少一个中间层112可以包括具有大于10W/mK的热导率的填充材料。
在通过图3C，3D，3E或3F中示出的工艺中的至少一种在至少一个侧壁114上面沉积至少一个中间层112之后，并且在通过腔体底壁318，腔体侧壁316和至少一个中间层112将芯片106结合和/或粘附到载体102之后，方法300可以进一步包括布线和电绝缘工艺。这些布线和电绝缘工艺可以在芯片顶面上实施。至少一种电互连336可以被电连接到至少一个芯片顶面接触焊盘326。至少一个电互连336可以包括来自下面材料组中的至少一种材料，元素或者合金，所述组由下述构成：铜，铝，银，锡，钛，金，钯，锌，镍，铁。
根据如在图3F中示出的一些实施例，至少一个电互连336可以包括导电线，例如，其可以是接合到至少一个芯片顶面接触焊盘326的线。随后，电绝缘材料338（例如注模填料和/或例如层压体）可以被形成在芯片顶面上面并且包围和/或电绝缘至少一个电互连336。至少一个电互连336可以被电连接到导电引线框的至少一部分。尽管在图3F中示出使用线接合的电布线，可以理解电布线和电绝缘可以被应用到如根据图3B到3F和图4示出的实施例中的任何实施例。
根据如在图3E中示出的另一实施例，至少一个电互连336可以包括沉积在至少一个芯片顶面接触焊盘326上面的导电材料。例如，电绝缘材料338可以被沉积在芯片顶面上面。可以在至少一个芯片顶面接触焊盘326上面的电绝缘材料338中形成至少一个孔，从而暴露所述至少一个芯片顶面接触焊盘326。可以在该至少一个孔中形成至少一个电互连336，其中至少一个电互连336可以被电连接到至少一个芯片顶面接触焊盘326。至少一个电互连336可以通过水电镀和/或溅射和/或蒸发形成。至少一个电互连336可以进一步包括用于将至少一个芯片顶面接触焊盘326电连接到结合结构337（例如，焊料结构，例如焊料球）的至少一个再分配层。尽管在图3E中示出使用沉积互连的电布线，但是可以理解电布线和电绝缘可以被应用到如根据图3B到3F和图4示出的实施例中的任何实施例。
图4示出根据实施例的芯片封装410。芯片封装410可以包括已经关于图3A到3F描述的特征中的一个或多个或所有特征。除了载体102可以包括直接铜接合衬底402。直接铜接合衬底402可以包括陶瓷材料（例如Al2O3），其可以具有良好的热特性。直接铜接合衬底402可以包括陶瓷衬底以及接合和/或熔合到陶瓷衬底402的第一面444的铜层442。此外，另外的铜层可以被接合和/或熔合到陶瓷衬底的第二面446。陶瓷衬底402可以包括形成在陶瓷衬底402中的至少一个腔体404（与104相似）。另外的铜层可以被形成在腔体404中，例如给腔体底壁（与318相似）和至少一个腔体侧壁（与316相似）加衬里。至少一个中间层112可以包括另外的铜层。换句话说，另外的铜层可以与至少一个中间层112相似。至少一个中间层112可以被接合和/或熔合到陶瓷材料（例如陶瓷衬底402）。如根据前面实施例描述的，芯片106可以至少部分地设置在腔体404内，并且通过芯片背面金属化层108被电连接到载体102。芯片背面322和至少一个侧壁114可以通过另外的铜层被连接到载体102。另外的铜层可以被设置在芯片106的至少一个侧壁114上面，并且电连接到芯片背面金属化层108；其中另外的铜层可以被配置以将来自芯片106的热量热传导到载体102。如果需要，焊料材料（例如管芯附着材料328）可以被沉积在另外的铜层上面，其中管芯附着材料328可以将芯片背面金属化层108和至少一个侧壁114电连接并且热连接到载体102，并且其中管芯附着材料328可以进而例如通过焊接将芯片背面322和至少一个侧壁114粘附到载体102。直接铜接合衬底402可以被形成在另外的载体448上面，其可以包括另外的引线框。直接铜接合衬底402可以通过铜层442被电连接和/或热连接到另外的载体338。
不同实施例提供一种芯片封装，其包括：包括至少一个腔体的载体；至少部分地被设置在至少一个腔体内并且通过芯片背面金属化层电连接到载体的芯片；设置在芯片的至少一个侧壁上面的至少一个中间层；其中至少一个中间层被配置为将来自芯片的热量热传导到载体。
根据实施例，至少一个中间层被电连接到芯片背面金属化层。
根据实施例，载体包括引线框。
根据实施例，载体包括来自下面材料组中的至少一种材料，所述材料组由下述构成：铜，镍，铁，银，金，钯，磷，铜合金，镍合金，铁合金，银合金，金合金，钯合金，磷合金。
根据实施例，至少一个侧壁的表面面积基本上等于或者大于芯片背面的表面面积。
根据实施例，芯片包括包含碳化硅和氮化镓中的至少一个的半导体功率器件。
根据实施例，芯片包括消散从大约10W变动到30W的功率的半导体功率器件。
根据实施例，芯片包括从大约100μm变动到大约800μm的厚度。
根据实施例，至少一个中间层包括金属。
根据实施例，至少一个中间层包括来自下面材料组中的至少一种材料，元素或者合金，所述组由下述构成：铜，铝，银，锡，钛，金，钯，锌，镍，铁。
根据实施例，至少一个中间层包括管芯附着材料，所述管芯附着材料包括焊料材料。
根据实施例，焊料材料包括包含来自下面材料组中的至少一种材料的焊料合金，所述材料组由下述构成：锡，铟，金，银，铜，镍，铅和锑，以及其一种或者多种合金。
根据实施例，至少一个侧壁通过焊料材料被焊接到载体。
根据实施例，管芯附着材料被进一步形成在芯片背面上面，其中芯片背面和至少一个侧壁通过管芯附着材料被焊接到载体。
根据实施例，至少一个中间层包括大于10W/mK的热导率。
根据实施例，至少一个中间层被电短路到芯片背面金属化层。
根据实施例，至少一个中间层包括形成在芯片背面和至少一个侧壁上面的第一金属层，其中第一层形成芯片背面金属化层的至少一部分；和形成在第一金属层上面的管芯附着层，其中管芯附着层将芯片背面和至少一个侧壁电连接到载体。
根据实施例，至少一个中间层被配置为将来自至少一个侧壁的热量热传导到至少一个腔体侧壁。
根据实施例，至少一个中间层将至少一个侧壁电连接到载体。
根据实施例，载体包括陶瓷材料；并且
其中至少一个中间层包括接合到陶瓷材料的铜层；其中芯片背面和至少一个侧壁通过铜层被连接到载体。
不同实施例提供一种用于制作芯片封装的方法，所述方法包括：设置芯片，其至少部分地被设置在形成在芯片载体中的至少一个腔体内，并且通过芯片背面金属化层将芯片电连接到载体；在所述芯片的至少一个侧壁上面设置至少一个中间层；所述至少一个中间层从而将来自芯片的热量热传导到载体。
根据实施例，在芯片的至少一个侧壁上面设置至少一个中间层包括在前端工艺中设置至少一个中间层。
根据实施例，在芯片的至少一个侧壁上面设置至少一个中间层包括在芯片背面和至少一个侧壁上设置管芯附着材料，其中芯片背面和至少一个侧壁通过管芯附着材料被连接到载体。
虽然已经参照具体实施例特别地示出和描述了本发明，本领域技术人员应该理解在不脱离如由所附权利要求所限定的本发明的精神和范围的情况下，可以在其中作出形式和细节方面的各种改变。本发明的范围因而由所附权利要求表明，并且因此在权利要求的等同物的含义和范围内的所有变化旨在被包括。

Claims (24)

1.一种芯片封装，包括：
包括至少一个腔体的载体；
至少部分地设置在所述至少一个腔体内的芯片；
设置在所述芯片的至少一个侧壁上面的至少一个中间层；
其中所述至少一个中间层被配置为将来自所述芯片的热量热传导到所述载体，
其中所述至少一个中间层包括
形成在所述芯片背面和所述至少一个侧壁上的第一金属层，其中所述第一金属层形成芯片背面金属化层的至少一部分，和
形成在所述第一金属层上的管芯附着层，其中所述管芯附着层将所述芯片背面和所述至少一个侧壁电连接到所述载体。
2.根据权利要求1的芯片封装，其中所述芯片通过所述芯片背面金属化层被电连接到所述载体。
3.根据权利要求2的芯片封装，其中所述至少一个中间层被电连接到所述芯片背面金属化层。
4.根据权利要求1的芯片封装，其中所述载体包括引线框。
5.根据权利要求1的芯片封装，其中所述载体包括来自下面材料组中的至少一种材料，所述材料组由下述构成：铜，镍，铁，银，金，钯，磷，铜合金，镍合金，铁合金，银合金，金合金，钯合金，磷合金。
6.根据权利要求1的芯片封装，其中所述至少一个侧壁的表面面积等于或者大于芯片背面的表面面积。
7.根据权利要求1的芯片封装，其中所述芯片包括半导体功率器件，该半导体功率器件包括碳化硅和氮化镓中的至少一个。
8.根据权利要求1的芯片封装，其中所述芯片包括半导体功率器件，该半导体功率器件消散从10W变化到30W的功率。
9.根据权利要求1的芯片封装，其中所述芯片包括从100μm变化到800μm的厚度。
10.根据权利要求1的芯片封装，其中所述至少一个中间层包括金属。
11.根据权利要求1的芯片封装，其中所述至少一个中间层包括来自下面的材料组中的至少一种材料，元素或者合金，所述组由下述构成：铜，铝，银，锡，钛，金，钯，锌，镍，铁。
12.根据权利要求1的芯片封装，其中所述至少一个中间层包括管芯附着材料，所述管芯附着材料包括焊料材料。
13.根据权利要求12的芯片封装，其中所述焊料材料包括包含来自下面材料组的至少一种材料的焊料合金，所述材料组由下述构成：锡，铟，金，银，铜，镍，铅和锑，以及其一种或者多种合金。
14.根据权利要求12的芯片封装，其中所述至少一个侧壁通过所述焊料材料被焊接到所述载体。
15.根据权利要求12的芯片封装，其中所述管芯附着材料被进一步形成在芯片背面上，其中所述芯片背面和所述至少一个侧壁通过所述管芯附着材料被焊接到所述载体。
16.根据权利要求1的芯片封装，其中所述至少一个中间层包括大于10W/mK的热导率。
17.根据权利要求1的芯片封装，其中所述至少一个中间层被电短路到所述芯片背面金属化层。
18.根据权利要求1的芯片封装，其中所述至少一个中间层被配置为将来自所述至少一个侧壁的热量热传导到至少一个腔体侧壁。
19.根据权利要求1的芯片封装，其中所述至少一个中间层将所述至少一个侧壁电连接到所述载体。
20.根据权利要求1的芯片封装，其中所述载体包括陶瓷材料；并且
其中所述至少一个中间层包括接合到所述陶瓷材料的铜层；
其中所述芯片背面和所述至少一个侧壁通过所述铜层被连接到所述载体。
21.一种用于制作芯片封装的方法，所述方法包括：
将芯片至少部分地设置在形成在芯片载体中的至少一个腔体内；
在所述芯片的至少一个侧壁上设置至少一个中间层；所述至少一个中间层从而将来自所述芯片的热量热传导到所述载体；
其中所述至少一个中间层包括
形成在所述芯片背面和所述至少一个侧壁上的第一金属层，其中所述第一金属层形成芯片背面金属化层的至少一部分，和
形成在所述第一金属层上的管芯附着层，其中所述管芯附着层将所述芯片背面和所述至少一个侧壁电连接到所述载体。
22.根据权利要求21的用于制作芯片封装的方法，其中在所述芯片的所述至少一个侧壁上面设置所述至少一个中间层包括在前端工艺中设置所述至少一个中间层。
23.根据权利要求21的用于制作芯片封装的方法，其中在所述芯片的所述至少一个侧壁上面设置至少一个中间层包括在所述芯片背面和所述至少一个侧壁上设置管芯附着材料，其中所述芯片背面和所述至少一个侧壁通过所述管芯附着材料被连接到所述载体。
24.根据权利要求21的用于制作芯片封装的方法，进一步包括通过芯片背面金属化层将所述芯片电连接到所述载体；以及
将所述至少一个中间层电连接到所述芯片背面金属化层。
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