CN103681356A - Method for manufacturing FinFET by using carbon nano tube as mask - Google Patents
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- CN103681356A CN103681356A CN201310739668.3A CN201310739668A CN103681356A CN 103681356 A CN103681356 A CN 103681356A CN 201310739668 A CN201310739668 A CN 201310739668A CN 103681356 A CN103681356 A CN 103681356A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 89
- 239000002041 carbon nanotube Substances 0.000 title claims abstract description 88
- 229910021393 carbon nanotube Inorganic materials 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 230000008569 process Effects 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 27
- 239000002109 single walled nanotube Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000003054 catalyst Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000002048 multi walled nanotube Substances 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
Abstract
The invention provides a method for manufacturing FinFET by using a carbon nano tube as a mask. The method includes forming a one-dimensional carbon nano tube parallel array structure horizontally arranged on a semiconductor substrate; utilizing the carbon nano tube parallel array structure as a mask layer, adopting an anisotropic etching process to etch the semiconductor substrate to form a fin-shaped array structure in the semiconductor substrate, removing the carbon nano tube parallel array structure, and manufacturing a source/drain electrode, a gate electrode and contact holes on the fin-shaped array structure by means of the photoetching and etching process to form a FinFET device. By means of the method, the width of the fin-shaped structure can be effectively controlled, a FinFET device with the fin-shaped structure with small size is manufactured, process difficulty is reduced, and the device performance can be effectively modulated.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind ofly take carbon nano-tube and prepare the method for FinFET as mask.
Background technology
Along with constantly dwindling of semiconductor process techniques node, traditional planar MOSFET has run into increasing technological challenge, FinFET is as a kind of novel three-dimension device structure, can greatly promote the device property of MOSFET, comprise and suppress short channel effect, reduce element leakage, improve drive current and promote Sub-Threshold Characteristic etc.At present, FinFET has become the confessed new device structure that can continue silica-based MOSFET size reduction trend of industry, and will obtain volume production at the following process node of 20 nanometer.
The silicon fin structure of three-dimensional structure (Si Fin) is to realize one of critical process prepared by FinFET device, and the main flow technique of preparing at present Si Fin remains the photoetching technique based on traditional, and in conjunction with advanced semiconductor process techniques, as self aligned side wall technique etc., the minimum widith of prepared Si Fin can only be realized 10～20 nanometer scale conventionally, but, for FinFET device, the width close relation of the lifting of device performance and Si Fin, generally, along with the width of Si Fin reduces, under the control of grid voltage, more easily form the Si Fin entirely exhausting, thereby the remarkable grid-control performance of boost device, the leakage that simultaneously reduces device causes potential barrier and reduces effect, and then obtain high performance FinFET device.At present, the lifting of seeking FinFET device performance remains one of focus of research, especially at the aspects such as structural parameters of improving the preparation technology of FinFET device, optimization FinFET device, remains the direction that many researchers explore.
Carbon nano-tube is as a kind of novel monodimension nanometer material; its unique material behavior can potentially be applied to the preparation and fabrication field of nanostructure; there are some researches show that the carbon nano-tube of utilization does mask material and can prepare undersized SiO2 groove structure (Hye R.; et.al.; Nature Nanotechnol.; vol.2, pp.267,2008; Liu H.T., et.al., J.Am.Chem.Soc., vol.131, pp.17034,2009; Zhao H.B., et.al., Chin.Phys.B, vol.20, pp.108103,2011), but, lack at present the technology that carbon nano-tube mask and FinFET are combined, how the two is become to the problem of needs solution in conjunction with preparing high performance FinFET device.
Summary of the invention
In order to overcome the problems referred to above, the present invention aims to provide a kind ofly take carbon nano-tube and prepares the method for FinFET as mask, thereby carbon nano-tube mask is combined with FinFET technology, reaches the high performance small size FinFET of preparation and cost-saving object.
Of the present inventionly a kind ofly take carbon nano-tube and prepare the method for FinFET as mask, comprise the following steps:
Step S01 a: Semiconductor substrate is provided;
Step S02: form horizontal one dimension carbon nano-tube parallel array structure in described Semiconductor substrate;
Step S03: utilize described carbon nano-tube parallel array structure to do mask layer, adopt the Semiconductor substrate described in anisotropic etch process etching, form fin-shaped array structure in described Semiconductor substrate;
Step S04: remove described carbon nano-tube parallel array structure;
Step S05: through photoetching and etching technics, prepare source/drain electrode, gate electrode and contact hole on described fin-shaped array structure, thereby form described FinFET device.
Preferably, described anisotropic etch process is reactive ion etching process.
Preferably, in described step S02, the method that forms horizontal one dimension carbon nano-tube parallel array structure comprises: directly in described Semiconductor substrate, prepare one dimension carbon nano-tube parallel array or by some carbon nano-tube parallel arrangements in described Semiconductor substrate.
Preferably, the described method of directly preparing one dimension carbon nano-tube parallel array in described Semiconductor substrate comprises:
Steps A 1: form catalyst pattern in described Semiconductor substrate;
Steps A 2: adopt chemical vapour deposition technique, direct growth goes out described one dimension carbon nano-tube parallel array structure in described Semiconductor substrate.
It is preferably, described that by some carbon nano-tube parallel arrangements, the method in described Semiconductor substrate comprises:
Step B1: go out carbon nano-tube parallel array at another Grown;
Step B2: the surface that described carbon nano-tube parallel array is impressed into a flexible material;
Step B3: the carbon nano-tube parallel array on described flexible material surface is transferred in described Semiconductor substrate.
Preferably, in described step S04, adopt chemical corrosion, dry etching or ultrasonic cleaning to remove described carbon nano tube array structure.
Preferably, described step S05 comprises:
Step C1: adopt photoetching and etching technics, etch source/drain electrode figure on described fin-shaped array structure, and grow source/drain structure, thereby form described source/drain electrode;
Step C2: form described gate electrode on described fin-shaped array structure and between described source/drain electrode;
Step C3: form described contact hole on described source/drain electrode.
Preferably, described carbon nano-tube is Single Walled Carbon Nanotube, multi-walled carbon nano-tubes or Single Walled Carbon Nanotube tube bank.
Preferably, described Semiconductor substrate is silicon substrate.
The present invention be take carbon nano-tube and is prepared the method for FinFET as mask, when preparation fin structure, take full advantage of the small size features of one dimension carbon nano-tube material and unique material behavior, without the optical semiconductor lithography by advanced, can prepare the fin structure that width is very little, thereby broken through the restriction of conventional lithography process, for the improvement of FinFET device preparation technology and the lifting of device performance provide a kind of brand-new solution.In addition, the width of the fin structure of the FinFET that the present invention is prepared is mainly determined by the diameter of carbon nano-tube mask material, and generally, the diameter minimum of Single Walled Carbon Nanotube is in 1～2 nanometer range, the diameter of multi-walled carbon nano-tubes is not from 10 nanometer to tens nanometers etc., the diameter of Single Walled Carbon Nanotube tube bank is not according to the quantity difference of Single Walled Carbon Nanotube from several nanometers to tens nanometers etc., as can be seen here, in the present invention, the width of the fin structure of prepared FinFET device can be according to selecting different carbon nano-tube materials to control effectively, thereby method is easily provided to the modulation of FinFET device performance.
Accompanying drawing explanation
Fig. 1 is that the carbon nano-tube of take of a preferred embodiment of the present invention is prepared the schematic flow sheet of the method for FinFET as mask
Fig. 2-8 are above-mentioned preferred embodiment of the present invention take carbon nano-tube and prepares the corresponding cross section structure schematic diagram of each preparation process of the method for FinFET as mask
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Below in conjunction with specific embodiments and the drawings 1-8, to of the present invention, take the method that carbon nano-tube prepares FinFET as mask and be described in further detail.Wherein, Fig. 1 is that the carbon nano-tube of take of a preferred embodiment of the present invention is prepared the schematic flow sheet of the method for FinFET as mask, and Fig. 2-8 are above-mentioned preferred embodiment of the present invention take carbon nano-tube and prepare the corresponding cross section structure schematic diagram of each preparation process of the method for FinFET as mask.
Refer to Fig. 1, the present embodiment of the present invention a kind of be take carbon nano-tube and prepared the method for FinFET as mask, comprises the following steps:
Step S01: refer to Fig. 2, a Semiconductor substrate 1 is provided;
Concrete, the Semiconductor substrate 1 in the present invention can be, but not limited to as silicon substrate, germanium silicon substrate, germanium substrate etc., and in the present embodiment, the Semiconductor substrate 1 adopting is silicon substrate.
Step S02: refer to Fig. 3, form horizontal one dimension carbon nano-tube parallel array structure 2 in Semiconductor substrate 1;
Concrete, in the present invention, the method that forms horizontal one dimension carbon nano-tube parallel array structure 2 in Semiconductor substrate 1 can be, but not limited to direct growth carbon nano-tube parallel array in Semiconductor substrate 1, also the carbon nano-tube parallel array of preparing on other substrate can be transferred in this Semiconductor substrate 1.In the present embodiment, adopt the method for direct growth carbon nano-tube parallel array in Semiconductor substrate, specifically comprise the steps:
Steps A 1: form catalyst pattern in Semiconductor substrate 1;
Steps A 2: adopt chemical vapour deposition technique, direct growth goes out one dimension carbon nano-tube parallel array structure 2 in Semiconductor substrate 1.
Concrete, in the present embodiment, can be, but not limited to adopt photoetching and stripping technology on silicon substrate, to form catalyst pattern, this catalyst pattern can be regular figure, the spacing between catalyst pattern can require to determine according to actual process.In chemical vapor deposition processes, according to chemical vapour deposition (CVD) principle, under the booster action of input air-flow, a large amount of carbon nano-tube are grown between catalyst pattern, thereby form carbon nano-tube parallel array.In another embodiment of the present invention, also the carbon nano-tube parallel array of preparing on other substrate can be transferred in Semiconductor substrate, can be, but not limited to utilize flexible material to prepare as follows:
Step B1: go out carbon nano-tube parallel array at another Grown;
Step B2: the surface that carbon nano-tube parallel array is impressed into a flexible material;
Step B3: the carbon nano-tube parallel array on flexible material surface is transferred in Semiconductor substrate.
Here, first, can adopt conventional more ripe technique first on other substrate, to prepare the parallel display of carbon nano-tube, such as quartz substrate etc.; Then, utilize a flexible material such as PMMA etc. by carbon nano-tube parallel array impression thereon, described impression can be, but not limited to adopt mechanical means to be directly stamped on this flexible material, also can be between carbon nano pipe array filling flexible material, then by this, the flexible material with carbon nano-tube parallel array is placed on silicon substrate, then this flexible material etching off is removed or in follow-up etching process, this flexible material etched away.
The carbon nano-tube adopting in the present invention can be Single Walled Carbon Nanotube, multi-walled carbon nano-tubes or Single Walled Carbon Nanotube tube bank etc., therefore, can be according to the width of different fin structure, select different carbon nano-tube kinds, for the kind of the carbon nano-tube that will grow, adopt different growing method carbon nano tube array grows again.
After prepared by carbon nano tube array structure, then above-mentioned steps S02 proceeds the preparation of the FinFET of the present embodiment.
Step S03: refer to Fig. 4, do mask layer with carbon nano-tube parallel array structure 2, adopt anisotropic etch process etching semiconductor substrate 1, form fin-shaped array structure 3 in Semiconductor substrate 1;
Concrete, in the present invention, can be, but not limited to adopt reactive ion etching process to carry out anisotropic etching to Semiconductor substrate 1, the concrete technology parameter of etching is such as reaction pressure, gas flow, reaction temperature etc. can need to set according to actual process, and the present invention does not impose any restrictions this.
Step S04: refer to Fig. 5, remove carbon nano tube array structure 3;
Concrete, in the present embodiment, it is chemical corrosion method that the method that carbon nano tube array structure 3 is removed can be, but not limited to, and can be also the methods such as dry etching or ultrasonic cleaning.
Step S05: through photoetching and etching technics, prepare source/drain electrode 4, gate electrode 5 and contact hole 6 in Semiconductor substrate 1, thereby form FinFET device.
Concrete, in the present embodiment, this step can be specially:
Step C1: refer to Fig. 6, adopt photoetching and etching technics, on fin-shaped array structure 3, etch source/drain electrode figure, and grow source/drain structure, thus formation source/drain electrode 4;
Here, can be, but not limited to utilize epitaxy technique to carry out growth source/drain structure, this source/drain structure can be, but not limited to as Si or SiGe source/drain structure.
Step C2: refer to Fig. 7, form gate electrode 5 on fin-shaped array structure 3 and between source/drain electrode 4;
Here, can be, but not limited to comprise: first in Semiconductor substrate 1, deposit successively gate medium and grid material, such as gate medium can be high-K gate dielectric etc., grid material can be metal; Then, through photoetching and etching technics, etching gate medium and grid material, thus form gate electrode 5.
Step C3: refer to Fig. 8, form contact hole 6 on source/drain electrode 4.
It should be noted that, prepare the method for source/drain electrode 4, gate electrode 5 and the contact hole 6 of FinFET of the present invention, can adopt the main flow technique of current preparation FinFET to carry out, the present invention does not impose any restrictions this.
In the present invention, the diameter of carbon nano-tube is determining the width of groove and the width of hard mask pattern, thereby effectively controls the width of fin structure, and prepares the fin structure that width is very little, and this performance for modulation FinFET device provides method easily.
In sum, the present invention be take carbon nano-tube and is prepared the method for FinFET as mask, when preparation fin structure, take full advantage of the small size features of one dimension carbon nano-tube material and unique material behavior, without the optical semiconductor lithography by advanced, can prepare the fin structure that width is very little, thereby broken through the restriction of conventional lithography process, for the improvement of FinFET device preparation technology and the lifting of device performance provide a kind of brand-new solution.In addition, the width of the fin structure of the FinFET that the present invention is prepared is mainly determined by the diameter of carbon nano-tube mask material, and generally, the diameter minimum of Single Walled Carbon Nanotube is in 1～2 nanometer range, the diameter of multi-walled carbon nano-tubes is not from 10 nanometer to tens nanometers etc., the diameter of Single Walled Carbon Nanotube tube bank is not according to the quantity difference of Single Walled Carbon Nanotube from several nanometers to tens nanometers etc., as can be seen here, in the present invention, the width of the fin structure of prepared FinFET device can be according to selecting different carbon nano-tube materials to control effectively, thereby method is easily provided to the modulation of FinFET device performance.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (9)
1. the carbon nano-tube of take is prepared a method of FinFET as mask, it is characterized in that, comprises the following steps:
Step S01 a: Semiconductor substrate is provided;
Step S02: form horizontal one dimension carbon nano-tube parallel array structure in described Semiconductor substrate;
Step S03: utilize described carbon nano-tube parallel array structure to do mask layer, adopt the Semiconductor substrate described in anisotropic etch process etching, form fin-shaped array structure in described Semiconductor substrate;
Step S04: remove described carbon nano-tube parallel array structure;
Step S05: through photoetching and etching technics, prepare source/drain electrode, gate electrode and contact hole on described fin-shaped array structure, thereby form described FinFET device.
2. according to claim 1ly take carbon nano-tube and prepare the method for FinFET as mask, it is characterized in that, described anisotropic etch process is reactive ion etching process.
3. according to claim 1ly take carbon nano-tube and prepare the method for FinFET as mask, it is characterized in that, in described step S02, the method that forms horizontal one dimension carbon nano-tube parallel array structure comprises: directly in described Semiconductor substrate, prepare one dimension carbon nano-tube parallel array or by some carbon nano-tube parallel arrangements in described Semiconductor substrate.
4. according to claim 3ly take carbon nano-tube and prepare the method for fin structure as mask, it is characterized in that, the described method of directly preparing one dimension carbon nano-tube parallel array in described Semiconductor substrate comprises:
Steps A 1: form catalyst pattern in described Semiconductor substrate;
Steps A 2: adopt chemical vapour deposition technique, direct growth goes out described one dimension carbon nano-tube parallel array structure in described Semiconductor substrate.
5. according to claim 3ly take carbon nano-tube and prepare the method for fin structure as mask, it is characterized in that, described by some carbon nano-tube parallel arrangements, the method in described Semiconductor substrate comprises:
Step B1: go out carbon nano-tube parallel array at another Grown;
Step B2: the surface that described carbon nano-tube parallel array is impressed into a flexible material;
Step B3: the carbon nano-tube parallel array on described flexible material surface is transferred in described Semiconductor substrate.
6. according to claim 1ly take carbon nano-tube and prepare the method for FinFET as mask, it is characterized in that, in described step S04, adopt chemical corrosion, dry etching or ultrasonic cleaning to remove described carbon nano tube array structure.
7. according to claim 1ly take carbon nano-tube and prepare the method for FinFET as mask, it is characterized in that, described step S05 comprises:
Step C1: adopt photoetching and etching technics, etch source/drain electrode figure on described fin-shaped array structure, and grow source/drain structure, thereby form described source/drain electrode;
Step C2: form described gate electrode on described fin-shaped array structure and between described source/drain electrode;
Step C3: form described contact hole on described source/drain electrode.
8. according to claim 1ly take carbon nano-tube and prepare the method for FinFET as mask, it is characterized in that, described carbon nano-tube is Single Walled Carbon Nanotube, multi-walled carbon nano-tubes or Single Walled Carbon Nanotube tube bank.
9. according to claim 1ly take carbon nano-tube and prepare the method for FinFET as mask, it is characterized in that, described Semiconductor substrate is silicon substrate.
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| CN104637788A (en) * | 2015-01-30 | 2015-05-20 | 北京大学 | Selective area growing method for III-nitride micro graphic structure and structure |
| CN105336566A (en) * | 2014-06-27 | 2016-02-17 | 清华大学 | Preparation method of nanoscale micro structure |
| CN105668540A (en) * | 2014-11-19 | 2016-06-15 | 清华大学 | Preparation method of nanowire array |
| CN106276778A (en) * | 2015-05-21 | 2017-01-04 | 清华大学 | The preparation method of a kind of metal nanowire film and conducting element |
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| CN105336566B (en) * | 2014-06-27 | 2018-10-02 | 清华大学 | A kind of preparation method of nanoscale microstructures |
| CN105668540B (en) * | 2014-11-19 | 2017-11-14 | 清华大学 | A kind of preparation method of nano-wire array |
| CN105668540A (en) * | 2014-11-19 | 2016-06-15 | 清华大学 | Preparation method of nanowire array |
| CN104637788A (en) * | 2015-01-30 | 2015-05-20 | 北京大学 | Selective area growing method for III-nitride micro graphic structure and structure |
| CN106276778B (en) * | 2015-05-21 | 2018-08-14 | 清华大学 | A kind of preparation method and conducting element of metal nanowire film |
| CN106276778A (en) * | 2015-05-21 | 2017-01-04 | 清华大学 | The preparation method of a kind of metal nanowire film and conducting element |
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| CN107026074B (en) * | 2015-10-28 | 2021-07-13 | 三星电子株式会社 | Method for manufacturing semiconductor device |
| TWI653665B (en) | 2017-01-10 | 2019-03-11 | 鴻海精密工業股份有限公司 | Method for making gallium nitride epitaxial layer by silicon substrate |
| CN108695162A (en) * | 2017-04-12 | 2018-10-23 | 联华电子股份有限公司 | The manufacturing method of fin structure |
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| CN109599339A (en) * | 2017-09-29 | 2019-04-09 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor device and forming method thereof |
| US11728215B2 (en) | 2017-09-29 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin Field-Effect Transistor device and method of forming the same |
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