CN103681348A - 一种沟槽金属氧化物半导体场效应管及其制造方法 - Google Patents

一种沟槽金属氧化物半导体场效应管及其制造方法 Download PDF

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CN103681348A
CN103681348A CN201310308826.XA CN201310308826A CN103681348A CN 103681348 A CN103681348 A CN 103681348A CN 201310308826 A CN201310308826 A CN 201310308826A CN 103681348 A CN103681348 A CN 103681348A
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epitaxial loayer
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谢福渊
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LISHI TECHNOLOGY Co Ltd
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Abstract

本发明公开一种由以下步骤制得的沟槽金属氧化物半导体场效应管：在外延层的上表面淀积形成接触绝缘层；提供接触掩模版并刻蚀所述的接触绝缘层形成接触孔洞；在接触孔洞上方对所述外延层进行有角度的源区掺杂剂的离子注入并经过离子扩散形成源区。根据本发明的结构，可以节省源区掩模版并改善源区的电阻特性。

Description

一种沟槽金属氧化物半导体场效应管及其制造方法
技术领域
本发明涉及一种半导体功率器件的器件构造及制造方法。特别涉及一种改进的沟槽金属氧化物半导体场效应管(MOSFET，下同)的器件沟槽及制造方法。
背景技术
图1A所示为美国专利号US6,888,196B2的美国专利中揭示的一种N沟道沟槽MOSFET单元结构。在这个现有技术中，n+源区104具有传统的特点，即沿着n+源区104上表面的方向，从沟道区到沟槽式源体接触区106的侧壁之间，n+源区104具有相同的表面掺杂浓度和相同的结深。此外，该揭示的N沟道沟槽MOSFET形成于一个N型外延层102中并位于一个N+衬底100之上。P型体区103形成于所述的N型外延层102中，所述的n+源区104靠近该P型体区103的上表面，并且延伸于沟槽栅105的上部分和临近的沟槽式源体接触区106的侧壁之间。如图所示，所述的n+源区104在沿其上表面的方向上具有相同的表面掺杂浓度和相同的结深(Ds，如图1A所示)，这与该n+源区104的形成过程有关。
图1B所示为所述的n+源区104的制造方法。在经过P型离子注入和离子扩散形成所述的P型体区103之后，再经由一层源区掩模(未示出)对所述P型体区103的整个上表面进行N型源区掺杂剂的离子注入并进行离子扩散。由于所述的P型体区103的整个上表面承受了同样掺杂浓度的N型离子注入和离子扩散的步骤，因此所述的n+源区104在与其上表面等距离处，具有相同的掺杂浓度和相同的结深。
上述n+源区具有的这种掺杂浓度和结深的均匀分布的特点可能会导致该N沟道沟槽MOSFET在UIS(Unclamped Induetive Switching，非钳位感性开关)测试中产生失效点，如图1C所示。该图为图1A中所示的N沟道沟槽MOSFET单元结构的n+源区104和沟槽式源体接触区106的俯视图，Rbc为沟槽式源体接触区106到单元拐角处的电阻，Rbe为沟槽式源体接触区106到单元边缘处的电阻。由于沟槽式源体接触区106到单元拐角处的距离大于其到单元边缘处的距离，因而Rbc的阻值大于Rbe的阻值，这就会导致在UIS测试中在单元拐角处产生失效点。
因此，在半导体功率器件领域中，尤其是在沟槽MOSFET器件的设计和制造领域中，需要提出一种新颖的器件构造以解决上述的在沟槽MOSFET单元拐角处产生UIS失效点的问题，同时提高器件的雪崩击穿特性。
发明内容
本发明克服了现有技术中存在的缺点，提供了一种改进的沟槽MOSFET的制造方法，可以减小器件的尺寸，并且在制造过程中可以节省源区掩模版，从而减少制造成本。
根据本发明的实施例，提供了一种沟槽金属氧化物半导体场效应管的制造方法，包括：
(1)在第一导电类型的外延层中形成多个第一类沟槽栅和第二导电类型的体区；
(2)在所述外延层的上表面淀积一层接触绝缘层；
(3)提供接触掩模版并在所述的接触绝缘层中刻蚀形成接触孔洞；
(4)通过所述的接触孔洞进行多角度的第一导电类型掺杂剂的离子注入，并进行离子扩散形成源区；和
(5)沿所述的接触孔洞的侧壁进行硅刻蚀，使其穿过所述的源区并延伸入所述的体区。
根据一些优选的实施例，还包括在刻蚀所述的接触孔洞进入所述的体区之后，将通过该接触孔洞进行第二导电类型掺杂剂离子的离子注入，并通过快速热退火或炉退火工序激活所掺杂的离子，形成位于所述的体区中的第二导电类型的体掺杂区，其大部分载流子浓度大于所述的体区，并且至少包围所述的接触沟槽的底部。
根据本发明的实施例，提供了另一种沟槽金属氧化物半导体场效应管的制造方法，包括：
(a)在第一导电类型的衬底上生长所述第一导电类型的外延层，其中所述的外延层的大部分载流子浓度低于所述衬底；
(b)在所述外延层的上表面提供沟槽掩模版，并刻蚀所述外延层形成多个栅沟槽；
(c)在所述的多个栅沟槽的内表面生长牺牲氧化层，并通过移除该牺牲氧化层来消除在刻蚀过程中引入的缺陷；
(d)在所述多个沟槽栅的内表面淀积一层氧化层作为栅极氧化层；
(e)在所述的栅极氧化层上方淀积掺杂的多晶硅层，通过回刻该多晶硅层和栅极氧化层，形成位于有源区的多个第一类沟槽栅、位于栅接触区的至少一个第二类宽沟槽栅和位于终端区的多个第三类悬浮的沟槽栅；
(f)对所述的外延层进行第二导电类型掺杂剂离子的离子注入和扩散，形成体区；
(g)在所述的外延层的上表面淀积一层接触绝缘层；
(h)在所述接触绝缘层上方提供接触掩模版，并刻蚀所述的接触绝缘层形成多个接触孔洞；
(i)通过该多个接触孔洞进行多角度的第一导电类型掺杂剂的离子注入并进行离子扩散形成源区；
(j)沿侧壁继续刻蚀所述的多个接触孔洞使其向下分别延伸入所述的体区和所述的第二类宽沟槽栅；和
(k)对所述的多个接触孔洞进行第二导电类型掺杂剂的离子注入，并进行快速热退火或炉退火工序激活该离子，形成体接触区。
根据一些优选的实施例，其中所述的多角度的第一导电类型掺杂剂的离子注入包括至少两种角度，该两种角度相对于所述的外延层上表面的垂线在5°-30°之间。更优选地，其中所述的多角度的第一导电类型掺杂剂的离子注入包括零角度，该零角度是相对于所述外延层上表面的垂线的角度。
根据本发明的实施例，还提供了一种半导体功率器件，由工艺步骤(1)-(5)制得。
根据本发明的实施例，还提供了一种半导体功率器件，由工艺步骤(a)-(k)制得。
本发明的一个优点是，可以在不使用源区掩模版的条件下对源区进行离子注入，由此可以降低制造成本。
本发明的另一个优点是，由本发明的方法形成的源区可以有效降低源区的寄生电阻。
附图说明
本发明的这些和其他实施方式的优点将通过下面结合附图的详细说明如后，其中：
图1A为现有技术揭示的沟槽MOSFET的剖视图。
图1B为图1A所揭示的沟槽MOSFET的源区制造方法。
图1C为图1A所揭示的沟槽MOSFET的俯视图。
图2A为根据本发明的一个实施例的沟槽MOSFET的源区制造方法。
图2B为根据本发明的一个实施例的沟槽MOSFET的俯视图。
图2C为根据本发明的另一个实施例的沟槽MOSFET的俯视图。
图3A为根据本发明的一个具体实施例的沟槽MOSFET的剖视图，也是图2B或图2C中的俯视图沿X1-X1’方向的剖视图。
图3B为图3A中所揭示的沟槽式源体接触区和沟道区到源区表面的距离和源区多数载流子掺杂浓度之间的曲线关系。
图3C为图2B或图2C中沿X2X2’方向的剖视图。
图4为根据本发明的另一个具体实施例的沟槽MOSFET的剖视图。
图5为根据本发明的另一个具体实施例的沟槽MOSFET的剖视图。
图6为根据本发明的另一个具体实施例的沟槽MOSFET的剖视图。
图7为根据本发明的另一个具体实施例的沟槽MOSFET的剖视图。
图8为根据本发明的另一个具体实施例的沟槽MOSFET的剖视图。
图9A为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图9B为图9A中沿A1B1C1D1方向的剖视图。
图10A为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图10B为图10A中沿A2-B2C2D2方向的剖视图。
图10C为图10A中沿E-F-G方向的剖视图。
图11A为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图11B为图11A中部分区域放大图。
图11C为图11B中沿H-H’方向的剖视图。
图12为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图13为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图14A为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图14B为图14A中沿I-J-K-L方向的剖视图。
图14C为图14A中沿M-M’方向的剖视图。
图15为根据本发明的另一个具体实施例的沟槽MOSFET的俯视图。
图16A-16D为根据图10B所示的本发明实施例的沟槽MOSFET制作过程的剖视图。
图17示出了根据本发明的另一个实施例的沟槽MOSFET的源区制造方法。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。但是本发明不局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实施本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的技术特征可以相互结合，有特别说明的除外。
图2A揭示了根据本发明的实施例的沟槽MOSFET中源区的制造方法，与图1B对照可知，根据本发明的实施例的沟槽MOSFET中的源区的离子注入过程不是位于体区的全部上表面上方，而是在位于体区中央的部分上表面的上方，之后再进行源区掺杂剂离子的横向和纵向扩散。
图2B和2C分别为根据本发明的不同实施例的沟槽MOSFET单元结构的俯视图，其不同之处在于源区掺杂剂离子横向扩散的程度和范围不同。
图3A揭示了根据本发明的一个优选的实施例的有源区(active area)的剖视图。该图同时也示出了图2B或图2C所示俯视图的X1-X1’方向的剖视图。根据该优选的实施例的N沟道沟槽MOSFET形成于N型外延层301中，且位于N+衬底300之上，同时该衬底的下表面衬有漏金属390，其优选地为Ti/Ni/Ag。在所述的N型外延层301中，形成有多个第一类沟槽栅310，其优选地可以由掺杂的多晶硅层形成，且衬有一层栅极氧化层320。P型体区304位于每两个相邻的第一类沟槽栅310之间，其中，靠近所述的P型体区304的上表面，形成有n+源区308。根据本发明的实施例，从沟槽式源体接触区314的侧壁到临近的沟道区之间，该n+源区308的大部分载流子的浓度沿其上表面方向呈现高斯分布的特点。其中，所述的沟槽式源体接触区314填充以金属插塞且衬有一层势垒层316，其中所述的金属插塞可以优选地为钨插塞315，所述的势垒层316可以优选地为Ti/TiN或者Co/TiN或者Ta/TiN。该沟槽式源体接触区314穿过一层接触绝缘层和所述的n+源区308并延伸入所述的P型体区304中，其中所述的接触绝缘层优选地包括：一层未掺杂的SRO(Silicon Rich Oxide，富氧硅)层330-1；和一层BPSG(Boron Phosphorus Silicon Glass，硼磷硅玻璃)层或PSG(Phosphorus Silicon Glass，磷硅玻璃)层330-2。值得注意的是，所述的沟槽式源体接触区314具有垂直的侧壁结构，即其侧壁与所述的n+源区308上表面之间的夹角为90°±5°，但是其在所述的BPSG或PSG层330-2中的沟槽宽度大于位于其他部分的沟槽宽度，这样会提高所述的沟槽式源体接触区314与源金属340之间的接触特性。在所述的沟槽式源体接触区314下方，形成有一个p+体接触区317，其位于所述的P型体区304中，且至少包围所述的沟槽式源体接触区314的底部，以降低所述的钨插塞315和所述的P型体区304之间的接触电阻。此外，所述的接触绝缘层上方形成有一层降阻层318，其优选地为Ti或者Ti/TiN。同时，在该降阻层318上方，形成源金属340以与所述的钨插塞315之间形成电气接触，并且该源金属340优选地为Al合金或Cu。
图3B分别示出了图3A中N沟道沟槽MOSFET的沟槽式源体接触区314和沟道区到n+源区308表面的距离和源区大部分载流子掺杂浓度之间的曲线关系。其中n+代表n+源区308，P代表P型体区304，p+代表p+体接触区317。图3C示出了图2B或图2C中的俯视图沿X2-X2’方向的剖视图。在单元拐角处，n区域328的大部分载流子浓度低于n+源区308，相对于现有技术而言，耐压增大，从而进一步提高了沟槽MOSFET的雪崩击穿特性。
图4示出了根据本发明的另一个优选的实施例的N沟道沟槽MOSFET的有源区的一个剖视图，其与图3A所示的优选的实施例有相似的结构，不同之处在于，在图4中每个沟槽式源体接触区414只在BPSG或PSG层430-2中具有垂直的侧壁结构，而在未掺杂的SRO层430-1、n+源区408和在P型体区404中都具有倾斜的侧壁结构。通过采用这样的倾斜的侧壁结构，增大了p+体接触区417与所述的沟槽式源体接触区414之间的接触面积，从而进一步降低了钨插塞415与所述的P型体区404之间的接触电阻，提高了雪崩击穿特性。
图5示出了根据本发明的另一个优选的实施例的N沟道沟槽MOSFET的有源区的一个剖视图，其与图4所示的优选的实施例有着相似的结构，不同之处在于，在图5中所述的沟槽式源体接触区514仅在P型体区504中具有倾斜的侧壁结构，而在n+源区508和未掺杂的SRO层530-1中都具有垂直的侧壁结构，采取这样的侧壁结构可以在有效增大p+体接触区517与所述的沟槽式源体接触区514之间接触面积的同时，避免在所述的n+源区中引入其他的掺杂剂离子从而保证良好的源区接触特性。
图6示出了根据本发明的另一个优选的实施例的N沟道沟槽MOSFET的有源区的一个剖视图，其与图3A所示的优选的实施例有着相似的结构，不同之处在于，在图6中所述的沟槽式源体接触区614中的金属插塞优选地为源金属640，并衬有一层势垒层616。
图7示出了根据本发明的另一个优选的实施例的N沟道沟槽MOSFET的有源区的一个剖视图，其与图4所示的优选的实施例有着相似的结构，不同之处在于，在图7中所述的沟槽式源体接触区714中的金属插塞优选地为源金属740，并衬有一层势垒层716。
图8示出了根据本发明的另一个优选的实施例的N沟道沟槽MOSFET的有源区的一个剖视图，其与图5所示的优选的实施例有着相似的结构，不同之处在于，在图8中所述的沟槽式源体接触区814中的金属插塞优选地为源金属840，并衬有一层势垒层816。
图9A示出了根据本发明的另一个优选的实施例的沟槽MOSFET的俯视图，其具有由封闭单元结构(正方形或矩形单元结构)构成的有源区和由多个悬浮沟槽栅构成的终端区。其沿A1-B1-C1-D1方向的剖视图如图9B所示。该剖视图包括：有源区、栅接触区和终端区。其中，有源区的结构采用图3A中所示的实施例，包括多个第一类沟槽栅350。栅接触区位于所述的有源区和所述的终端区之间，包括至少一个第二类宽沟槽栅354，其宽度和深度都大于所述的第一类沟槽栅350。所述的第一类沟槽栅350都通过所述的第二类宽沟槽栅354由沟槽式栅接触区359中的钨插塞360连接至栅金属362。终端区包括多个第三类悬浮的沟槽栅352，其具有悬浮的电压且周围环绕有不包括n+源区的P型体区364，同时所述的第三类悬浮的沟槽栅352的宽度和深度都等于或大于所述的第一类沟槽栅350。其中，所述的第一类沟槽栅350、第二类宽沟槽栅354和第三类悬浮的沟槽栅352都优选地由掺杂的多晶硅层形成并衬有一层栅极氧化层353。
图10A示出了根据本发明的另一个优选的实施例的沟槽MOSFET的俯视图，其具有由封闭单元结构(正方形或矩形)构成的有源区和由多个悬浮沟槽栅构成的终端区。其沿A2-B2-C2-D2方向的剖视图如图10B所示。该剖视图包括：有源区、栅接触区和终端区。与图9B相比的不同之处在于，图10B中所述的N沟道沟槽MOSFET还包括一个第四类沟槽栅440，其位于所述的有源区边缘，作用在于阻止位于有源区边缘的n+源区(如图10B所示)的过度横向扩散，从而提高器件的雪崩击穿特性。此外，所述的第四类沟槽栅440通过位于一个沟槽式边缘接触区441中的钨插塞446而短接至源金属442。图10C示出了图10A中沿E-F-G方向的剖视图，根据图10B和图10C可以看出，位于有源区和靠近栅接触区的P型体区443都短接至源金属442，而位于所述的终端区中的P型体区443’具有悬浮的电压。
图11A示出了根据本发明的另一个优选的实施例的沟槽MOSFET的俯视图，图11B示出了根据图11A中有源区的优选的放大示意图，同时，图11B中沿H-H’界面的剖视图如图11C所示。结合图11A、图11B和图11C可以看出，该沟槽MOSFET的有源区中包括：A类沟槽式源体接触区和B类沟槽式源体接触区，其中A类沟槽式源体接触区的沟槽宽度小于B类沟槽式源体接触区(A类和B类沟槽式源体接触区的个数根据具体的实施例确定)。因此，在图11C中，位于所述的B型沟槽式源体接触区下方的p+体接触区497的横向宽度大于位于所述的A型沟槽式源体接触区下方的p+体接触区497’的横向宽度，进而p+体接触区497比497’更靠近位于有源区的第一类沟槽栅498。因此，将包含所述的B型沟槽式源体接触区的单元作为缓冲单元，其Vth(阈值电压)必然大于包含所述的A型沟槽式源体接触区的普通单元，这是由于当提供栅极电压偏置时，由于p+体接触区497更接近沟道区，缓冲单元就不会被首先开启。
图12示出了根据本发明的另一个优选的实施例的沟槽MOSFET的俯视图，其具有由带状单元结构构成的有源区和由多个悬浮沟槽栅构成的终端区，其中位于有源区中的沟槽式源体接触区具有相同的沟槽宽度。图13示出了根据本发明的另一个优选的实施例的沟槽MOSFET的俯视图，其具有由带状单元结构构成的有源区和由多个悬浮沟槽栅构成的终端区，其中靠近有源区边缘的沟槽式源体接触区的沟槽宽度最大。
图14A示出了根据本发明的另一个优选的实施例的N沟道沟槽MOSFET的俯视图，其沿I-J-K-L方向的剖视图如图14B所示，其沿M-M’截面的剖视图如图14C所示。结合图14B与图14C可以看出，与图9B相比，根据该实施例的N沟道沟槽MOSFET中位于有源区和栅接触区之间的P型体区620不是通过沟槽式源体接触区短接至源金属621，而是具有悬浮的电压。
图15示出了根据本发明的另一个优选的实施例的沟槽MOSFET的俯视图，与图14A有着相似的结构，不同之处在于图14A所示的沟槽MOSFET的有源区具有封闭的单元结构，而图15中所示的沟槽MOSFET具有带状的单元结构。
图16A至图16D为制造图10B所示的本发明的一个优选的实施例的制造方法和步骤。如图16A所示，首先，N型外延层435形成于N+衬底436之上，其中，所述的N+衬底436的大部分载流子浓度高于所述的N型外延层435。之后，在所述的N型外延层435的上表面提供一层沟槽掩模版(未示出)，根据该沟槽掩模版的定义，在所述的N型外延层435中刻蚀形成多个栅沟槽(437-1-437-4)并至一定的深度。然后，形成一层牺牲氧化层(未示出)并通过去除该牺牲氧化层来消除刻蚀栅沟槽的过程中可能引入的缺陷。接着，在所有栅沟槽(437-1-437-4)的内表面和N型外延层435的上表面形成一层氧化层并在其上淀积一层掺杂的多晶硅用来填充栅沟槽。之后，通过CMP(化学机械抛光)或等离子刻蚀移除位于N型外延层435表面的氧化层和掺杂的多晶硅，使其填充于栅沟槽中用来形成栅极氧化层438和多个沟槽栅，其中所述的多个沟槽栅包括：多个第一类沟槽栅439-1，至少一个第二类宽沟槽栅439-2，第三类悬浮的沟槽栅439-3和第四类沟槽栅440。接着，在整个结构的上方进行P型体区掺杂剂离子的离子掺杂和离子扩散以形成P型体区443和443’，其中P型体区443’位于终端区。
在图16B中，首先在图16A中的结构的上表面先后淀积一层未掺杂的SRO层444-1和一层BPSG或PSG层444-2。之后，提供一层接触掩模版(未示出)，根据该接触掩模版的定义，先后刻蚀所述的BPSG或PSG层444-2、所述的未掺杂的SRO层444-1，形成多个接触孔洞(445-1-445-3)。接着，移除所述的接触掩模版，沿所述的多个接触孔洞(445-1-445-3)的内表面和所述的BPSG或PSG层444-2的上表面淀积一层厚度约为300A的屏蔽氧化层(screen oxide，未示出)。然后，进行n+源区掺杂剂离子的离子注入通过接触孔洞进入P型体区，并进行离子扩散以形成n+源区448。
在图16C中，先通过干法或湿法的氧化层刻蚀移除所述的屏蔽氧化层，再对所述的多个接触孔洞沿其侧壁进行干法硅刻蚀，使得：接触孔洞445-1进一步穿过所述的n+源区448而延伸入P型体区；接触孔洞445-2延伸入所述的第四类沟槽栅440；接触孔洞445-3延伸入所述的第二类宽沟槽栅439-2。之后，进行BF2离子注入以形成p+体接触区447，并通过快速热退火或炉退火工序以激活该掺杂的离子。
在图16D中，现在稀HF氛围中进行湿法刻蚀，扩大所述的多个接触孔洞(445-1-4453，如图16C所示)位于所述的BPSG或PSG层4442中的宽度。然后，在所述的多个接触孔洞(445-1-445-3，如图16C所示)的内表面和所述的BPSG或PSG层444-2的上表面淀积一层Ti/TiN或Co/TiN或Ta/TiN作为势垒层(未示出)，并在其上淀积金属钨449，之后，通过回刻该金属钨和势垒层，使二者位于所述的多个接触孔洞中(445-1-445-3，如图16C所示)，分别形成：沟槽式源体接触区450、沟槽式边缘接触区441和沟槽式栅接触区451。接着，在所形成的结构的上表面淀积一层降阻层Ti或Ti/TiN(未示出)，并在其上淀积金属层Al合金或铜，通过金属掩模版(未示出)的定义刻蚀该金属层和降阻层，使其形成源金属442和栅金属452。最后，对N+衬底436的下表面进行研磨并淀积形成漏金属453。
图17示出了一个制作n+源区更优选的方法，其包括通过所述的接触孔洞进行n+源区掺杂剂离子的多角度的离子注入并进行离子扩散，其中所述的多角度包括零角度和至少两个倾斜角度的离子注入，并且相对于所述外延层435’的上表面的垂线，该倾斜角度的范围在5°-30°之间。通过这种多角度的离子注入形成的n+源区448’，其到临近的沟道区的横向浓度增加，进而降低了位于n+源区448’的寄生电阻的大小。
尽管在此说明了各种实施例，可以理解，在不脱离本发明的精神和范围内可以对本发明作出各种修改。例如，可以用本发明的方法形成其导电类型与文中所描述的相反的导电类型的各种半导体区域的结构，但所作出的修改应包涵在本发明要求保护的权利要求范围之内。

Claims (11)

1.一种沟槽金属氧化物半导体场效应管的制造方法，包括：
在第一导电类型的外延层中形成多个第一类沟槽栅和第二导电类型的体区；
在所述外延层的上表面淀积一层接触绝缘层；
提供接触掩模版并在所述的接触绝缘层中刻蚀形成接触孔洞；
通过所述的接触孔洞进行多角度的第一导电类型掺杂剂的离子注入，并进行离子扩散形成源区；和
沿所述的接触孔洞的侧壁进行硅刻蚀，使其穿过所述的源区并延伸入所述的体区。
2.根据权利要求1所述的沟槽金属氧化物半导体场效应管的制造方法，还包括在刻蚀所述的接触孔洞进入所述的体区之后，将通过该接触孔洞进行第二导电类型掺杂剂离子的离子注入，并通过快速热退火或炉退火工序激活所掺杂的离子，形成位于所述的体区中的第二导电类型的体掺杂区，其大部分载流子浓度大于所述的体区，并且至少包围所述的接触沟槽的底部。
3.根据权利要求1所述的沟槽金属氧化物半导体场效应管的制造方法，还包括在所述的接触孔洞内淀积形成势垒层和金属插塞。
4.根据权利要求1所述的沟槽金属氧化物半导体场效应管的制造方法，其中所述的多角度的第一导电类型掺杂剂的离子注入包括至少两种角度，该两种角度相对于所述的外延层上表面的垂线在5°-30°之间。
5.根据权利要求4所述的沟槽金属氧化物半导体场效应管的制造方法，其中所述的多角度的第一导电类型掺杂剂的离子注入包括零角度，该零角度相对于所述外延层上表面的垂线的角度。
6.一种沟槽金属氧化物半导体场效应管的制造方法，包括：
在第一导电类型的衬底上生长所述第一导电类型的外延层，其中所述的外延层的大部分载流子浓度低于所述衬底；
在所述外延层的上表面提供沟槽掩模版，并刻蚀所述外延层形成多个栅沟槽；
在所述的多个栅沟槽的内表面生长牺牲氧化层，并通过移除该牺牲氧化层来消除在刻蚀过程中引入的缺陷；
在所述多个沟槽栅的内表面淀积一层氧化层作为栅极氧化层；
在所述的栅极氧化层上方淀积掺杂的多晶硅层，通过回刻该多晶硅层和栅极氧化层，形成位于有源区的多个第一类沟槽栅、位于栅接触区的至少一个第二类宽沟槽栅和位于终端区的多个第三类悬浮的沟槽栅；
对所述的外延层进行第二导电类型掺杂剂离子的离子注入和扩散，形成体区；
在所述的外延层的上表面淀积一层接触绝缘层；
在所述接触绝缘层上方提供接触掩模版，并刻蚀所述的接触绝缘层形成多个接触孔洞；
通过该多个接触孔洞进行多角度的第一导电类型掺杂剂的离子注入并进行离子扩散形成源区；
沿侧壁继续刻蚀所述的多个接触孔洞使其向下分别延伸入所述的体区和所述的第二类宽沟槽栅；和
对所述的多个接触孔洞进行第二导电类型掺杂剂的离子注入，并进行快速热退火或炉退火工序激活该离子，形成体接触区。
7.根据权利要求6所述的沟槽金属氧化物半导体场效应管的制造方法，还包括在所述的多个接触孔洞内淀积形成势垒层和金属插塞。
8.根据权利要求6所述的沟槽金属氧化物半导体场效应管的制造方法，其中所述的多角度的第一导电类型掺杂剂的离子注入包括至少两种角度，该两种角度相对于所述的外延层上表面的垂线在5°-0°之间。
9.根据权利要求8所述的沟槽金属氧化物半导体场效应管的制造方法，其中所述的多角度的第一导电类型掺杂剂的离子注入包括零角度，该零角度相对于所述外延层上表面的垂线的角度。
10.一种半导体功率器件，由权利要求1制得。
11.一种沟槽金属氧化物半导体场效应管，由权利要求6制得。
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