CN103681318B - Use the method that the selective oxidation technology of silicon manufactures junction barrier schottky diode - Google Patents
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 55
- 239000010703 silicon Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000004888 barrier function Effects 0.000 title claims abstract description 31
- 230000003647 oxidation Effects 0.000 title claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 15
- 238000005516 engineering process Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 42
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 36
- 239000004568 cement Substances 0.000 claims description 36
- 230000003287 optical effect Effects 0.000 claims description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 32
- 239000013078 crystal Substances 0.000 claims description 28
- -1 compound ions Chemical class 0.000 claims description 23
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 8
- 238000005245 sintering Methods 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000035755 proliferation Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Condensed Matter Physics & Semiconductors (AREA)
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- Electrodes Of Semiconductors (AREA)
Abstract
The method that a kind of selective oxidation technology using silicon of disclosure manufactures junction barrier schottky diode, use LOCOS(local oxidation of silicon) formation of silicon oxide, the range of scatter of the foreign ion injected effectively is confined between LOCOS region of silicon oxide, thus effectively reducing the P region of PN junction or the scope of the n-quadrant laterally diffusion of (horizontal direction), thus decrease the Schottky interface shared by P region or n-quadrant horizontal proliferation, therefore the area of Schottky interface can be fully utilized, effective schottky barrier interface is bent to curved surface thus increasing conductive area simultaneously, compensate the area that special-shaped island takies, thus improve function and the efficiency of the energising of barrier junction Schottky diode forward.
Description
Technical field
The present invention designs diode and manufactures field, is specifically related to a kind of method that selective oxidation technology using silicon manufactures junction barrier schottky diode.
Background technology
Schottky diode is the low-power consumption come out in recent years, big electric current, ultra-speed semiconductor device.Its reverse recovery time extremely short (may diminish to a few nanosecond), forward conduction voltage drop is about 0.4V only, and rectified current can reach several thousand milliamperes.These good characteristics be fast recovery diode incomparable.Schottky diode is to utilize the metal-semiconductor junction principle that metal and semiconductor contact are formed to be made, the metal-semiconductor that is otherwise known as (contact) diode or surface barrier diode.
The Schottky barrier interface that normal schottky diode has between coating metal and silicon layer.This interface can turn on big forward current when forward voltage；And stoping current flowing under reverse voltage conditions, only a small amount of reverse leakage occurs.When reverse biased strengthens, reverse leakage can along with increasing, and this is the natural physical characteristic of Schottky barrier.The problem increased to overcome this reverse leakage to increase along with backward voltage, and a kind of junction barrier schottky diode designed, this junction barrier schottky diode adds the zonule of " P " or " N " type semiconductor ion diffusion of multiple isolation under the Schottky barrier interface of normal schottky diode, and the epitaxial region of these " P " type regions and " N " type forms the epitaxial region of multiple PN junction or " N " type region and " P " type and forms multiple PN junction.When reverse biased strengthens, these PN junctions form one layer of vague and general layer under Schottky barrier interface, the thickness of this vague and general layer can increase along with backward voltage and expand, thus reduces the impact on Schottky barrier interface of the electric field of backward voltage, reaches the purpose that reverse leakage can be greatly lowered.But the shortcoming existing for this barrier Schottky diode is: occupy the area of a part of original Schottky barrier interface owing to adding " P " or " N " type island region；So when forward voltage, it is possible to the area of On current diminishes, so the reduction that forward current also can be relative, thus reduce function and the efficiency of forward conduction electric current.Therefore, how to limit addition " P " or " N " type semiconductor ion scope that laterally (horizontal direction) spreads, effective schottky barrier interface is bent to curved surface thus increasing conductive area simultaneously, compensate the area that special-shaped island takies, be the problem needing in barrier Schottky diode manufacturing process to solve.
Summary of the invention
The technical problem to be solved is to provide a kind of method using selective oxidation technology using silicon to manufacture junction barrier schottky diode, the method can reduce " P " or " N " special-shaped semiconductor ion scope that laterally (horizontal direction) spreads of addition, effective schottky barrier interface is bent to curved surface thus increasing conductive area simultaneously, compensate the area that special-shaped island takies, be effectively improved function and the efficiency of the energising of barrier junction Schottky diode forward.
For solving the problems referred to above, the present invention is achieved by the following scheme:
A kind of method that selective oxidation technology using silicon manufactures junction barrier schottky diode, including crystal generation step and encapsulation step, wherein crystal generation step includes:
(1) at silicon chip substrate overlying lid layer silicon epitaxy layer；
(2) first grow up on silicon epitaxy layer silicon oxide one layer thin, it deposits one layer of silicon nitride again；
(3) forming multiple block optical cement region by photoetching process on silicon nitride layer surface, these block optical cement regions are each independently distributed and cover silicon nitride layer surface；
(4) with dry ecthing method, the silicon nitride etch under the region not having optical cement to cover is fallen, then optical cement is removed clean；
(5) using the silicon oxide that boiler tube sintering process is the two-way growth thick layer of upper and lower surface of silicon oxide in the region not having silicon nitride, now due to the growth that silicon oxide is downward, silicon face becomes the lower prominent curved surface that some are separate；
(6) use phosphoric acid that remaining silicon nitride is removed；
(7) in step (6) gained plane of crystal ion implantation implanting impurity ion, the now region of the wafer surface silicon oxide of (5) described thickness in steps, foreign ion is blocked from entering to silicon face；
(8) by boiler tube sintering process, foreign ion is diffused to below silicon chip surface and form PN junction with lower prominent curved regions；
(9) forming a ring-type optical cement region by photoetching process in the surface of step (8) gained crystal, this ring-type optical cement region is positioned at the edge of plane of crystal and covers plane of crystal；
(10) with dry or wet etch method, the silicon oxide under the region not having optical cement to cover is etched away, then optical cement is removed clean；
(11) in step (10) gained wafer surface Schottky metal, and the Schottky interface of metallic silicon is formed with boiler tube or quick heat treatment method；
(12) in the surface metal-layer of step (11) gained wafer surface evaporation or sputter thick layer, then with photoetching and engraving method, surface metal-layer is carried out separating or independent；
(13) silicon chip substrate is thinned to suitable thickness, and at wafer bottom surface evaporation or sputter metal layer on back.
In above-mentioned steps (2), described silicon oxide is SiO2, described silicon nitride is Si3N4。
In above-mentioned steps (2), the thickness of silicon oxide is less than the thickness of silicon nitride.
In above-mentioned steps (8), foreign ion diffusion depth in vertical direction is the degree of depth of prominent curved surface less than or equal under epitaxial layer.
In said method, when using N+ type silicon chip substrate, then the epitaxial layer covered is N-type epitaxial layer, the boron ion that foreign ion is P type injected or the compound ions of boron；Additionally, when using P+ type silicon chip substrate, then the epitaxial layer covered is P-type epitaxial layer, and the ion injected is phosphonium ion or the arsenic ion of N-type.
Compared with prior art, the present invention uses LOCOS(local oxidation of silicon) formation of silicon oxide, the range of scatter of the foreign ion injected effectively is confined between LOCOS region of silicon oxide, thus effectively reducing the P region of PN junction or the scope of the n-quadrant laterally diffusion of (horizontal direction), thus decrease the Schottky interface shared by P region or n-quadrant horizontal proliferation, therefore the area of Schottky interface can be fully utilized, effective schottky barrier interface is bent to curved surface thus increasing conductive area simultaneously, compensate the area that special-shaped island takies, thus improve function and the efficiency of the energising of barrier junction Schottky diode forward.
Accompanying drawing explanation
Fig. 1-Fig. 9 is each obtained crystal structure schematic diagram step by step of crystal generation step described in embodiment 1.
In order to implement, crystal generation step described in 2 is finally obtained obtains crystal structure schematic diagram to Figure 10.
Detailed description of the invention
Embodiment 1:
A kind of method that selective oxidation technology using silicon manufactures junction barrier schottky diode, including crystal generation step and encapsulation step, wherein crystal generation step includes:
(1) at N+ type silicon chip substrate overlying lid layer N-type silicon epitaxy layer.As shown in Figure 1.
(2) first grow up on N-type silicon epitaxy layer silicon oxide one layer thin, it deposits one layer of silicon nitride again；And the thickness of silicon oxide is less than the thickness of silicon nitride.In the present embodiment, described silicon oxide is SiO2, its thickness is about 300 angstroms；Described silicon nitride is Si3N4, its thickness is about 2000 angstroms.
(3) forming multiple block optical cement region on silicon nitride layer surface by photoetching process, distribution that these block optical cement regions are each independent also covers silicon nitride layer surface.As shown in Figure 2.
(4) with dry ecthing method, the silicon nitride etch of (now for not having optical cement covering part) under non-block optical cement region is fallen, then optical cement is removed totally.As shown in Figure 3.
(5) using boiler tube sintering process silicon oxide of upper and lower two-way growth thick layer in non-block optical cement region (now for not having silicon nitride overlay area), its thickness is about 1um.Due to the growth that silicon oxide is downward, silicon lower surface becomes the lower prominent curved surface that some are separate；And due to silicon oxide growth upwards, silicon upper surface becomes the upper prominent curved surface that some are separate.As shown in Figure 4.
(6) use phosphoric acid that remaining silicon nitride is removed.
(7) in the compound ions of step (6) the gained plane of crystal boron ion by ion implantation implanting p-type or boron.Now, the region of the silicon oxide of (5) described thickness in steps due to wafer surface, the compound ions of boron ion or boron is blocked from entering to silicon face, and namely the compound ions of boron ion or boron is limited between lower prominent curved surface.As shown in Figure 5.
(8) by boiler tube sintering process, the compound ions of boron or boron is diffused to below silicon face and form PN junction with lower prominent curved regions.Due to the stop of thick silicon oxide, the compound ions of boron or boron diffusion breadth in the horizontal direction is limit between thick silicon oxide layer.It addition, the diffusion depth that the compound ions of boron or boron is in vertical direction is less than or equal to the degree of depth of sunk area, namely elevation of water residing for the bottommost after the compound ions diffusion of boron or boron is higher than elevation of water residing for the bottommost of thick silicon oxide layer.As shown in Figure 6.
(9) forming a ring-type optical cement region by photoetching process in the surface of step (8) gained crystal, this ring-type optical cement region is positioned at the edge of plane of crystal and covers plane of crystal.As shown in Figure 7.
(10) with dry or wet etch method, the silicon oxide under the region not having optical cement to cover is etched away, then optical cement is removed clean.As shown in Figure 8.
(11) in step (10) gained wafer surface Schottky metal, and the Schottky interface of metallic silicon is formed with boiler tube or quick heat treatment method.As shown in Figure 9.
(12) in the anode surface metal level of step (11) gained wafer surface evaporation or sputter thick layer, then with photoetching and engraving method, anode surface metal level is carried out separating or independent.
(13) silicon chip substrate is thinned to suitable thickness, and at wafer bottom surface evaporation or sputtering cathode metal layer on back.
Embodiment 2:
The N-type of embodiment 1 and P type can be exchanged by the present embodiment 2, and obtain with P+ type substrate, the barrier junction Schottky diode of P-type epitaxial layer and N-type ion implanting, as shown in Figure 10.Namely
A kind of method that selective oxidation technology using silicon manufactures junction barrier schottky diode, including crystal generation step and encapsulation step, wherein crystal generation step includes:
(1) at P+ type silicon chip substrate overlying lid layer P-type silicon epitaxy layer；As shown in Figure 1.
(2) first grow up on P-type silicon epitaxy layer silicon oxide one layer thin, it deposits one layer of silicon nitride again；And the thickness of silicon oxide is less than the thickness of silicon nitride.In the present embodiment, described silicon oxide is SiO2, its thickness is about 300A；Described silicon nitride is Si3N4, its thickness is about 2000A.Above-mentioned 1A=10-4u。
(3) forming multiple block optical cement region on silicon nitride layer surface by photoetching process, distribution that these block optical cement regions are each independent also covers silicon nitride layer surface.
(4) with dry ecthing method, the silicon nitride etch of (now for not having optical cement covering part) under non-block optical cement region is fallen, then optical cement is removed totally.
(5) using boiler tube sintering process silicon oxide of upper and lower two-way growth thick layer in non-block optical cement region (now for not having silicon nitride overlay area), its thickness is about 1um.Due to the growth that silicon oxide is downward, silicon lower surface becomes the lower prominent curved surface that some are separate；And due to silicon oxide growth upwards, silicon upper surface becomes the upper prominent curved surface that some are separate.
(6) use phosphoric acid that remaining silicon nitride is removed.
(7) phosphonium ion or the arsenic ion of N-type is injected in step (6) gained plane of crystal ion implantation.Now, the region of the silicon oxide of (5) described thickness in steps due to wafer surface, phosphonium ion or arsenic ion are blocked from entering to silicon face, and namely phosphonium ion or arsenic ion are limited between lower prominent curved surface.
(8) by boiler tube sintering process, phosphonium ion or arsenic ion are diffused to below silicon face and form PN junction with lower prominent curved regions.Due to the stop of thick silicon oxide, phosphonium ion or arsenic ion diffusion breadth in the horizontal direction is limit between thick silicon oxide layer.It addition, the diffusion depth that phosphonium ion or arsenic ion are in vertical direction is less than or equal to the degree of depth of sunk area, namely elevation of water residing for the bottommost after phosphonium ion or arsenic ion diffusion is higher than elevation of water residing for the bottommost of thick silicon oxide layer.
(9) forming a ring-type optical cement region by photoetching process in the surface of step (8) gained crystal, this ring-type optical cement region is positioned at the edge of plane of crystal and covers plane of crystal.
(10) with dry or wet etch method, the silicon oxide under the region not having optical cement to cover is etched away, then optical cement is removed clean.
(11) in step (10) gained wafer surface Schottky metal, and the Schottky interface of metallic silicon is formed with boiler tube or quick heat treatment method；As shown in Figure 10.
(12) in the cathode surface metal level of step (11) gained wafer surface evaporation or sputter thick layer, then with photoetching and engraving method, cathode surface metal level is carried out separating or independent.
(13) silicon chip substrate is thinned to suitable thickness, and at wafer bottom surface evaporation or sputter anode metal layer on back.
Claims (5)
1. use the method that the selective oxidation technology of silicon manufactures junction barrier schottky diode, including crystal generation step and encapsulation step, it is characterised in that: described crystal generation step includes:
(1) at silicon chip substrate overlying lid layer silicon epitaxy layer；
(2) first grow up on silicon epitaxy layer silicon oxide one layer thin, it deposits one layer of silicon nitride again；
(3) forming multiple block optical cement region by photoetching process on silicon nitride layer surface, these block optical cement regions are each independently distributed and cover silicon nitride layer surface；
(4) with dry ecthing method, the silicon nitride etch under the region not having optical cement to cover is fallen, then optical cement is removed clean；
(5) using the silicon oxide that boiler tube sintering process is the two-way growth thick layer of upper and lower surface of silicon oxide in the region not having silicon nitride, now due to the growth that silicon oxide is downward, silicon face becomes the lower prominent curved surface that some are separate；
(6) use phosphoric acid that remaining silicon nitride is removed；
(7) in step (6) gained plane of crystal ion implantation implanting impurity ion, the now region of the surface of the wafer silicon oxide of (5) described thickness in steps, foreign ion is blocked from entering to silicon face；
(8) by boiler tube sintering process, foreign ion being diffused to silicon chip surface P region formed below, its silicon epitaxy layer with lower floor's N-type constitutes PN junction；
(9) forming a ring-type optical cement region by photoetching process in the surface of step (8) gained crystal, this ring-type optical cement region is positioned at the edge of plane of crystal and covers plane of crystal；
(10) with dry or wet etch method, the silicon oxide under the region not having optical cement to cover is etched away, then optical cement is removed clean；
(11) in the surface Schottky metal of step (10) gained wafer, and the schottky interface of metallic silicon is formed with boiler tube or quick heat treatment method；
(12) in the surface metal-layer of the surface of step (11) gained wafer evaporation or sputter thick layer, then with photoetching and engraving method, surface metal-layer is carried out separating or independent；
(13) silicon chip substrate is thinned to suitable thickness, and at the bottom surface of wafer evaporation or sputter metal layer on back.
2. use the method that the selective oxidation technology of silicon manufactures junction barrier schottky diode according to claim 1, it is characterised in that: in step (2), described silicon oxide is SiO2, described silicon nitride is Si3N4。
3. the method that the selective oxidation technology of use silicon according to claim 1 or claim 2 manufactures junction barrier schottky diode, it is characterised in that: in step (2), the thickness of silicon oxide is less than the thickness of silicon nitride.
4. use the method that the selective oxidation technology of silicon manufactures junction barrier schottky diode according to claim 1, it is characterised in that: in step (8), foreign ion diffusion depth in vertical direction is the degree of depth of prominent curved surface less than or equal under epitaxial layer.
5. use the method that the selective oxidation technology of silicon manufactures junction barrier schottky diode according to claim 1, it is characterised in that:
When using N+ type silicon chip substrate, then the epitaxial layer covered is N-type epitaxial layer, and the foreign ion injected is the compound ions of the boron ion of P type or boron；
When using P+ type silicon chip substrate, then the epitaxial layer covered is P-type epitaxial layer, and the foreign ion injected is phosphonium ion or the arsenic ion of N-type.
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| CN105590850A (en) * | 2014-10-23 | 2016-05-18 | 无锡华润华晶微电子有限公司 | Schottky diode manufacturing method |
| CN106298775B (en) * | 2015-05-20 | 2019-12-24 | 北大方正集团有限公司 | Hybrid rectifier diode and manufacturing method thereof |
| CN105226103A (en) * | 2015-10-14 | 2016-01-06 | 上海芯石微电子有限公司 | Containing schottky device and the manufacture method of directed diffusion junctions |
| CN105762076B (en) * | 2016-02-29 | 2019-01-18 | 重庆平伟实业股份有限公司 | A kind of production technology of diffused high-voltage great-current Schottky chip |
| CN106298977B (en) * | 2016-10-26 | 2019-11-15 | 苏州捷芯威半导体有限公司 | Diode anode structure, longitudinal diode and transverse diode |
| CN107221604A (en) * | 2017-06-01 | 2017-09-29 | 深圳市华星光电技术有限公司 | Organic Light Emitting Diode and manufacture method |
| CN113130624A (en) * | 2021-03-26 | 2021-07-16 | 先之科半导体科技(东莞)有限公司 | Low-loss Schottky rectifier tube and forming process thereof |
| CN113314618A (en) * | 2021-06-04 | 2021-08-27 | 厦门吉顺芯微电子有限公司 | Planar Schottky rectifier device with increased contact area and manufacturing method thereof |
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| DE19853743C2 (en) * | 1998-11-21 | 2000-10-12 | Micronas Intermetall Gmbh | Semiconductor component with at least one Zener diode and at least one Schottky diode connected in parallel thereto, and method for producing the semiconductor components |
| CN1591908A (en) * | 2003-08-18 | 2005-03-09 | 谢福淵 | Junction barrier schottky device of low forward flow voltage drop and high reverse blocking voltage |
| JP4695402B2 (en) * | 2005-01-26 | 2011-06-08 | パナソニック株式会社 | Manufacturing method of Schottky barrier diode |
| CN101452967B (en) * | 2007-11-30 | 2010-11-03 | 上海华虹Nec电子有限公司 | Schottky barrier diode device and manufacturing method thereof |
| DE102009018971A1 (en) * | 2009-04-25 | 2010-11-04 | Secos Halbleitertechnologie Gmbh | Construction of a Schottky diode with improved high-current behavior and method for its production |
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