CN103680442B

CN103680442B - A kind of gating drive circuit, gate driver circuit and display device

Info

Publication number: CN103680442B
Application number: CN201310655614.9A
Authority: CN
Inventors: 郑亮亮; 金婷婷; 徐飞
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2013-12-06
Filing date: 2013-12-06
Publication date: 2015-09-30
Anticipated expiration: 2033-12-06
Also published as: CN103680442A

Abstract

The invention discloses a kind of gating drive circuit, gate driver circuit and display device, the different gating drive circuits treating the circuit of gating can not selected flexibly in the same time in order to provide a kind of.Described gating drive circuit at least comprises: two gatings control electronic circuit and two gating drive sub-circuits, and a gating control electronic circuit is corresponding with a gating drive sub-circuits; The input end that each gating controls electronic circuit is connected with gating signal end respectively, and the first input end of the gating drive sub-circuits that output terminal is corresponding with it is respectively connected; Second input end of each gating drive sub-circuits is all connected with input signal source, and the output terminal of each gating drive sub-circuits is gating end; At synchronization, the first gating signal exported by described gating signal end and the second gating signal are controlled described each gating and control electronic circuit, the gating end only having a gating drive sub-circuits is strobed, and the gating end be strobed exports the signal of described input signal source input.

Description

A kind of gating drive circuit, gate driver circuit and display device

Technical field

The present invention relates to display technique field, particularly relate to a kind of gating drive circuit, gate driver circuit and display device.

Background technology

In recent years, flourish along with semiconductor technologies, portable type electronic product and flat-panel screens product also rise thereupon.TFT (Thin Film Transistor, thin film transistor (TFT)) liquid crystal display, owing to having the advantages such as low, the radiationless line scattering of operating voltage, lightweight and volume be little, becomes the standard output device of various electronic product gradually.Along with various display device, as more and more higher in level of integrated system such as mobile phone, panel computers (PAD), thickness is more and more thinner, CPU (the Central Processing Unit of system, central processing unit) from previous monokaryon be upgraded to present double-core, four cores and eight cores so that more multinuclear product systems ask city successively, system power consumption is more and more higher, the requirement of market to the cruising time of mobile phone and PAD is also more and more higher, thus the power consumption continuing to reduce display device becomes the target that system manufacturer and panel vendor continue to pursue.

The picture element matrix that TFT LCD is generally arranged by horizontal and vertical directions is formed, when TFT LCD shows, by shift register (Shift Register, be called for short SR) produce grid input signal, i.e. output signal G1, the G2.......Gn of driving circuit, each row pixel is scanned successively, as shown in Figure 1 from the first row to last column.The input end of each shift register receives raster data model clock signal C TV, receives gated sweep trigger pip STV at the input end of first order shift register cell SR1.In existing TFT LCD design, sweep-black action can be carried out when TFT LCD is in part display state, namely the grid of TFT LCD can scan from top to bottom line by line, and source drive signal (i.e. data line) remains on low level always, TFT LCD is not charged, thus reduce the power consumption of source driving chip.

But existing circuit design is only reduction of the power consumption of source electrode drive circuit, do not reduce the power consumption of gate driver circuit, no matter gate driver circuit drives the grid line of all row at grid scan line the need of when opening simultaneously, to the selection underaction of driven grid line, cause the overall power consumption of liquid crystal display still very large.

Summary of the invention

Embodiments provide a kind of gating drive circuit, gate driver circuit and display device, the different gating drive circuits treating the circuit of gating can not selected flexibly in the same time in order to provide a kind of.

Described gating drive circuit at least comprises: two gatings control electronic circuit and two gating drive sub-circuits, and a gating control electronic circuit is corresponding with a gating drive sub-circuits;

The input end that each gating controls electronic circuit is connected with gating signal end respectively, and the first input end of the gating drive sub-circuits that output terminal is corresponding with it is respectively connected; Second input end of each gating drive sub-circuits is all connected with input signal source, and the output terminal of each gating drive sub-circuits is gating end;

At synchronization, the first gating signal exported by described gating signal end and the second gating signal are controlled described each gating and control electronic circuit, the gating end only having a gating drive sub-circuits is strobed, and the gating end be strobed exports the signal of described input signal source input.

Preferably, described two gatings control electronic circuit and are respectively the first gating control electronic circuit and the second gating control electronic circuit; Two gating drive sub-circuits are respectively the first gating drive sub-circuits and the second gating drive sub-circuits; Also comprise: the 3rd gating controls electronic circuit and the 3rd gating drive sub-circuits.

Preferably, also comprise: the 4th gating controls electronic circuit and the 4th gating drive sub-circuits.

Preferably, described first gating drive sub-circuits comprises: the first conducting thin film transistor (TFT) and the first shutoff thin film transistor (TFT); The grid of described first conducting thin film transistor (TFT) controls electronic circuit with the grid of the first shutoff thin film transistor (TFT) with described first gating and is connected; The source electrode of the first conducting thin film transistor (TFT) is connected with the source electrode of the first shutoff thin film transistor (TFT), is connected with the first gating end simultaneously; The drain electrode of the first conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the first shutoff thin film transistor (TFT) is connected with low level signal source;

Described second gating drive sub-circuits comprises: the second conducting thin film transistor (TFT) and the second shutoff thin film transistor (TFT); The grid of described second conducting thin film transistor (TFT) controls electronic circuit with the grid of the second shutoff thin film transistor (TFT) with described second gating and is connected; The source electrode of the second conducting thin film transistor (TFT) is connected with the source electrode of the second shutoff thin film transistor (TFT), is connected with the second gating end simultaneously; The drain electrode of the second conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the second shutoff thin film transistor (TFT) is connected with low level signal source;

Described first conducting thin film transistor (TFT) and the second conducting thin film transistor (TFT) are p-type thin film transistor, and described first shutoff thin film transistor (TFT) and the second shutoff thin film transistor (TFT) are n-type thin film transistor.

Preferably, described 3rd gating drive sub-circuits comprises: the 3rd conducting thin film transistor (TFT) and the 3rd shutoff thin film transistor (TFT); The grid of described 3rd conducting thin film transistor (TFT) controls electronic circuit with the grid of the 3rd shutoff thin film transistor (TFT) with described 3rd gating and is connected; The source electrode of the 3rd conducting thin film transistor (TFT) is connected with the source electrode of the 3rd shutoff thin film transistor (TFT), is connected with the first gating end simultaneously; The drain electrode of the 3rd conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the 3rd shutoff thin film transistor (TFT) is connected with low level signal source;

Described 4th gating drive sub-circuits comprises: the 4th conducting thin film transistor (TFT) and the 4th shutoff thin film transistor (TFT); The grid of described 4th conducting thin film transistor (TFT) controls electronic circuit with the grid of the 4th shutoff thin film transistor (TFT) with described 4th gating and is connected; The source electrode of the 4th conducting thin film transistor (TFT) is connected with the source electrode of the 4th shutoff thin film transistor (TFT), is connected with the first gating end simultaneously; The drain electrode of the 4th conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the 4th shutoff thin film transistor (TFT) is connected with low level signal source;

Described 3rd conducting thin film transistor (TFT) and the 4th conducting thin film transistor (TFT) are p-type thin film transistor, and described 3rd shutoff thin film transistor (TFT) and the 4th shutoff thin film transistor (TFT) are n-type thin film transistor.

Preferably, described gating signal end comprises the first gating signal end and the second gating signal end; First gating signal end and the second gating signal end are respectively used to export described first gating signal and the second gating signal.

Preferably, described first gating control electronic circuit comprises: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);

The source electrode of described the first film transistor is connected with the grid of the first shutoff thin film transistor (TFT) with the grid of described first conducting thin film transistor (TFT), and the grid of described the first film transistor is connected with described first gating signal end with drain electrode;

The source electrode of described second thin film transistor (TFT) is connected with the source electrode of described the first film transistor, and the grid of described second thin film transistor (TFT) is connected with described second gating signal end with drain electrode;

The source electrode of described 3rd thin film transistor (TFT) is connected with the drain electrode of the 4th thin film transistor (TFT), and the drain and gate of described 3rd thin film transistor (TFT) is connected with high level signal source;

The grid of described 4th thin film transistor (TFT) is connected with the source electrode of the second thin film transistor (TFT), and the source electrode of described 4th thin film transistor (TFT) is connected with low level signal source;

Described the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT) are n-type thin film transistor.

Preferably, described second gating control electronic circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT);

The source electrode of described 5th thin film transistor (TFT) is connected with the grid of described 7th thin film transistor (TFT), and the grid of described 5th thin film transistor (TFT) is connected with described second gating signal end with drain electrode;

The source electrode of described 6th thin film transistor (TFT) is connected with the drain electrode of the 7th thin film transistor (TFT), and the drain and gate of described 6th thin film transistor (TFT) is connected with high level signal source;

The source electrode of described 7th thin film transistor (TFT) is connected with low level signal source;

The source electrode of described 8th thin film transistor (TFT) is connected with the grid of the second shutoff thin film transistor (TFT) with the grid of described second conducting thin film transistor (TFT), and the grid of described 8th thin film transistor (TFT) is connected with the drain electrode of described 7th thin film transistor (TFT) with drain electrode;

The grid of described 9th thin film transistor (TFT) is connected with described first gating signal end with drain electrode, and the source electrode of described 9th thin film transistor (TFT) is connected with the source electrode of described 8th thin film transistor (TFT);

Described 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT) are n-type thin film transistor.

Preferably, described second gating control electronic circuit comprises: the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT);

The source electrode of described 8th thin film transistor (TFT) is connected with the grid of the second shutoff thin film transistor (TFT) with the grid of described second conducting thin film transistor (TFT), and the grid of described 8th thin film transistor (TFT) is connected with the drain electrode of described 4th thin film transistor (TFT) with drain electrode;

Described the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th film crystal, the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT) are n-type thin film transistor.

Preferably, described 3rd gating control electronic circuit comprises: the tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT), the 13 thin film transistor (TFT) and the 14 thin film transistor (TFT);

The source electrode of described tenth thin film transistor (TFT) is connected with the grid of described 12 thin film transistor (TFT), and the grid of described tenth thin film transistor (TFT) is connected with described first gating signal end with drain electrode;

The source electrode of described 11 thin film transistor (TFT) is connected with the drain electrode of the 12 thin film transistor (TFT), and the source electrode of described 11 thin film transistor (TFT) is connected with high level signal source with grid;

The source electrode of described 12 thin film transistor (TFT) is connected with low level signal source;

The source electrode of described 13 thin film transistor (TFT) is connected with the grid of the 3rd shutoff thin film transistor (TFT) with the grid of described 3rd conducting thin film transistor (TFT), and the grid of described 13 thin film transistor (TFT) is connected with the drain electrode of described 12 thin film transistor (TFT) with drain electrode;

The grid of described 14 switching transistor is connected with described second gating signal end with drain electrode, and the source electrode of described 14 thin film transistor (TFT) is connected with the source electrode of described 13 thin film transistor (TFT);

Described tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT), the 13 thin film transistor (TFT) and the 14 thin film transistor (TFT) are n-type thin film transistor.

Preferably, described 3rd gating control electronic circuit comprises: the 13 thin film transistor (TFT) and the 14 thin film transistor (TFT);

The source electrode of described 13 thin film transistor (TFT) is connected with the grid of the 3rd shutoff thin film transistor (TFT) with the grid of described 3rd conducting thin film transistor (TFT), and the grid of described 13 thin film transistor (TFT) is connected with the drain electrode of described 4th thin film transistor (TFT) with drain electrode;

Described 13 thin film transistor (TFT) and the 14 thin film transistor (TFT) are n-type thin film transistor.

Preferably, described 4th gating control electronic circuit comprises: the 15 thin film transistor (TFT), the 16 thin film transistor (TFT), the 17 thin film transistor (TFT), the 18 thin film transistor (TFT), the 19 thin film transistor (TFT) and the 20 thin film transistor (TFT);

The grid of described 15 thin film transistor (TFT) is connected with high level signal source with drain electrode, and source electrode is connected with the drain electrode of described 16 thin film transistor (TFT);

The grid of described 16 thin film transistor (TFT) is connected with described first gating signal end, and source electrode is connected with low level signal source, drains to be connected with the drain electrode of described 17 thin film transistor (TFT);

The grid of described 17 thin film transistor (TFT) is connected with drain electrode, and source electrode is connected with the grid of the 4th shutoff thin film transistor (TFT) with described 4th conducting thin film transistor (TFT);

The grid of described 18 thin film transistor (TFT) is connected with high level signal source with drain electrode, and source electrode is connected with the drain electrode of described 19 thin film transistor (TFT);

The grid of described 19 thin film transistor (TFT) is connected with described first gating signal end, and source electrode is connected with low level signal source, drains to be connected with the drain electrode of described 20 thin film transistor (TFT);

The grid of described 20 thin film transistor (TFT) is connected with drain electrode, and source electrode is connected with the grid of the 4th shutoff thin film transistor (TFT) with described 4th conducting thin film transistor (TFT);

Described 15 thin film transistor (TFT), the 16 thin film transistor (TFT), the 17 thin film transistor (TFT), the 18 thin film transistor (TFT), the 19 thin film transistor (TFT) and the 20 thin film transistor (TFT) are n-type thin film transistor.

Preferably, the signal of described input signal source input is gated sweep trigger pip or gated sweep termination signal.

The embodiment of the present invention provides a kind of gate driver circuit, comprise the shift register cell of mutual cascade, also comprise above-mentioned gating drive circuit, with multiple, each gating end of described gating drive circuit treats that the input end one_to_one corresponding of the circuit of gating is connected respectively, for for treating the signal that the circuit of gating provides input signal source to input, described in treat that the circuit of gating is described shift register cell.

The embodiment of the present invention also provides a kind of display device, comprises described gate driver circuit.

Embodiments provide a kind of novel gating drive circuit, at least comprise: two gatings control electronic circuit and two gatings control electronic circuits; The input end that each gating controls electronic circuit is connected with gating signal end respectively, and output terminal is connected with the first input end one_to_one corresponding of each gating drive sub-circuits respectively; Second input end of each gating drive sub-circuits is connected with input signal source simultaneously, and the output terminal of each gating drive sub-circuits is gating end; At synchronization, the first gating signal that described gating signal end exports and the second gating signal control electronic circuit by controlling described each gating, make and to have and the gating end only having a gating to control the gating drive sub-circuits that electronic circuit is connected is strobed, the gating end be strobed exports the signal of described input signal source input.In the specific implementation, when time schedule controller T-CON entering part display (Partial Display) pattern, time schedule controller first keeps CS0 and CS1 signal to be low level, notify that source electrode drive circuit carries out sweep-black action simultaneously, the level switching CS0 and CS1 afterwards again shows configuration status to corresponding part, select scanning from a certain shift register cell preset, when some grid line does not need scanning, corresponding shift register cell does not work, and the output terminal output low level of the source electrode drive circuit of correspondence, reduce the power consumption of gate driver circuit and source electrode drive circuit.

Accompanying drawing explanation

The grid electrode drive circuit structure schematic diagram that Fig. 1 provides for prior art;

The gating drive circuit structural representation that Fig. 2 provides for the embodiment of the present invention one;

The gating drive circuit structural representation that Fig. 3 provides for the embodiment of the present invention two;

The gating drive circuit structural representation that Fig. 4 provides for the embodiment of the present invention three;

The gating drive circuit structural representation comprising the concrete structure of each gating drive sub-circuits that Fig. 5 provides for the embodiment of the present invention;

What Fig. 6 provided for the embodiment of the present invention comprises the gating drive circuit structural representation that the first gating controls electronic circuit, the second gating controls electronic circuit, the first gating drive sub-circuits and the second gating drive sub-circuits;

Fig. 7 is the gating drive circuit structural representation after the simplification shown in Fig. 6;

Fig. 8 controls the gating drive circuit structural representation of electronic circuit and the 3rd gating drive sub-circuits for comprising the 3rd gating on the basis of the gating drive circuit structural representation shown in Fig. 7;

Fig. 9 is the gating drive circuit structural representation after the simplification shown in Fig. 8;

Figure 10 controls the gating drive circuit structural representation of electronic circuit and the 4th gating drive sub-circuits for comprising the 4th gating on the basis of the gating drive circuit structural representation shown in Fig. 9;

The grid electrode drive circuit structure schematic diagram that Figure 11 provides for the embodiment of the present invention.

Embodiment

The gating drive circuit that the embodiment of the present invention provides goes for the gate driver circuit in display device.Such as, when the existing full-screen display mode of display device has again subregion to show the display mode of all the other regions of image display blank screen or white screen (namely without the display of any image), when needs show a certain display mode, the basis of the gate driver circuit provided in prior art arranges gating drive circuit, the output terminal of gating drive circuit is connected with the input end of the transposition of partial register cell in gate driver circuit, the input end of the shift register cell of needs is loaded into for control gate scanning trigger pip (i.e. STV signal), the shift register be connected with this shift register cell input end is not triggered, the shift register cell be not triggered stops the grid line of scanning corresponding row, realize display device selectivity when the subregional display mode of display part and close the signal of display black or white portion, thus reduce the power consumption of gate driver circuit, the power consumption of the whole display device of further reduction.

Gating drive circuit, gate driver circuit and the display device that the embodiment of the present invention provides is illustrated below with reference to accompanying drawing.

Embodiment one:

See Fig. 2, the gating drive circuit that the embodiment of the present invention provides comprises:

First gating controls electronic circuit 11, second gating and controls electronic circuit 12, first gating drive sub-circuits 21 and the second gating drive sub-circuits 22;

It is corresponding with the first gating drive sub-circuits 21 that first gating controls electronic circuit 11;

It is corresponding with the second gating drive sub-circuits 22 that second gating controls electronic circuit 12;

The output terminal of the first gating drive sub-circuits 21 is the first gating end;

The output terminal of the second gating drive sub-circuits 22 is the second gating end;

Particularly, first gating controls one end (A1) of electronic circuit 11 and is connected with the first end (B1) of the first gating drive sub-circuits 21, and the other end (A2) that the first gating controls electronic circuit 11 is connected with gating signal end (CS0 with CS1); This first gating controls electronic circuit 11 and controls gating drive sub-circuits 21 conducting or shutoff for the gating signal exported according to gating signal end synchronization;

Second end (B2) of the first gating drive sub-circuits 21 is connected with input signal source (Input), 3rd end (B3) is the first gating end (Output0), and this first gating end Output0 is used for treating that the circuit of gating is connected with first; When the first drive sub-circuits 21 conducting (when the first gating end Output0 is strobed), the signal that input signal source Input inputs exports to from the first gating end Output0 the circuit that described first treats gating;

Second gating controls one end (C1) of electronic circuit 12 and is connected with the first end (D1) of the second gating drive sub-circuits 22, and the other end (C2) that the second gating controls electronic circuit 12 is connected with gating signal end (CS0 with CS1); This second gating controls electronic circuit 12 for the first gating signal of exporting according to gating signal end synchronization and control gating drive sub-circuits 22 conducting of the second gating signal or shutoff;

Second end (D2) of the second gating drive sub-circuits 22 is connected with input signal source (Input), 3rd end (D3) is the second gating end (Output1), and this second gating end Output1 is used for treating that the circuit of gating is connected with second; When the second drive sub-circuits 22 conducting (when the second gating end Output1 is strobed), the signal that input signal source Input inputs exports to from the second gating end Output1 the circuit that described second treats gating.

The gating drive circuit that the embodiment of the present invention one provides, has two gating ends, and each gating end connects the circuit that is treated gating, and gating drive circuit selects one of them to treat the circuit working of gating at synchronization, and another treats that the circuit of gating quits work; The circuit working treating gating of concrete selection, different because of the difference of the gating signal of gating signal end output.Can realize the circuit working treating gating controlling flexibly to preset, other treat that the circuit of gating quits work, and reduce the power consumption treating the circuit of gating.

Embodiment two:

On the basis of the gating drive circuit shown in Fig. 2, see Fig. 3, gating drive circuit comprises further:

3rd gating controls electronic circuit 13 and the 3rd gating drive sub-circuits 23;

3rd gating controls one end (E1) of electronic circuit 13 and is connected with the first end (F1) of the 3rd gating drive sub-circuits 23, and the other end (E2) that the 3rd gating controls electronic circuit 13 is connected with gating signal end (CS0 with CS1); 3rd gating controls electronic circuit 13 and controls gating drive sub-circuits 23 conducting or shutoff for the gating signal exported according to gating signal end synchronization;

Second end (F2) of the 3rd gating drive sub-circuits 23 is connected with input signal source (Input), 3rd end (F3) is the 3rd gating end (Output2), and the 3rd gating end Output2 is used for treating that the circuit of gating is connected with the 3rd; When the 3rd drive sub-circuits 23 conducting (when the 3rd gating end Output2 is strobed), the signal that input signal source Input inputs exports to from the 3rd gating end Output2 the circuit that the described 3rd treats gating.

Embodiment three:

On the basis of the gating drive circuit shown in Fig. 3, see Fig. 4, comprise further:

4th gating controls electronic circuit 14 and the 4th gating drive sub-circuits 24;

4th gating controls one end (G1) of electronic circuit 14 and is connected with the first end (H1) of the 4th gating drive sub-circuits 24, and the other end (G2) that the 4th gating controls electronic circuit 14 is connected with gating signal end (CS0 with CS1); 4th gating controls electronic circuit 14 and controls gating drive sub-circuits 24 conducting or shutoff for the gating signal exported according to gating signal end synchronization;

Second end (H2) of the 4th gating drive sub-circuits 24 is connected with input signal source (Input), 3rd end (H3) is the 4th gating end (Output3), and the 4th gating end Output3 is used for treating that the circuit of gating is connected with the 4th; When 24 conducting of four-wheel drive electronic circuit (when the 4th gating end Output3 is strobed), the signal that input signal source Input inputs exports to from the 4th gating end Output3 the circuit that the described 4th treats gating.

Preferably, the gating drive circuit shown in Fig. 2 ~ Fig. 4, gating signal end comprises the first gating signal end and the second gating signal end;

First gating signal end and the second gating signal end are respectively used to output first gating signal CS0 and the second gating signal CS1;

Each module concrete structure in Fig. 2 ~ Fig. 4 and function is specifically introduced below with reference to gating signal end.

Gating drive circuit shown in arbitrary see Fig. 5, Fig. 2 ~ Fig. 4, the first gating drive sub-circuits 21 comprises:

First conducting thin film transistor (TFT) P1 and the first shutoff thin film transistor (TFT) T1;

First conducting all controls electronic circuit 11 with the first gating with the grid of thin film transistor (TFT) P1 with the grid of the first shutoff thin film transistor (TFT) T1 and is connected; The first conducting source electrode of thin film transistor (TFT) P1 is connected with the source electrode of the first shutoff thin film transistor (TFT) T1; The first conducting drain electrode of thin film transistor (TFT) P1 is connected with input signal source Input; First turns off the drain electrode and low level signal source V of using thin film transistor (TFT) T1 _gLbe connected;

Second gating drive sub-circuits 22 comprises:

Second conducting thin film transistor (TFT) P2 and the second shutoff thin film transistor (TFT) T2; Second conducting controls electronic circuit 12 with the grid of the second shutoff thin film transistor (TFT) T2 with the second gating with the grid of thin film transistor (TFT) P2 and is connected; The second conducting source electrode of thin film transistor (TFT) P2 is connected with the source electrode of the second shutoff thin film transistor (TFT) T2; The second conducting drain electrode of thin film transistor (TFT) P2 is connected with input signal source Input; Second turns off the drain electrode and low level signal source V of using thin film transistor (TFT) T2 _gLbe connected;

Wherein, the first conducting thin film transistor (TFT) P1 and the second conducting thin film transistor (TFT) P2 is p-type thin film transistor, and the first shutoff thin film transistor (TFT) T1 and the second shutoff thin film transistor (TFT) T2 is n-type thin film transistor.

The conducting under low level voltage effect of p-type thin film transistor, turns off under high level voltage effect; N-type thin film transistor turns off under low level voltage effect, conducting under high level voltage effect.

Gate driver circuit shown in composition graphs 1 illustrates the principle of work of the first gating drive sub-circuits 21:

When the current potential of the grid of the first conducting thin film transistor (TFT) P1 and the grid of the first shutoff thin film transistor (TFT) T1 is low level, first conducting thin film transistor (TFT) P1 conducting, first turns off with thin film transistor (TFT) T1 shutoff, the the first gating end Output0 be connected with the first conducting thin film transistor (TFT) P1 is strobed, and the shift register cell be attached thereto starts to scan corresponding line grid line;

When the current potential of the grid of the first conducting thin film transistor (TFT) P1 and the grid of the first shutoff thin film transistor (TFT) T1 is high level, first conducting thin film transistor (TFT) P1 turns off, first turns off with thin film transistor (TFT) T1 conducting, the current potential of the first gating end Output0 is pulled low to electronegative potential, Output0 is not strobed, the shift register cell be attached thereto does not scan corresponding line grid line, and namely this shift register cell does not work.

The first gating control electronic circuit, the first gating signal and the second gating signal that the current potential height of the grid of the first conducting thin film transistor (TFT) P1 and the grid of the first shutoff thin film transistor (TFT) T1 is attached thereto controls.

The principle of work of the second gating drive sub-circuits 22 and principle of work of the first gating drive sub-circuits 21 is similar repeats no more here.

The 3rd gating drive sub-circuits 23 shown in Fig. 3 and Fig. 4, and the structure of the 4th gating drive sub-circuits 24 shown in Fig. 4 and the similar of the first gating drive sub-circuits 21.

See Fig. 5, the 3rd gating drive sub-circuits 23 comprises:

3rd conducting thin film transistor (TFT) P3 and the 3rd shutoff thin film transistor (TFT) T3;

3rd conducting all controls electronic circuit 13 with the 3rd gating with the grid of thin film transistor (TFT) P3 with the grid of the 3rd shutoff thin film transistor (TFT) T3 and is connected; The 3rd conducting source electrode of thin film transistor (TFT) P3 is connected with the source electrode of the 3rd shutoff thin film transistor (TFT) T3; The 3rd conducting drain electrode of thin film transistor (TFT) P3 is connected with input signal source Input; 3rd turns off the drain electrode and low level signal source V of using thin film transistor (TFT) T3 _gL(i.e. corresponding negative voltage input) is connected;

4th gating drive sub-circuits 24 comprises:

4th conducting thin film transistor (TFT) P4 and the 4th shutoff thin film transistor (TFT) T4;

4th conducting all controls electronic circuit 14 with the 4th gating with the grid of thin film transistor (TFT) P4 with the grid of the 4th shutoff thin film transistor (TFT) T4 and is connected; The 4th conducting source electrode of thin film transistor (TFT) P4 is connected with the source electrode of the 4th shutoff thin film transistor (TFT) T4; The 4th conducting drain electrode of thin film transistor (TFT) P4 is connected with input signal source Input; 4th turns off the drain electrode and low level signal source V of using thin film transistor (TFT) T4 _gLbe connected;

The principle of work of the 3rd gating drive sub-circuits 23 and the 4th gating drive sub-circuits 24 and the principle of work of the first gating drive sub-circuits 21 similar, repeat no more here.

Gating drive circuit shown in Fig. 5, the first gating signal that first gating signal end and the second gating signal end CS1 synchronization export and the second gating signal ensure in the first gating end Output0, the second gating end Output1, the 3rd gating end Output2 and the 4th gating end Output3, only have the current potential of a gating end to be high-level strobe state, the current potential of all the other gating ends is that low level is not strobed state.

The signal exported below with reference to the above-mentioned gating signal end each gating specifically introduced in Fig. 2 ~ Fig. 4 controls the principle of work of the structure of electronic circuit.

Preferably, control electronic circuit 11 see the first gating in the arbitrary gating drive circuit shown in Fig. 6, Fig. 2 to Fig. 4 to comprise:

The first film transistor M1, the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4;

The source electrode of the first film transistor M1 is connected with the grid of the first shutoff thin film transistor (TFT) T1 with the grid of the first conducting thin film transistor (TFT) P1, and the grid of the first film transistor M1 is connected with the first gating signal end with drain electrode;

The source electrode of the second thin film transistor (TFT) M2 is connected with the source electrode of the first film transistor M1, and the grid of the second thin film transistor (TFT) M2 is connected with the second gating signal end CS1 with drain electrode;

The source electrode of the 3rd thin film transistor (TFT) M3 is connected with the drain electrode of the 4th thin film transistor (TFT) M4, the drain and gate of the 3rd thin film transistor (TFT) M3 and high level signal source V _gH(corresponding positive voltage input) is connected;

The grid of the 4th thin film transistor (TFT) M4 is connected with the source electrode of the second thin film transistor (TFT) M2, the source electrode of the 4th thin film transistor (TFT) M4 and low level signal source V _gLbe connected;

The first film transistor M1, the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4 are n-type thin film transistor.

Preferably, control electronic circuit 12 see the second gating in the arbitrary gating drive circuit shown in Fig. 6, Fig. 2 to Fig. 4 to comprise:

5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8 and the 9th thin film transistor (TFT) M9;

The source electrode of the 5th thin film transistor (TFT) M5 is connected with the grid of the 7th thin film transistor (TFT) M7, and the grid of the 5th thin film transistor (TFT) M5 is connected with the second gating signal end CS1 with drain electrode;

The source electrode of the 6th thin film transistor (TFT) M6 is connected with the drain electrode of the 7th thin film transistor (TFT) M7, the drain and gate of the 6th thin film transistor (TFT) M6 and high level signal source V _gHbe connected;

The source electrode of the 7th thin film transistor (TFT) M7 and low level signal source V _gLbe connected.

The source electrode of the 8th thin film transistor (TFT) M8 is connected with the grid of the second shutoff thin film transistor (TFT) T2 with the grid of the second conducting thin film transistor (TFT) P2, and the grid of the 8th thin film transistor (TFT) M8 is connected with the drain electrode of the 7th thin film transistor (TFT) M7 with drain electrode;

The grid of the 9th thin film transistor (TFT) M9 is connected with the first gating signal end with drain electrode, and the source electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the 8th thin film transistor (TFT) M8;

5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8 and the 9th thin film transistor (TFT) M9 are n-type thin film transistor.

Preferably, in order to simplify circuit structure, see Fig. 7, the second gating controls electronic circuit 12 and only comprises: the 8th thin film transistor (TFT) M8 and the 9th switching transistor M9;

The source electrode of the 8th thin film transistor (TFT) M8 is connected with the grid of the second shutoff thin film transistor (TFT) T2 with the grid of the second conducting thin film transistor (TFT) P2, and the grid of the 8th thin film transistor (TFT) M8 is connected with the drain electrode of the 4th thin film transistor (TFT) M4 with drain electrode;

Be connected with the first gating signal end source electrode of the 9th thin film transistor (TFT) M9 of the grid of the 9th thin film transistor (TFT) M9 and drain electrode is connected with the source electrode of the 8th thin film transistor (TFT) M8;

To compare the circuit structure shown in Fig. 6, the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6 and the 7th thin film transistor (TFT) M7 that second gating controls in electronic circuit save, and the drain and gate of the 8th thin film transistor (TFT) M8 is connected with the drain electrode of the 4th thin film transistor (TFT) M4.

Preferably, control electronic circuit 13 see the 3rd gating in the arbitrary gating drive circuit shown in Fig. 8, Fig. 3 and Fig. 4 to comprise:

Tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11, the 12 thin film transistor (TFT) M12, the 13 thin film transistor (TFT) M13 and the 14 thin film transistor (TFT) M14;

The source electrode of the tenth thin film transistor (TFT) M10 is connected with the grid of the 12 thin film transistor (TFT) M12, and the grid of the tenth thin film transistor (TFT) M10 is connected with the first gating signal end with drain electrode;

The source electrode of the 11 thin film transistor (TFT) M11 is connected with the drain electrode of the 12 thin film transistor (TFT) M12, the source electrode of the 11 thin film transistor (TFT) M11 and grid and high level signal source V _gHbe connected;

The source electrode of the 12 thin film transistor (TFT) M12 and low level signal source V _gLbe connected.

The source electrode of the 13 thin film transistor (TFT) M13 is connected with the grid of the 3rd shutoff thin film transistor (TFT) T3 with the grid of the 3rd conducting thin film transistor (TFT) P3, and the grid of the 13 thin film transistor (TFT) M13 is connected with the drain electrode of the 12 thin film transistor (TFT) M12 with drain electrode;

The grid of the 14 switching transistor M14 is connected with the second gating signal end CS1 with drain electrode, and the source electrode of the 14 thin film transistor (TFT) M14 is connected with the source electrode of the 13 thin film transistor (TFT) M13;

Tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11, the 12 thin film transistor (TFT) M12, the 13 thin film transistor (TFT) M13 and the 14 thin film transistor (TFT) M14 are n-type thin film transistor.

Preferably, in order to simplify circuit structure, comprise see controlling electronic circuit with the 9, three gating: the 13 thin film transistor (TFT) M13 and the 14 switching transistor M14;

The source electrode of the 13 thin film transistor (TFT) M13 is connected with the grid of the 3rd shutoff thin film transistor (TFT) T3 with the grid of the 3rd conducting thin film transistor (TFT) P3, and the grid of the 13 thin film transistor (TFT) M13 is connected with the drain electrode of the 4th thin film transistor (TFT) M4 with drain electrode;

Circuit structure shown in Fig. 9 saves the tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11 and the 12 thin film transistor (TFT) M12 on the basis of the circuit structure shown in Fig. 8.The drain electrode of the 13 thin film transistor (TFT) M13 is connected with the drain electrode of the 4th thin film transistor (TFT) M4.

Preferably, control electronic circuit 14 see the 4th gating in the gating drive circuit shown in Figure 10, Fig. 4 to comprise:

15 thin film transistor (TFT) M15, the 16 thin film transistor (TFT) M16, the 17 thin film transistor (TFT) M17, the 18 thin film transistor (TFT) M18, the 19 thin film transistor (TFT) M19 and the 20 thin film transistor (TFT) M20;

The source electrode of the 15 thin film transistor (TFT) M15 is connected with the drain electrode of the 16 thin film transistor (TFT) M16, source electrode and grid and high level signal source V _gHbe connected;

The source electrode of the 16 thin film transistor (TFT) M16 and low level signal source V _gLbe connected;

The source electrode of the 17 thin film transistor (TFT) M17 is connected with the grid of the 4th shutoff thin film transistor (TFT) T4 with the grid of the 4th conducting thin film transistor (TFT) P4, and grid is connected with the drain electrode of the 16 thin film transistor (TFT) M16 with drain electrode;

The source electrode of the 18 thin film transistor (TFT) M18 is connected with the drain electrode of the 19 thin film transistor (TFT) M19, source electrode and grid and high level signal source V _gHbe connected;

The source electrode of the 19 thin film transistor (TFT) M19 and low level signal source V _gLbe connected;

The source electrode of the 20 thin film transistor (TFT) M20 is connected with the grid of the 4th shutoff thin film transistor (TFT) T4 with the grid of the 4th conducting thin film transistor (TFT) P4, and grid is connected with the drain electrode of the 19 thin film transistor (TFT) M19 with drain electrode.

15 thin film transistor (TFT) M15, the 16 thin film transistor (TFT) M16, the 17 thin film transistor (TFT) M17, the 18 thin film transistor (TFT) M18, the 19 thin film transistor (TFT) M19 and the 20 thin film transistor (TFT) M20 are n-type thin film transistor.

Preferably, the signal that input signal source of the present invention (Input) inputs can be gated sweep trigger pip STV or gated sweep termination signal.

Gating drive circuit is as shown in Figure 10 known, and the embodiment of the present invention adopts 22 thin film transistor (TFT)s to achieve in the same time can not the different object treating gating circuit of gating four.

Level state below with reference to gating signal end illustrates the arbitrary principle be strobed of four gating ends in gating drive circuit.

The level state of the first gating signal end and the second gating signal end has four kinds.

State one: the first gating signal end is low level state, and the second gating signal end is low level state;

State two: the first gating signal end is low level state, and the second gating signal end is high level state;

State three: the first gating signal end is high level state, and the second gating signal end is low level state;

State four: the first gating signal end is high level state, and the second gating signal end is high level state;

If low level state of the present invention represents with " 0 ", high level state represents with " 1 ".

The level state of the first gating signal end and the second gating signal end respectively is (0,0), (0,1), (1,0), (1,1).

When the first gating signal end and the second gating signal end level state are at a time any state in above-mentioned state one to state four, a gating end corresponding in first gating end Output0, the second gating end Output1, the 3rd gating end Output2 and the 4th gating end Output3 is high level state and is strobed, and all the other are low level state and are not strobed.

The gating drive circuit that the embodiment of the present invention provides is equivalent to a single pole multiple throw;

As CS0=CS1=0, the first gating end Output0 is only had to be strobed;

Work as CS0=0, during CS1=1, only have the second gating end Output1 to be strobed;

Work as CS0=1, during CS1=0, only have the 3rd gating end Output2 to be strobed;

Work as CS0=1, during CS1=1, only have the 4th gating end Output3 to be strobed.

The principle that each gating end is strobed specifically is introduced below with reference to accompanying drawing 10.

If the signal that the input signal source Input in gating drive circuit outputs to each gating drive sub-circuits is high level signal.

As CS0=CS1=0, namely the current potential of the first gating signal end and the second gating signal end CS1 is low level;

For the first gating end Output0:

As long as the first film transistor M1 be connected with the grid of the first shutoff thin film transistor (TFT) T1 with the first conducting thin film transistor (TFT) P1 and second one of them conducting of thin film transistor (TFT) M2, then the level of the first gating end Output0 is dragged down;

The first film transistor M1 and the second thin film transistor (TFT) M2 turns off, the current potential of the grid of the first conducting thin film transistor (TFT) P1 and the first shutoff thin film transistor (TFT) T1 is low level, first conducting thin film transistor (TFT) P1 is p-type thin film transistor, grid is thin film transistor (TFT) conducting under low level state, and the first gating end Output0 is strobed; First shutoff thin film transistor (TFT) T1 is n-type thin film transistor, and when grid is under low level state, thin film transistor (TFT) turns off.

For the second gating end Output1:

As long as the 8th thin film transistor (TFT) M8 be connected with the grid of the second shutoff thin film transistor (TFT) T2 with the second conducting thin film transistor (TFT) P2 and the 9th one of them conducting of thin film transistor (TFT) M9, then the level of the second gating end Output1 is dragged down;

3rd thin film transistor (TFT) M3 is at high level signal source V _gHeffect under conducting, and output high level signal, the 8th thin film transistor (TFT) M8 conducting be connected with the source electrode of the 3rd thin film transistor (TFT) M3,8th thin film transistor (TFT) M8 exports high level signal simultaneously, the current potential of the grid of the second conducting thin film transistor (TFT) P2 be connected with the source electrode of the 8th thin film transistor (TFT) M8 and the second shutoff thin film transistor (TFT) T2 is high level, second conducting thin film transistor (TFT) P2 turns off, second turns off with thin film transistor (TFT) T2 conducting, and second turns off the drain electrode and low level signal source V of using thin film transistor (TFT) T2 _gLbe connected, the source electrode (i.e. the second gating end Output1) of the second shutoff thin film transistor (TFT) T2 is pulled low to low level, and the second gating end Output1 is not strobed.

For the 3rd gating end Output2:

As long as the 13 thin film transistor (TFT) M13 be connected with the grid of the 3rd shutoff thin film transistor (TFT) T3 with the 3rd conducting thin film transistor (TFT) P3 and the 14 one of them conducting of thin film transistor (TFT) M14, then the level of the 3rd gating end Output2 is dragged down;

The grid of the 13 thin film transistor (TFT) M13 is connected with the source electrode of the 3rd thin film transistor (TFT) M3 with drain electrode, and the 3rd thin film transistor (TFT) M3 is at high level signal source V _gHeffect under conducting, and output high level signal, 13 thin film transistor (TFT) M13 high level signal used lower conducting and export high level signal, 3rd shutoff thin film transistor (TFT) T3 conducting under the effect of high level signal, the source electrode (i.e. the 3rd gating end Output2) of the 3rd shutoff thin film transistor (TFT) T3 is pulled low to low level, and the 3rd gating end Output2 is not strobed.

For the 4th gating end Output3:

As long as the 17 thin film transistor (TFT) M17 be connected with the grid of the 4th shutoff thin film transistor (TFT) T4 with the 4th conducting thin film transistor (TFT) P4 and the 20 one of them conducting of thin film transistor (TFT) M20, then the level of the 4th gating end Output3 is dragged down;

The 16 thin film transistor (TFT) M16 be connected with the second gating signal end with the first gating signal end respectively and the 19 thin film transistor (TFT) M19 turns off under low level signal effect, with high level signal source V _gHthe 15 thin film transistor (TFT) M15 be connected and the 18 thin film transistor (TFT) M18 conducting under high level effect, export high level signal simultaneously, the 17 thin film transistor (TFT) M17 be connected with the source electrode of the 18 thin film transistor (TFT) M18 with the 15 thin film transistor (TFT) M15 respectively and the 20 thin film transistor (TFT) M20 conducting and export high level signal under the effect of high level signal, the 4th shutoff thin film transistor (TFT) T4 conducting under the effect of high level signal be connected with the source electrode of the 20 thin film transistor (TFT) M20 with the 17 thin film transistor (TFT) M17, the source electrode (i.e. the 4th gating end Output3) of the 4th shutoff thin film transistor (TFT) T4 is pulled low to low level, 4th gating end Output3 is not strobed.

Work as CS0=0, during CS1=1, i.e. the first gating signal end output low level signal, the second gating signal end CS1 exports high level signal;

For the first gating end Output0:

The the second thin film transistor (TFT) M2 conducting be simultaneously connected with the grid of the first shutoff thin film transistor (TFT) T1 with the second gating signal end CS1 and the first conducting thin film transistor (TFT) P1, export high level signal, this high level signal makes the first shutoff thin film transistor (TFT) T1 be dragged down by the level of the first gating end Output0, and the first gating end Output0 is not strobed.

For the second gating end Output1:

8th thin film transistor (TFT) M8 is connected with the grid of the second shutoff thin film transistor (TFT) T2 with the second conducting thin film transistor (TFT) P2 with the source electrode of the 9th thin film transistor (TFT) M9, and the grid of the 9th thin film transistor (TFT) M9 is connected with the first gating signal end, is in off state; The grid of the 8th thin film transistor (TFT) M8 is connected with the drain electrode of the 4th thin film transistor (TFT) M4, because the grid of the 4th thin film transistor (TFT) M4 is connected with the second gating signal end CS1,4th thin film transistor (TFT) M4 conducting, the drain electrode of the 4th thin film transistor (TFT) M4 is pulled low to low level, and the 8th thin film transistor (TFT) M8 turns off; Second conducting thin film transistor (TFT) P2 conducting under low level effect, the second gating end Output1 gating.

For the 3rd gating end Output2:

The grid of the 14 thin film transistor (TFT) M14 is connected with the second gating signal end CS1 with drain electrode, and source electrode is connected with the grid of the 3rd shutoff thin film transistor (TFT) T3 with the 3rd conducting thin film transistor (TFT) P3; 14 thin film transistor (TFT) M14 conducting under high level signal effect exports high level signal simultaneously, 3rd shutoff thin film transistor (TFT) T3 conducting under high level signal effect, the source electrode (i.e. the 3rd gating end Output2) of the 3rd shutoff thin film transistor (TFT) T3 is pulled low to low level, and the 3rd gating end Output2 is not strobed.

For the 4th gating end Output3:

The 16 thin film transistor (TFT) M16 be connected with the first gating signal end turns off under low level signal effect, with high level signal source V _gHthe 15 thin film transistor (TFT) M15 conducting under high level effect be connected, export high level signal simultaneously, the 17 thin film transistor (TFT) M17 be connected with the source electrode of the 15 thin film transistor (TFT) M15 conducting and export high level signal under the effect of high level signal, the 4th shutoff thin film transistor (TFT) T4 conducting under the effect of high level signal be connected with the source electrode of the 17 thin film transistor (TFT) M17, the source electrode (i.e. the 4th gating end Output3) of the 4th shutoff thin film transistor (TFT) T4 is pulled low to low level, and the 4th gating end Output3 is not strobed.

Work as CS0=1, during CS1=0, namely the first gating signal end exports high level signal, the second gating signal end CS1 output low level signal;

For the first gating end Output0:

The first film transistor M1 conducting under high level signal effect be connected with the first gating signal end, export high level signal, this high level signal makes the first shutoff thin film transistor (TFT) T1 be dragged down by the level of the first gating end Output0, and the first gating end Output0 is not strobed.

For the second gating end Output1:

The 9th thin film transistor (TFT) M9 conducting under high level signal effect be connected with the first gating signal end, export high level signal, this high level signal makes the second shutoff thin film transistor (TFT) T2 be dragged down by the level of the second gating end Output1, and the second gating end Output1 is not strobed.

For the 3rd gating end Output2:

The 14 thin film transistor (TFT) M14 be connected with the second gating signal end CS1 turns off under low level signal effect;

The 4th thin film transistor (TFT) M4 be connected with the grid of the 13 thin film transistor (TFT) M13, its grid is connected with the first gating signal end, conducting under high level signal effect, and its drain electrode is by low level signal source V _gLbe pulled low to low level, the grid of the 13 thin film transistor (TFT) M13 turns off under the effect of low level signal;

13 thin film transistor (TFT) M13 and the 14 thin film transistor (TFT) M14 turns off simultaneously, the 3rd conducting thin film transistor (TFT) P3 conducting under low level effect, the 3rd gating end Output2 gating.

For the 4th gating end Output3:

The 19 thin film transistor (TFT) M19 be connected with the second gating signal end CS1 turns off under low level signal effect, with high level signal source V _gHthe 18 thin film transistor (TFT) M18 conducting under high level effect be connected, export high level signal simultaneously, the 20 thin film transistor (TFT) M20 be connected with the source electrode of the 18 thin film transistor (TFT) M18 conducting and export high level signal under the effect of high level signal, the 4th shutoff thin film transistor (TFT) T4 conducting under the effect of high level signal be connected with the source electrode of the 20 thin film transistor (TFT) M20, the source electrode (i.e. the 4th gating end Output3) of the 4th shutoff thin film transistor (TFT) T4 is pulled low to low level, and the 4th gating end Output3 is not strobed.

Work as CS0=1, during CS1=1, namely the first gating signal end exports high level signal, and the second gating signal end CS1 exports high level signal;

For the first gating end Output0:

For the second gating end Output1:

For the 3rd gating end Output2:

The 14 thin film transistor (TFT) M14 be connected with the second gating signal end CS1 conducting and export high level signal under high level signal effect; The 3rd shutoff thin film transistor (TFT) T3 conducting under high level effect be connected with the source electrode of the 14 thin film transistor (TFT) M14, the 3rd gating end Output2 is not strobed.

For the 4th gating end Output3:

The 16 thin film transistor (TFT) M16 be connected with the second gating signal end CS1 with the first gating signal end and the 19 thin film transistor (TFT) M19 conducting under high level effect, the drain electrode of the 16 thin film transistor (TFT) M16 and the 19 thin film transistor (TFT) M19 is by low level signal source V _gLbe pulled low to low level, the 17 thin film transistor (TFT) M17 be connected with the drain electrode of the 19 thin film transistor (TFT) M19 with the 16 thin film transistor (TFT) M16 respectively and the 20 thin film transistor (TFT) M20 all turns off, 4th conducting thin film transistor (TFT) P4 conducting under the effect of low level signal, the 4th gating end Output3 gating.

The gating drive circuit that all embodiments of the present invention provide, can be, but not limited to be applicable to gate driver circuit.

The embodiment of the present invention also provides a kind of gate driver circuit, comprise the shift register cell of mutual cascade, also comprise at least one gating drive circuit, with multiple, each gating end of described gating drive circuit treats that the input end one_to_one corresponding of the circuit of gating is connected respectively, described in treat that the circuit of gating is described shift register cell; The gating drive circuit that described gating drive circuit provides for the above-mentioned any embodiment of the present invention.

See Figure 11, the embodiment of the present invention also provides a kind of gate driver circuit, comprising:

The shift register cell of several mutual cascades, be respectively SR1 ..., SRa, SRa+1 ..., SRb, SRb+1 ..., SRc, SRc+1 ..., SRd, SRd+1 ... SRn; The output terminal of each shift register cell is connected with corresponding grid line, as G1 ..., Ga, Ga+1 ..., Gb, Gb+1 ..., Gc, Gc+1 ..., Gd, Gd+1 ... Gn;

First gating drive circuit 20 and the second gating drive circuit 30;

First gating drive circuit 20 is for selecting initial sweep capable, and the second gating drive circuit 30 terminates scan line for selecting;

The first input end (Input) of the first gating drive circuit 20 is connected with gated sweep trigger pip STV, and the second input end is connected with the second gating signal CS1 with the first gating signal CS0 respectively with the 3rd input end;

First gating drive circuit 20 comprises at least two gating ends (Figure 11 shows that four gating ends Output0, Output1 and Output2), each gating end with treat that the shift register cell of gating is connected;

First gating end Output0 is connected with the input end of shift register cell SR1;

Second gating end Output1 is connected with the input end of shift register cell SRa+1;

3rd gating end Output2 is connected with the input end of shift register cell SRb+1.

Wherein, the first gating drive circuit 20 and the second gating drive circuit 30 are one of at least gating drive circuit that the above embodiment of the present invention provides.

It should be noted that, any one the gating end in gating drive circuit all can be connected with the input end of shift register cell SR1; Be not limited to the first gating end Output0 be connected with the input end of shift register cell SR1.

Illustrate for the gating drive circuit that the first gating drive circuit 20 provides for the above embodiment of the present invention.Now, the signal that the input signal source Input in gating drive circuit outputs to each gating drive sub-circuits is gated sweep trigger pip STV.

When STV is high level, by switching level state gating shift register cell SR1 or the shift register cell SRa+1 or shift register cell SRb+1 of the first gating signal CS0 and the second gating signal CS1; Such as when shift register cell SR1 is strobed, the input end of gated sweep trigger pip STV input shift register cell S R1, gate driver circuit scans successively from top to bottom from shift register cell SR1; When shift register cell SRb+1 is strobed, the input end of gated sweep trigger pip STV input shift register cell S R b+1, gate driver circuit scans from shift register cell b+1, shift register cell SR1 to shift register cell SRb by driving scanning, does not reduce the power consumption of gate driver circuit.

When the gating drive circuit that the embodiment of the present invention provides is for the second gating drive circuit 30, the signal that the input signal source Input in gating drive circuit outputs to each gating drive sub-circuits is the signal being provided for gated sweep termination.

Second gating drive circuit 30 also can be by multiple single-pole single-throw switch (SPST), such as comprise the first single-pole single-throw switch (SPST) SW1 and the second single-pole single-throw switch (SPST) SW2, first single-pole single-throw switch (SPST) SW1 is connected with the second gating signal CS1 with the first gating signal CS0 with the second single-pole single-throw switch (SPST) SW2, under the different conditions of the first gating signal CS0 and the second gating signal CS1, switch the opening and closing of the first single-pole single-throw switch (SPST) SW1 and the second single-pole single-throw switch (SPST) SW2; The output terminal of the second gating drive circuit 30 is connected with shift register cell SRd+1 with shift register cell SRc+1 respectively, when shift register cell SRc+1 and shift register cell SRd+1 is arbitrary be strobed time, to this shift register cell be strobed terminate scanning.

Preferably, OR circuit (as the OR circuit Or Gate1 in Figure 11 and Or Gate2) can also be connected at the input end of shift register cell and the output terminal of corresponding first gating drive circuit 20.

The embodiment of the present invention also provides a kind of display device, comprises above-mentioned gate driver circuit.This display device can be the display device such as liquid crystal panel, liquid crystal display, LCD TV, ORGANIC ELECTROLUMINESCENCE DISPLAYS oled panel, OLED display, OLED TV or Electronic Paper.

Embodiments provide a kind of novel gating drive circuit, minimumly 22 thin film transistor (TFT)s can be adopted to realize the gating of different output terminal.Gate driver circuit arranges described gating drive circuit, in the specific implementation, when time schedule controller T-CON entering part display (Partial Display) pattern, time schedule controller first keeps CS0 and CS1 signal to be low level, notify that source electrode drive circuit carries out sweep-black action simultaneously, the level switching CS0 and CS1 afterwards again shows configuration status to corresponding part, select scanning from a certain shift register cell preset, when some grid line does not need scanning, corresponding shift register cell does not work, and the output terminal output low level of the source electrode drive circuit of correspondence, reduce the power consumption of gate driver circuit and source electrode drive circuit.

Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims

1. a gating drive circuit, is characterized in that, at least comprises:

Two gatings control electronic circuit and two gating drive sub-circuits, and a gating control electronic circuit is corresponding with a gating drive sub-circuits;

The input end that each gating controls electronic circuit is connected with gating signal end respectively, and the first input end of the gating drive sub-circuits that output terminal is corresponding with it is respectively connected;

Second input end of each gating drive sub-circuits is all connected with input signal source, and the output terminal of each gating drive sub-circuits is gating end;

2. gating drive circuit according to claim 1, is characterized in that, described two gatings control electronic circuit and are respectively the first gating control electronic circuit and the second gating control electronic circuit; Two gating drive sub-circuits are respectively the first gating drive sub-circuits and the second gating drive sub-circuits;

Also comprise:

3rd gating controls electronic circuit and the 3rd gating drive sub-circuits.

3. gating drive circuit according to claim 2, is characterized in that, also comprises:

4th gating controls electronic circuit and the 4th gating drive sub-circuits.

4. gating drive circuit according to claim 3, is characterized in that, described first gating drive sub-circuits comprises:

First conducting thin film transistor (TFT) and the first shutoff thin film transistor (TFT); The grid of described first conducting thin film transistor (TFT) controls electronic circuit with the grid of the first shutoff thin film transistor (TFT) with described first gating and is connected; The source electrode of the first conducting thin film transistor (TFT) is connected with the source electrode of the first shutoff thin film transistor (TFT), is connected with the first gating end simultaneously; The drain electrode of the first conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the first shutoff thin film transistor (TFT) is connected with low level signal source;

Described second gating drive sub-circuits comprises:

Second conducting thin film transistor (TFT) and the second shutoff thin film transistor (TFT); The grid of described second conducting thin film transistor (TFT) controls electronic circuit with the grid of the second shutoff thin film transistor (TFT) with described second gating and is connected; The source electrode of the second conducting thin film transistor (TFT) is connected with the source electrode of the second shutoff thin film transistor (TFT), is connected with the second gating end simultaneously; The drain electrode of the second conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the second shutoff thin film transistor (TFT) is connected with low level signal source;

5. gating drive circuit according to claim 4, is characterized in that, described 3rd gating drive sub-circuits comprises:

3rd conducting thin film transistor (TFT) and the 3rd shutoff thin film transistor (TFT); The grid of described 3rd conducting thin film transistor (TFT) controls electronic circuit with the grid of the 3rd shutoff thin film transistor (TFT) with described 3rd gating and is connected; The source electrode of the 3rd conducting thin film transistor (TFT) is connected with the source electrode of the 3rd shutoff thin film transistor (TFT), is connected with the first gating end simultaneously; The drain electrode of the 3rd conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the 3rd shutoff thin film transistor (TFT) is connected with low level signal source;

Described 4th gating drive sub-circuits comprises:

4th conducting thin film transistor (TFT) and the 4th shutoff thin film transistor (TFT); The grid of described 4th conducting thin film transistor (TFT) controls electronic circuit with the grid of the 4th shutoff thin film transistor (TFT) with described 4th gating and is connected; The source electrode of the 4th conducting thin film transistor (TFT) is connected with the source electrode of the 4th shutoff thin film transistor (TFT), is connected with the first gating end simultaneously; The drain electrode of the 4th conducting thin film transistor (TFT) is connected with described input signal source; The drain electrode of the 4th shutoff thin film transistor (TFT) is connected with low level signal source;

6. gating drive circuit according to claim 5, is characterized in that, described gating signal end comprises the first gating signal end and the second gating signal end; First gating signal end and the second gating signal end are respectively used to export described first gating signal and the second gating signal.

7. gating drive circuit according to claim 6, is characterized in that, described first gating controls electronic circuit and comprises: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);

8. gating drive circuit according to claim 7, is characterized in that, described second gating controls electronic circuit and comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT);

9. gating drive circuit according to claim 7, is characterized in that,

Described second gating controls electronic circuit and comprises: the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT);

10. gating drive circuit according to claim 9, it is characterized in that, described 3rd gating controls electronic circuit and comprises: the tenth thin film transistor (TFT), the 11 thin film transistor (TFT), the 12 thin film transistor (TFT), the 13 thin film transistor (TFT) and the 14 thin film transistor (TFT);

The grid of described 14 thin film transistor (TFT) is connected with described second gating signal end with drain electrode, and the source electrode of described 14 thin film transistor (TFT) is connected with the source electrode of described 13 thin film transistor (TFT);

11. gating drive circuits according to claim 9, is characterized in that,

Described 3rd gating controls electronic circuit and comprises: the 13 thin film transistor (TFT) and the 14 thin film transistor (TFT);

The source electrode of described 13 thin film transistor (TFT) is connected with the grid of the 3rd shutoff thin film transistor (TFT) with the grid of described 3rd conducting thin film transistor (TFT), and the source gate of described 13 thin film transistor (TFT) is connected with the drain electrode of described 4th thin film transistor (TFT) with drain electrode;

12. gating drive circuits according to claim 11, it is characterized in that, described 4th gating controls electronic circuit and comprises: the 15 thin film transistor (TFT), the 16 thin film transistor (TFT), the 17 thin film transistor (TFT), the 18 thin film transistor (TFT), the 19 thin film transistor (TFT) and the 20 thin film transistor (TFT);

13. gating drive circuits according to claim 1, is characterized in that, the signal of described input signal source input is gated sweep trigger pip or gated sweep termination signal.

14. 1 kinds of gate driver circuits, comprise the shift register cell of mutual cascade, it is characterized in that, also comprise the gating drive circuit described in the arbitrary claim of claim 1-13, with multiple, each gating end of described gating drive circuit treats that the input end one_to_one corresponding of the circuit of gating is connected respectively, for for treating the signal that the circuit of gating provides input signal source to input, described in treat that the circuit of gating is described shift register cell.

15. 1 kinds of display device, is characterized in that, comprise gate driver circuit according to claim 14.