CN103646864A - Method for improving thickness uniformity of grid side wall spacing layer - Google Patents
Method for improving thickness uniformity of grid side wall spacing layer Download PDFInfo
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- CN103646864A CN103646864A CN201310600961.1A CN201310600961A CN103646864A CN 103646864 A CN103646864 A CN 103646864A CN 201310600961 A CN201310600961 A CN 201310600961A CN 103646864 A CN103646864 A CN 103646864A
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- 238000000034 method Methods 0.000 title claims abstract description 87
- 238000006243 chemical reaction Methods 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 238000002360 preparation method Methods 0.000 claims abstract description 7
- 238000010926 purge Methods 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 10
- 238000000638 solvent extraction Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 5
- 229920006395 saturated elastomer Polymers 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- 238000001179 sorption measurement Methods 0.000 claims description 2
- 238000006386 neutralization reaction Methods 0.000 claims 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 230000003647 oxidation Effects 0.000 abstract description 13
- 238000007254 oxidation reaction Methods 0.000 abstract description 13
- 238000004140 cleaning Methods 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract 5
- 239000002243 precursor Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000012495 reaction gas Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005019 vapor deposition process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 230000035484 reaction time Effects 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000035126 Facies Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a method for improving the thickness uniformity of a grid side wall spacing layer. The method comprises the step of providing a semiconductor silicon wafer with a grid structure. A reaction period comprises the steps of introducing a precursor special gas into the surface of the silicon wafer to be adsorbed until saturation, introducing a cleaning gas, introducing a reaction special gas so as to be reacted with the absorbed precursor special gas at the surface of the silicon wafer, and introducing the cleaning gas again; and the reaction period is repeated until required thickness of SiO2 for spacing is deposited. According to the invention, atomic layer vapor deposition process of a furnace tube is adopted to prepare the grid side wall spacing layer, a traditional tetraethyl orthosilicate (TEOS) process or high-temperature thermal oxidation (HTO) process is replaced in grid side wall spacing layer preparation, thereby improving the step coverage rate and the thickness uniformity of the grid side wall spacing layer, and having the characteristics of high growth rate, low reaction gas consumption, good step coverage rate, good film properties, low thermal budget and the like.
Description
Technical field
The present invention relates to semiconductor device preparation field, especially by adopting atomic layer deposition (ALD) to improve the method for the grid curb wall space layer uniformity.
Background technology
In semiconductor device, when transistor channel shortens to a certain degree, just there will be short-channel effect, when short channel has reduced to certain length, will affect the life-span of threshold voltage and the device of short channel.In addition, grid also easily suffers erosion in semiconductor device preparation process.
Grid curb wall wall plays an important role to protecting grid and reducing short-channel effect.Grid curb wall wall due to have growth easily, stable, disruptive field intensity, point insulating performance is good and equally with Si surface have a desirable interfacial characteristics, is therefore often used as grid curb wall wall.In existing technology, general traditional tetraethoxysilane (TEOS) technique or high-temperature thermal oxidation (HTO) technique of boiler tube that adopts deposits wall at grid curb wall.
The quality of prepared lateral wall partitioning layer quality, is to be decided by even thickness degree and step coverage in silicon chip, because step coverage and even thickness degree are closely related.In tetraethoxysilane (TEOS) technique, adopt Si (OC
2h
5)
4as the special gas of presoma, at 680 ℃ of temperature, reactive deposition layer, the even thickness degree of the wall of deposition is 2%-4%.And in high-temperature thermal oxidation (HTO) technique, be to adopt SiH
2cl
2or SiH
4as the special gas of presoma, temperature is risen under 780 ℃ of high temperature, reaction generation layer also deposits, and the even thickness degree of the wall of deposition is 1%-3%.
Patent CN101290882A discloses a kind of manufacture method that improves inhomogeneity grid oxic horizon, and this grid oxic horizon is produced on the silicon substrate of making isolation structure of shallow trench, and it comprises the first oxide layer and the second oxide layer.Prior art generates grid oxic horizon by a step thermal oxidation method, causes grid oxic horizon thin and easily make metal-oxide-semiconductor puncture from corner at other flat sites of Thickness Ratio of fleet plough groove isolation structure corner.The manufacture method that improves inhomogeneity grid oxic horizon of the present invention first generates the first oxide layer by thermal oxidation method; Then by chemical vapour deposition (CVD), in this first oxide layer, generate the second oxide layer.The method has adopted thermal oxidation technology to be combined and to prepare grid oxic horizon with chemical vapor deposition method, so that its uniformity improves.
Desirable Step Coverage is as shown in accompanying drawing 1A, and 1 is Semiconductor substrate, and 2 is grid, and 3 is grid curb wall spacer oxide layer, consistency of thickness in visible grid curb wall wall all directions, and the consistent situation of this grid curb wall space layer, also referred to as conformal Step Coverage.Yet, reduce (being reduced to 55nm and following) along with bandwidth, the raising of integrated level, the lateral wall partitioning layer that adopts traditional boiler tube TEOS or HTO technique to prepare, there is the problem that has larger even thickness degree difference between the variation of even thickness degree and step coverage in silicon chip and different silicon chip, in actual technical process, if can not well control, be easy in side wall sharp corner and the situation that occurs uneven thickness along vertical sidewall and bottom, as shown in accompanying drawing 1B, 1 is Semiconductor substrate, 2 is grid, 3 is the oxidation of grid curb wall interval, the grid curb wall wall that visible traditional handicraft obtains, there is poor step coverage, make space layer uniformity variation, cause device performance to have larger difference.
Summary of the invention
Thereby the object of this invention is to provide a kind of new technique, improve grid curb wall space layer uniformity, improve step coverage, thereby improve the performance of semiconductor device.
A first aspect of the present invention provides a kind of method that improves the grid curb wall space layer uniformity, and the concrete steps of the method comprise:
Step S1: the Semiconductor substrate with grid structure is positioned in a reaction chamber;
Step S2: pass into the special gas of presoma in described reaction chamber, the special aspiration of this presoma invests the surface of described grid structure, and after this grid structure adsorption is saturated, to purifying purge technique in described reaction chamber;
Step S3: continue in described reaction chamber and pass into and react special gas, this reacts special gas and the special solid/liquid/gas reactions of the presoma that is adsorbed on described grid structure surface, generation covers after a film on described grid structure surface, and again to purifying purge technique in described reaction chamber;
Step S4: repeating step S2-S3, with the lateral wall partitioning layer being formed by plural layers in the surface preparation of described grid structure.
In above-mentioned method, described generating process is preferably atomic layer deposition technique, more preferably in boiler tube, carries out.
In above-mentioned method, the range of reaction temperature that reacts the special gas of special gas and presoma is preferably 300-500 ℃.
In said method, reaction pressure scope is preferably 0.1-0.4Torr, more preferably 0.2-0.4Torr.
The special gas of presoma described in above-mentioned method is preferably Si[N (CH
3)
2]
3h.
In above-mentioned method, the special gas of presoma be liquid, by carrying gas, carries and passes in boiler tube, and presoma spy gas is unrestricted at the described content carrying in gas.
The gas that carries described in above-mentioned method is N
2or one or both the mixture in Ar.
The special gas of presoma described in said method with carry the mixed range of flow of gas and be preferably 100-400sccm, 200-300sccm more preferably.
The clean air passing into for the first time in above-mentioned method falls the special gas of unnecessary presoma for purifying purge, after purge is clean, stops passing into clean air, then carries out next step.
In above-mentioned method, the special gas of described reaction is preferably O
3, its range of flow is preferably 1-15slm, more preferably 5-10slm.
The clean air passing into for the second time in above-mentioned method falls unnecessary reacting gas for purge, after cleaning up, stops passing into clean air, then carries out subsequent operation.
In above-mentioned method, described clean air is preferably N
2, the purge of clean air guarantees the wall of Generation of atoms layer thickness, the range of flow of purge gas is preferably 5-30slm, more preferably 10-20slm.
In above-mentioned method, reaction equation is:
Si[N (CH
3)
2]
3h+O
3→ SiO
2+ accessory substance
In method of the present invention, described lateral wall partitioning layer material is silicon dioxide.
In method of the present invention, described step S2-S3 often completes once, and grid curb wall wall increases
more preferably
more preferably
A second aspect of the present invention provides grid a kind of as that above-mentioned preparation method prepares, described grid comprises the lateral wall partitioning layer of said method deposition, wherein, the even thickness degree of the wall of the tip position of grid, medium position and bottom position is less than 1%.
The beneficial effect of method of the present invention:
1) atomic layer deposition technique (ALD) has realized the thin film deposition (one-period) that approaches monoatomic layer thickness, have that THICKNESS CONTROL is accurate, in repeated high, the fabulous step coverage of thickness, silicon chip and the good and lower features such as heat budget of even thickness degree between silicon chip, be a kind of desirable grid curb wall spacer process.
2) in above-mentioned method, every generation one deck grid curb wall wall, generation film thickness increase
therefore, by control number reaction time, can simply accurately control the thickness of film, form the film that reaches atomic layer level thickness precision; Because presoma is saturated chemisorbed, therefore do not need to control the homogeneity of reactant flow, also can guarantee to generate the film of large-area uniformity.
Adopt the atomic layer deposition technique of boiler tube to prepare grid curb wall wall, substitute traditional tetraethoxysilane (TEOS) technique or high-temperature thermal oxidation (HTO) technique is prepared grid curb wall wall, thereby improve step coverage and even thickness degree.
Method of the present invention also has high growth rate, low reacting gas consumption, good step coverage, good film characteristics, the low features such as heat budget, uses grid curb wall wall prepared by method of the present invention still to have at low temperatures good film characteristics.
Accompanying drawing explanation
Fig. 1 is that (wherein, Figure 1A is that desirable deposition covers schematic diagram for the schematic diagram of the grid curb wall wall that obtains of traditional handicraft; Figure 1B is that actual deposition covers schematic diagram);
Fig. 2 is method step schematic flow sheet of the present invention;
Fig. 3 be the grid curb wall wall that obtains of atomic layer deposition of the present invention schematic diagram (wherein, Fig. 3 A is top portions of gates positional structure schematic diagram, Fig. 3 B is gate bottom positional structure schematic diagram, and Fig. 3 C is grid medium position structural representation, and Fig. 3 D is grid structure schematic diagram).
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention will be further described, but not as limiting to the invention.
Fig. 2 is method step schematic flow sheet of the present invention, as shown in Figure 2, shown in the special gas of presoma pass through N
2or Ar carries and enters boiler tube, the special gas of presoma, after silicon chip surface absorption is saturated, passes through N
2purge falls the special gas of unnecessary presoma, passes into O
3special gas, O
3special gas reacts with the presoma that is adsorbed on silicon chip surface and generates silicon dioxide spacer layer, passes into N
2purge falls unnecessary O
3.
As can be known from Fig. 2, four above-mentioned steps are a reaction time, often complete a reaction time, silicon dioxide film space layer increases about 1A, in order to guarantee to generate the silicon dioxide film wall of even thickness, need to repeat four above-mentioned steps, the reaction time of repetition, the silicon dioxide film space layer by required generation determined.
Use method of the present invention to carry out the preparation of grid curb wall wall, it is specially provides semiconductor silicon chip, boiler tube, the temperature range of wherein reacting the special gas of special gas and presoma is preferably 300-500 ℃, such as can be 300 ℃, 360 ℃, 410 ℃, 480 ℃, 500 ℃ etc.; The reaction pressure scope of reacting the special gas of special gas and presoma is preferably 0.1-0.4Torr, and 0.2-0.4Torr more preferably, such as being 0.2Torr, 0.3Torr, 0.4Torr etc.
Method of the present invention comprises: first pass into the special gas of presoma; Pass into again clean air, purify purge; After completing, pass into reacting gas; Pass into clean air and purify purge.
Wherein, pass into the special gas Si[N of presoma (CH
3)
2]
3h is saturated to silicon chip surface absorption, and wherein the special gas of presoma is liquid, need to carry gas N
2or Ar or N
2carry and pass in reaction boiler tube with the mist of Ar.While entering boiler tube, the special gas of presoma with carry the mixed range of flow of gas and be preferably 100-400sccm, 200-300sccm more preferably, such as being 200sccm, 210sccm, 250sccm, 275sccm, 300sccm etc.
Pass into purge gas N
2purify purge and fall the special gas Si[N of unnecessary presoma (CH
3)
2]
3h, passes into range of flow and is preferably 5-30slm, and 10-20slm more preferably, such as being 10slm, 13slm, 15slm, 18slm, 20slm etc.
Pass into the special gas O of reaction
3react, be specially and pass into the special gas O of reaction
3the special gas Si[N of presoma (CH with silicon chip surface absorption
3)
2]
3h reacts, reaction generate uniform silicon dioxide layer with and accessory substance.Pass into the special gas O of reaction
3range of flow be preferably 1-15slm, 5-10slm more preferably, such as being 5slm, 6slm, 8slm, 9slm, 10slm etc.
Pass into again purge gas N
2purify purge and fall the special gas O of unnecessary reaction
3, passing into range of flow and be preferably 5-30slm, 10-20slm more preferably, such as being 10slm, 11slm, 14slm, 17slm, 18slm, 20slm etc.
In method of the present invention, often complete four steps described in the present embodiment, grid curb wall space layer can increase
the thickness increasing more preferably
can be for example
Repeat described reaction time, generate wall to desired thickness.
For example, often complete the primary first-order equation cycle, the thickness that wall increases is preferably
as obtained the thickness of grid curb wall wall, be
need reaction repeated cycle 10 times, by that analogy, can obtain accurately the grid curb wall wall of desired thickness.
It should be noted that, the thickness of grid curb wall wall of the present invention is not limited to the above-mentioned numerical value of enumerating.
The invention also discloses a kind of atomic layer gas phase layer deposition boiler tube, this boiler tube comprises the special gas entrance of a presoma, reacts special gas entrance, can carry out the deposition of 125 silicon chips simultaneously.
Fig. 3 is the schematic diagram of the grid curb wall wall that obtains of atomic layer deposition of the present invention, and as shown in Figure 3, Fig. 3 D is grid structure schematic diagram, can find out the grid curb wall space layer distribution uniform that deposition obtains from Fig. 3 D.Wherein, the tip position structural representation that Fig. 3 A is grid, the thickness of silicon dioxide spacer layer is 49nm; Fig. 3 B is the bottom position structural representation of grid, and the thickness of silicon dioxide spacer layer is 49nm; Fig. 3 C is the medium position structural representation of grid, and the thickness of silicon dioxide spacer layer is also 49nm.
As shown in Figure 3, the grid curb wall wall that adopts the method in the embodiment of the present invention to obtain, the pass of its tip position, medium position and bottom position is:
Tip position thickness/medium position thickness=100%;
Medium position thickness/bottom position thickness=100%.
Visible, the tetraethoxysilane that method of the present invention is traditional compared with boiler tube (TEOS) technique or high-temperature thermal oxidation (HTO) technique, the even thickness degree that can significantly improve oxide layer, has outstanding step coverage, step top, middle part and bottom film consistency of thickness.
Method of the present invention is carried out contrasting of grid curb wall wall sedimentary facies related parameter with tetraethoxysilane (TEOS) technique, high-temperature thermal oxidation (HTO) technique, as shown in table 1:
Table 1, tetraethoxysilane (TEOS) and the list of high-temperature thermal oxidation (HTO) concrete technology
Wherein, the computing formula of even thickness degree is as follows:
Yong△ A(unit is %) the representative thickness uniformity, if the thickness of top, middle part and the bottom position of the grid curb wall wall making by the method described in the embodiment of the present invention is A
1, A
2, A
3:
As shown in Table 1, adopt in tetraethoxysilane (TEOS) technique or high-temperature thermal oxidation (HTO) technique, its required reaction temperature is respectively 680 ℃ and 760 ℃, far away higher than the required reaction temperature 200-600 ℃ of method of the present invention; The grid curb wall space layer that adopts tetraethoxysilane (TEOS) technique or high-temperature thermal oxidation (HTO) technique to make, its even thickness degree is respectively 2%-4% and 1%-3%, is all greater than the even thickness degree of the grid curb wall wall that method of the present invention makes.
Method of the present invention is particularly used in low live width, high-aspect-ratio side wall technique has larger advantage.The reaction temperature that it is relatively low, also makes heat budget significantly reduce.
Above specific embodiments of the invention be have been described in detail, but it is as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that this practicality is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (10)
1. a method that improves the grid curb wall space layer uniformity, is characterized in that, the step of described method comprises:
Step S1: the Semiconductor substrate with grid structure is positioned in a reaction chamber;
Step S2: pass into the special gas of presoma in described reaction chamber, the special aspiration of this presoma invests the surface of described grid structure, and after this grid structure adsorption is saturated, to purifying purge technique in described reaction chamber;
Step S3: continue in described reaction chamber and pass into and react special gas, this reacts special gas and the special solid/liquid/gas reactions of the presoma that is adsorbed on described grid structure surface, generation covers after a film on described grid structure surface, and again to purifying purge technique in described reaction chamber;
Step S4: repeating step S2-S3, with the lateral wall partitioning layer being formed by plural layers in the surface preparation of described grid structure.
2. the method for claim 1, is characterized in that, in described step S2 and S3, the special gas of presoma is Si[N (CH
3)
2]
3h.
3. the method for claim 1, is characterized in that, in described step S2, the special gas of presoma be liquid state, by carrying gas, sends into reaction system, described in to carry gas be N
2or one or both the mixture in Ar.
4. method as claimed in claim 3, is characterized in that, in described step S2, the special gas of presoma is 100-400sccm with carrying the mixed range of flow of gas.
5. the method for claim 1, is characterized in that, the range of reaction temperature that reacts the special gas of special gas and presoma in described step S3 is 300-500 ℃, and pressure limit is 0.1-0.4Torr.
6. method as claimed in claim 5, is characterized in that, in described step S3, reacting special gas is O
3, reacting special throughput scope is 1-15slm.
7. the method for claim 1, is characterized in that, described lateral wall partitioning layer material is silicon dioxide.
8. the method for claim 1, is characterized in that, in described step S2 neutralization procedure S3, uses clean air N
2, to purifying purge technique in described reaction chamber, wherein, the range of flow of purge gas is 5-30slm.
9. the method for claim 1, is characterized in that, described step S2-S3 often completes once, and grid curb wall wall increases
10. the semiconductor structure that the method for claim 1 prepares, it is characterized in that, described semiconductor structure comprises the lateral wall partitioning layer of method deposition described in claim 1, and wherein, the even thickness degree of the wall of the tip position of grid, medium position and bottom position is less than 1%.
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| CN104465357B (en) * | 2014-12-31 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | The forming method of Schottky diode barrier |
| CN107749413A (en) * | 2017-10-18 | 2018-03-02 | 武汉新芯集成电路制造有限公司 | It is a kind of to improve memory cell areas and the method for control circuit area side wall thicknesses difference |
| CN107749413B (en) * | 2017-10-18 | 2019-02-19 | 武汉新芯集成电路制造有限公司 | A method of it improving memory cell areas and control circuit area side wall thicknesses is poor |
| WO2021162240A1 (en) * | 2020-02-13 | 2021-08-19 | 주식회사 유진테크 머티리얼즈 | Method for forming thin film by using surface protection material |
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