CN103645692B - Wafer operation control system - Google Patents
Wafer operation control system Download PDFInfo
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- CN103645692B CN103645692B CN201310613051.7A CN201310613051A CN103645692B CN 103645692 B CN103645692 B CN 103645692B CN 201310613051 A CN201310613051 A CN 201310613051A CN 103645692 B CN103645692 B CN 103645692B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention discloses a kind of wafer operation control system, described system comprises memory module and execution module; Described memory module stores the chamber order needing process when each batch of wafer carries out production technology; Wherein a collection of wafer is when entering a reaction chamber and carrying out production technology, store this batch of wafer in described execution module reading memory module need the order through chamber and perform this operation, make this batch of wafer in different chambers, complete all production processes respectively.Technician can judge problem chamber place and corresponding production equipment by the present invention very soon according to electric property testing result, greatly improve the efficiency of operation of pinpointing the problems, also can adjust the process sequence in each chamber in time according to actual conditions, to adapt to the various condition of production simultaneously.
Description
Technical field
The present invention relates to semiconductor preparation field, specifically, be specifically related to a kind of wafer operation control system.
Background technology
Advanced integrated circuit fabrication process generally all comprises the operation of hundreds of step, the slight errors of any link all will cause the inefficacy of whole chip, constantly reducing particularly along with circuit critical size, it is stricter to the requirement of technology controlling and process, so the checkout equipment of the defect detection equipment being all configured with optics and electronics for finding timely and deal with problems in process of production and the new energy of electricity is to guarantee the quality of product.
As the part that Fig. 1 is an entire manufacturing process flow process, include technique, measurement, defects detection etc. respectively, but carry out because on-line checkingi is all sampling, the test of such as product parameters carries out in some fc-specific test FC structures, the detection of defect is also just inspected by random samples for the part wafer of the product of part, so often just can find that there is the phenomenon of inefficacy wafer when product carries out final electrical functions test.If need to find problematic processing step and equipment on production line to be relatively difficult for this kind of problem, because there is hundreds of platform equipment on a production line, and this equipment with 4 chamber operations has more than tens too, the order of wafer operation in chamber is all the same simultaneously, will be with very large workload like this to the slip-stick artist searching reason; On a production line simultaneously, if there is no Problems existing on Timeliness coverage production line and equipment continues running, follow-up production can be had a strong impact on, cause the yield of Total Product to decline, can not well investigate in-problem relevant device and step simultaneously.
According to above table, the wafer of same batch carries out production process successively respectively in chamber A, B, C, and in this technological process, no matter carrying out any technique is all complete in a fixing chamber.If a certain operation of carrying out of cavity C goes wrong, and normally there is not this problem in the equipment of other processing chambers, also just detected by the method for sampling in current prior art, may Timeliness coverage cavity C occur abnormal, only find that there is the existence of problem wafers at final electrical testing; When investigating, because all chambers all carry out same operation, if want accurately to learn which chamber and concrete equipment have problem and just needs a large amount of time and efforts, unavoidably add production cost.
Chinese patent (CN101718989A) discloses a kind of sampling method, and be applicable to a multiple product production line with multiple equipment, comprise: provide an equipment record, wherein this equipment record stores a data from the sample survey of equipment described in each.Afterwards, inspect each data from the sample survey in this equipment record, to find out at least one non-sampling device in described equipment.Then, confirm via non-sampling device described at least wherein one performed by multiple product batches of at least one technological operation.Finally, determine at least described product batches one of them, to carry out a pick test.
The method improves detection efficiency by body recording unit, but due to the randomness of sampling Detection, possibly cannot detect that the product of a certain batch goes wrong in time, carry out investigating also cumbersome even if pinpoint the problems in final test, need the manpower and materials of at substantial.
Summary of the invention
For above the deficiencies in the prior art, the invention provides a kind of wafer operation control system, wherein, described system comprises memory module and execution module;
Described memory module stores the chamber order needing process when each batch of wafer carries out production technology;
Wherein a collection of wafer is when entering a reaction chamber and carrying out production technology, store this batch of wafer in described execution module reading memory module need the order through chamber and perform this operation, make this batch of wafer in different chambers, complete all production processes respectively.
Above-mentioned wafer operation control system, wherein, described memory module includes one can edit cell, describedly can be used for needing to adjust according to technique to storing the chamber order of process when each batch of wafer carries out production technology in memory module by edit cell.
Above-mentioned wafer operation control system, wherein, each described reaction chamber includes some production equipments;
Wherein, each the production equipment comprised in same chamber is for carrying out different operations to wafer.
Above-mentioned wafer operation control system, wherein, includes partly or entirely identical production equipment in each described reaction chamber.
Above-mentioned wafer operation control system, wherein, the chamber order of part or all of batch of wafer process is different.
Above-mentioned wafer operation control system, wherein, described wafer operation control system at least controls the reaction chamber order of process required for two batches of wafers.
Owing to present invention employs above technical scheme, can realize in large scale integrated circuit production run by this system, the job state of wafer can be monitored very well, if wafer goes wrong in a certain operation, can be found out fast by this system may in-problem equipment and chamber, adjusts the operation of carrying out in each reaction chamber in real time and monitor by this system.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is prior art some processes process flow diagram when carrying out production technology;
Fig. 2 is the present invention's some processes process flow diagram when carrying out production technology;
Fig. 3 is the composition schematic diagram of wafer operation control system provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The invention provides a kind of method of efficiently reviewing wafer job state, as Figure 2-3, when each chamber carries out explained hereafter, can realize very well monitoring wafer job state by a wafer operation control system, once a operation wherein reflection chamber detected in final electrical performance testing in has problem, the equipment that discovery that can be very fast goes wrong.
Wherein, each reaction chamber includes some production equipments, and the production equipment that comprises of each chamber is all identical or part is identical, and every platform production equipment is used for carrying out different operations to wafer.
Wafer operation control system at least controls the reaction chamber order of process required for two batches of wafers, and it comprises memory module and execution module; Memory module stores the chamber order needing process when each batch of wafer carries out production technology, and this memory module include one can edit cell, can be used for needing to adjust according to technique to storing the chamber order of process when each batch of wafer carries out production technology in memory module by edit cell;
Wafer is when entering differential responses chamber and carrying out production technology, execution module enters the difference of reaction chamber according to wafer, store this batch of wafer in reading memory module need the order through chamber and perform this operation, make this batch of wafer in different chambers, complete all production processes respectively.
A form is provided to be further elaborated the present invention below:
As shown in above table, include 3 chambers A, B, C, each chamber includes equipment 1, equipment 2, equipment 3, every platform equipment is all for carrying out identical production process to wafer, such as equipment 1 pair of wafer carries out the first production technology, equipment 2 pairs of wafers carry out the second production technology, and equipment 3 pairs of wafers carry out the 3rd production technology.The memory module of wafer operation control system provided by the invention stores wafer 1 ~ 12 when carrying out three above-mentioned production technologies, and wafer needs through different reaction chambers and carries out operation, specific as follows:
When product wafer 1 enters into chamber A, the equipment 1,2,3 in chamber A carries out corresponding first, second, third production technology to wafer successively;
When product wafer 2 enters into B chamber, the equipment 1 first in A chamber carries out the first technique to it, then product wafer 2 is fed through chamber A, utilizes the equipment 2,3 in chamber A to carry out second, third follow-up production technology to it;
When product wafer 3 enters into C chamber, first the equipment 1 in C chamber carries out the first technique to it, then product wafer 2 is fed through chamber B, the equipment 2 in chamber B is utilized to carry out the second technique, again product wafer 3 is fed through chamber A complete the second technique in chamber B after, utilizes the equipment 3 pairs of wafers in chamber A to carry out the 3rd technique;
When product wafer 4 enters into A chamber, the equipment 1 first in A chamber carries out the first technique to it, then product wafer 2 is fed through chamber B, utilizes the equipment 2,3 in chamber B to carry out second, third follow-up production technology to it;
……
When product wafer 10 enters into A chamber, the equipment 1 first in A chamber carries out the first technique to it, then product wafer 2 is fed through chamber B, utilizes the equipment 2 in chamber B to carry out the second technique; Again wafer 10 is fed through cavity C after second technique completes, utilizes the equipment 3 in cavity C to proceed the 3rd technique;
When product wafer 11 enters into B chamber, the equipment 1 first in B chamber carries out the first technique to it, then product wafer 11 is fed through cavity C, utilizes the equipment 2 in cavity C to carry out the second technique; After second technique completes, wafer 11 is fed through chamber A, utilizes the equipment 3 in chamber A to proceed the 3rd technique;
When product wafer 11 enters into B chamber, the equipment first in B chamber carries out the first technique to it, then product wafer 11 is fed through cavity C, utilizes the equipment in cavity C to carry out the second technique; After second technique completes, wafer 11 is fed through chamber A, utilizes the equipment in chamber A to proceed the 3rd technique;
When product wafer 12 enters into C chamber, the equipment first in C chamber carries out first, second technique to it; After second technique completes, wafer 11 is fed through chamber A, utilizes the equipment in chamber A to proceed the 3rd technique
Because the wafer of same batch is not complete all operations in a chamber, and be through different chambers and complete all operations respectively, if a wherein operation of cavity A has problem, technician can find out in-problem chamber and equipment very soon according to the test of final electrical functions;
Simultaneously, in an embodiment of the present invention, if have any one reaction chamber A due to the reasons such as normal periodic maintenance maintenance or fault damage cause carrying out explained hereafter time, technician can according to process requirements, by in memory module can edit cell adjust each batch of wafer need the chamber of process order carry out dynamic conditioning, such as by wafer 1-6 process chamber order be adjusted to the order shown in following table, once wherein there is problem in a cavity B, the chamber obtaining ging wrong and concrete production equipment can be investigated fast equally, this not with repeat.
In sum, owing to present invention employs above technical scheme, control each reaction chamber by a wafer operation control system and different production processes is carried out to wafer, if detect that a certain operation of a wherein chamber goes wrong in the test of final electrical functions, because wafer carries out complete production technology by different reaction chambers, technician can judge problem chamber place and corresponding production equipment very soon according to electric property testing result, greatly improve the efficiency of operation of pinpointing the problems, also can adjust the process sequence in each chamber in time according to actual conditions simultaneously, to adapt to the various condition of production.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (6)
1. a wafer operation control system, is characterized in that, described system comprises memory module and execution module;
Described memory module stores the chamber order needing process when each batch of wafer carries out production technology;
Wherein a collection of wafer is when entering a chamber and carrying out production technology, described execution module reads in memory module and stores this batch of wafer and need order through chamber and executable operations, makes this batch of wafer in different chambers, complete all production processes respectively.
2. wafer operation control system as claimed in claim 1, it is characterized in that, described memory module includes one can edit cell, describedly can be used for needing to adjust according to technique to storing the chamber order of process when each batch of wafer carries out production technology in memory module by edit cell.
3. wafer operation control system as claimed in claim 1, it is characterized in that, each described chamber includes some production equipments;
Wherein, each the production equipment comprised in same chamber is for carrying out different operations to wafer.
4. wafer operation control system as claimed in claim 3, is characterized in that, include partly or entirely identical production equipment in each described chamber.
5. wafer operation control system as claimed in claim 1, is characterized in that, the chamber order of part or all of batch of wafer process is different.
6. wafer operation control system as claimed in claim 1, is characterized in that, described wafer operation control system at least controls the chamber order of process required for two batches of wafers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310613051.7A CN103645692B (en) | 2013-11-26 | 2013-11-26 | Wafer operation control system |
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| CN201310613051.7A CN103645692B (en) | 2013-11-26 | 2013-11-26 | Wafer operation control system |
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| CN103645692A CN103645692A (en) | 2014-03-19 |
| CN103645692B true CN103645692B (en) | 2016-04-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9002497B2 (en) * | 2003-07-03 | 2015-04-07 | Kla-Tencor Technologies Corp. | Methods and systems for inspection of wafers and reticles using designer intent data |
| CN100388451C (en) * | 2004-11-02 | 2008-05-14 | 力晶半导体股份有限公司 | Defect detection method |
| CN101421433B (en) * | 2006-02-10 | 2013-11-06 | 分子间公司 | Method and apparatus for combinatorially varying materials, unit process and process sequence |
| CN101196732A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method and system for monitoring semiconductor production line |
| US8143602B2 (en) * | 2009-03-25 | 2012-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-volume manufacturing massive e-beam maskless lithography system |
| CN102506773B (en) * | 2011-09-28 | 2016-03-09 | 上海华虹宏力半导体制造有限公司 | Detect the method for wafer surface roughness |
| CN102446786B (en) * | 2011-11-28 | 2013-12-04 | 上海华力微电子有限公司 | Device monitoring method during semiconductor process |
| CN102751219A (en) * | 2012-07-26 | 2012-10-24 | 上海宏力半导体制造有限公司 | Semiconductor device |
| CN102937594B (en) * | 2012-11-02 | 2015-01-21 | 上海华力微电子有限公司 | Defect detecting system and method |
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