CN103632984B - Without the integrated approach of the mounted thick film hybrid integrated circuit of lead-in wire flat table - Google Patents
Without the integrated approach of the mounted thick film hybrid integrated circuit of lead-in wire flat table Download PDFInfo
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- CN103632984B CN103632984B CN201310700979.9A CN201310700979A CN103632984B CN 103632984 B CN103632984 B CN 103632984B CN 201310700979 A CN201310700979 A CN 201310700979A CN 103632984 B CN103632984 B CN 103632984B
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- thick film
- integrated circuit
- hybrid integrated
- ceramic substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses without the mounted thick film hybrid integrated circuit integrated approach of lead-in wire flat table; the method adopts on a ceramic substrate; directly external for thick film hybrid integrated circuit link is produced on the bottom surface of ceramic substrate; external link is plane; hybrid integrated is carried out in the front of ceramic substrate and bottom surface; thick film conduction band, thick film stopband, thick-film capacitor, thick film inductance are adopted to dielectric thick film seals, insulation protection, adopt dielectric slurry to carry out paintings envelope to semiconductor bare chip and solidification is protected.This method feature has: 1. without package casing, volume-diminished; 2. without pin and corresponding lead, High-frequency Interference is reduced; 3. realize surface-mount type to install, reduce equipment volume, the high frequency performance of hoisting device; 4. change system reliability is improved.The integrated circuit that this method is produced is widely used in the fields such as space flight, aviation, boats and ships, electronics, communication, Medical Devices, Industry Control, is specially adapted to change system miniaturization, high frequency, highly reliable field.
Description
Technical field
The present invention relates to integrated circuit, furthermore, relate to thick film hybrid integrated circuit, particularly relate to surface-mount type thick film hybrid integrated circuit.
Background technology
In the integrated technology of original hybrid circuit, on a ceramic substrate, semiconductor chip, chip components and parts directly being filled is attached on thick film substrate, bonding wire (spun gold or Si-Al wire) is adopted to carry out the wire bonding of chip and substrate again, the wire bonding of substrate and pin, complete whole electrical equipment to connect, finally in specific atmosphere, Guan Ji and pipe cap are sealed to form.The subject matter that the integrated technology of original hybrid circuit exists to adopt Guan Ji and pipe cap to encapsulate internal circuit, because Guan Ji is large with pipe cap volume, pin long, it is many and longer to be connected the lead of pin, therefore, after encapsulation, the volume of thick film hybrid integrated circuit is comparatively large, High-frequency Interference is large, is subject to certain restrictions in applications such as equipment miniaturization, high frequencies.
Through retrieval, the application part relating to thick film hybrid integrated circuit in Chinese patent database has 11, substantially in recent years apply for, as No. 200910102792.2 " bonding system of high-reliability thick-film mixed integrated circuit and manufacture methods thereof ", No. 201110446104.1 " integrated approach of the controlled thick film hybrid integrated circuit of high integrated high-reliability working temperature ", No. 201210396194.2 " integrated approaches of highly sensitive temperature control thick film hybrid integrated circuit ", No. 201210496732.5 " integrated approaches of high-density thick-film hybrid integrated circuit " etc.Also there is no the application part without the mounted thick film hybrid integrated circuit of lead-in wire flat table at present.
Summary of the invention
Object of the present invention is just to provide a kind of without the mounted thick film hybrid integrated circuit integrated approach of lead-in wire flat table, by cancelling package casing (containing Guan Ji, pipe cap), cancelling pin and lead thereof, thus solve the integrated technology Problems existing of original hybrid integrated circuit.
To achieve the above object of the invention, inventor provide without lead-in wire flat table mounted thick film hybrid integrated circuit integrated approach and original thick film hybrid integrated circuit unlike: it does not need Guan Ji, pin and is connected the lead-in wire of pin, but adopt on a ceramic substrate, directly external for thick film hybrid integrated circuit link is produced on the bottom surface of ceramic substrate, external link is planar shaped; Carry out hybrid integrated in the front of ceramic substrate and bottom surface, front and bottom surface thick film conduction band, thick film stopband, thick-film capacitor, thick film inductance are adopted to dielectric thick film seals, insulation protection; Dielectric slurry is adopted to carry out painting envelope and solidification protection to the semiconductor bare chip of front hybrid integrated; Specific practice cancels the sealing cap operation of original integrated approach, increases following operation:
(1) before the printing of thick film conduction band, substrate through-hole drilling process is increased;
(2) while carrying out conduction band printing, via metal filled therewith is carried out;
(3) exit solder side carries out thickening printing;
(4) after stopband trims, carry out the printing of dielectric slurry, adopt aluminum oxide ceramic slurry, sintering film forming;
(5) assemble with bonding after semiconductor bare chip panel region be coated with envelope dielectric slurry, adopt low temperature solidified glass slurry to carry out paintings and seal.
The aperture precision of above-mentioned substrate through-hole punching controls within 0.1 μm.
The process conditions of above-mentioned sintering film forming are: temperature is 650 DEG C, 60min, sinters in nitrogen protection environment.
The process conditions of above-mentioned low-temperature setting are: temperature is 400 DEG C, 45min, complete the solidification being coated with envelope dielectric slurry in nitrogen protection environment.
What integrated approach of the present invention was integrated has following characteristics without the mounted thick film hybrid integrated circuit of lead-in wire flat table: 1. without package casing, volume significantly reduces; 2. without pin and corresponding lead, corresponding High-frequency Interference is reduced; 3. realize surface-mount type to install, reduce equipment volume, the high frequency performance of hoisting device; 4. the reliability of change system is improved.
The integrated circuit that the inventive method is produced is widely used in the fields such as space flight, aviation, boats and ships, electronics, communication, Medical Devices, Industry Control, be specially adapted to change system miniaturization, high frequency, highly reliable field, there is wide market prospects and application space.
Accompanying drawing explanation
Fig. 1 is the integrated circuit schematic that the inventive method is produced, Fig. 2 is for implementing ceramic substrate through hole schematic diagram of the present invention, Fig. 3 is for implementing thick film conduction band of the present invention, filling through hole schematic diagram, Fig. 4 is for implementing thick film stopband schematic diagram of the present invention, Fig. 5 is for implementing insulating thick film medium protective layer schematic diagram of the present invention, Fig. 6 is for implementing ball-type weld zone of the present invention schematic diagram, Fig. 7 is for implementing assembling of the present invention and bonding schematic diagram, Fig. 8 is coated with envelope schematic diagram for implementing dielectric slurry of the present invention, Fig. 9 is original process flow diagram, Figure 10 is the process flow diagram of the inventive method.
In above-mentioned each figure, 1 is ceramic substrate, and 2 is through hole; 3 is exit solder side, and 4 is conduction band/bonding region, and 5 is stopband; 6 is dielectric protective layer; 7 is ball-type weld zone, and 8 is chip components and parts, and 9 is semiconductor bare chip; 10 is bonding wire; 11 is packaged chip, and 12 is dielectric painting sealing, and 13 is metal throuth hole.
Embodiment
Embodiment: as shown in Figure 10, technique comprises following operation in the technological process of the inventive method:
(1) preparation of ceramic substrate, Gold conductor, ruthenium system resistance slurry;
(2) substrate cleaning and oven dry, shell clean and dry;
(3) substrate through-hole punching, aperture precision controls within 0.1 μm;
(4) thick film conductor paste printing conduction band, and 10min is dried at 150 DEG C;
(5) via metal filled therewith;
(6) exit solder side once thickeies printing;
(7) resistance slurry printing stopband, and 10min is dried at 150 DEG C;
(8) film forming is at 850 DEG C of sintering 10min, total time 35min of film forming and sintering;
(9) laser trim resistor;
(10) electric parameter and functional test;
(11) dielectric slurry printing, adopt aluminum oxide ceramic slurry, sintering temperature is 650 DEG C, 60min, in nitrogen protection environment, sinter film forming;
(12) scribing is separated;
(13) thick film substrate is assembled on the base of Guan Ji;
(14) assembled semiconductor chip and chip components and parts;
(15) with silicon-aluminium wire or gold wire bonding connect with the circuit completing semiconductor chip, substrate is connected with the circuit of pin;
(16) assemble with bonding after semiconductor bare chip panel region be coated with envelope dielectric slurry, adopt low temperature solidified glass slurry to carry out paintings and seal, curing temperature is 400 DEG C, 45min, completes in nitrogen protection environment;
(17) performance test;
(18) burn-in screen, leak check;
Adopt the inventive method, by cancelling package casing (containing Guan Ji, pipe cap), cancelling pin and lead thereof, the problems such as after the encapsulation that the integrated technology solving original hybrid circuit exists, the volume of thick film hybrid integrated circuit is comparatively large, High-frequency Interference is large, achieve the application in fields such as equipment miniaturization, high frequencies.
Claims (3)
1. without the mounted thick film hybrid integrated circuit integrated approach of lead-in wire flat table, its basic technology is conventional thick film hybrid integrated circuit manufacture craft, it is characterized in that: adopt the direct bottom surface external for thick film hybrid integrated circuit link being produced on ceramic substrate on a ceramic substrate, external link is planar shaped, hybrid integrated is carried out in the front of ceramic substrate and bottom surface, to thick film conduction band, thick film stopband, thick-film capacitor, thick film inductance adopts dielectric thick film to seal, insulation protection, dielectric slurry is adopted to carry out painting envelope and solidification protection to the semiconductor bare chip of front hybrid integrated, specific practice cancels former methodical sealing cap operation, increases following operation:
(1) before the printing of thick film conduction band, increase substrate through-hole drilling process;
(2), while carrying out conduction band printing, carry out via metal filled therewith;
(3) exit solder side carries out thickening printing;
(4) after stopband trims, carry out the printing of dielectric slurry, adopt aluminum oxide ceramic slurry, sintering film forming;
Assemble with bonding after semiconductor bare chip panel region be coated with envelope dielectric slurry, adopt low temperature solidified glass slurry to carry out paintings and seal; The process conditions of described low-temperature setting are: temperature is 400 DEG C, 45min, complete the solidification being coated with envelope material in nitrogen protection environment.
2. integrated approach as claimed in claim 1, is characterized in that the aperture precision that described substrate through-hole is punched controls within 0.1 μm.
3. integrated approach as claimed in claim 1, is characterized in that the process conditions of described sintering film forming are: temperature is 650 DEG C, 60min, sinters in nitrogen protection environment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310700979.9A CN103632984B (en) | 2013-12-19 | 2013-12-19 | Without the integrated approach of the mounted thick film hybrid integrated circuit of lead-in wire flat table |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310700979.9A CN103632984B (en) | 2013-12-19 | 2013-12-19 | Without the integrated approach of the mounted thick film hybrid integrated circuit of lead-in wire flat table |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103632984A CN103632984A (en) | 2014-03-12 |
| CN103632984B true CN103632984B (en) | 2016-03-23 |
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| CN201310700979.9A Active CN103632984B (en) | 2013-12-19 | 2013-12-19 | Without the integrated approach of the mounted thick film hybrid integrated circuit of lead-in wire flat table |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485324A (en) * | 2014-12-15 | 2015-04-01 | 贵州振华风光半导体有限公司 | Lead-less ball foot surface adhesion type microwave film hybrid integrated circuit and integration method thereof |
| CN104465607A (en) * | 2014-12-15 | 2015-03-25 | 贵州振华风光半导体有限公司 | Leadless plane surface-mounted type microwave thin film hybrid integrated circuit and integration method thereof |
| CN105552062A (en) * | 2015-12-04 | 2016-05-04 | 贵州振华风光半导体有限公司 | Method for integrating anti-interference semiconductor integrated circuit |
| CN105489505A (en) * | 2015-12-04 | 2016-04-13 | 贵州振华风光半导体有限公司 | Integration method for anti-interference and corrosion-resistant thin film hybrid integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208352A (en) * | 2010-03-29 | 2011-10-05 | 佑每佑科技股份有限公司 | Manufacturing method and structure of ceramic copper-plated base plate |
| CN103107107A (en) * | 2012-12-12 | 2013-05-15 | 贵州振华风光半导体有限公司 | Method of improving thick film hybrid integrated circuit homogenesis bonding system batch productbility |
| CN103165569A (en) * | 2011-12-19 | 2013-06-19 | 同欣电子工业股份有限公司 | Semiconductor airtight packaging structure and manufacturing method thereof |
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- 2013-12-19 CN CN201310700979.9A patent/CN103632984B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208352A (en) * | 2010-03-29 | 2011-10-05 | 佑每佑科技股份有限公司 | Manufacturing method and structure of ceramic copper-plated base plate |
| CN103165569A (en) * | 2011-12-19 | 2013-06-19 | 同欣电子工业股份有限公司 | Semiconductor airtight packaging structure and manufacturing method thereof |
| CN103107107A (en) * | 2012-12-12 | 2013-05-15 | 贵州振华风光半导体有限公司 | Method of improving thick film hybrid integrated circuit homogenesis bonding system batch productbility |
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| CN103632984A (en) | 2014-03-12 |
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Address after: 550018 Guizhou Province, Guiyang city new North Avenue No. 238 Patentee after: Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd. Address before: 550018 Guizhou Province, Guiyang city new North Avenue No. 238 Patentee before: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR Co.,Ltd. |