CN103632947B - 为使用全金属栅极的互补金属氧化物半导体集成多阈值电压器件的方法和*** - Google Patents
为使用全金属栅极的互补金属氧化物半导体集成多阈值电压器件的方法和*** Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 95
- 239000002184 metal Substances 0.000 title claims abstract description 95
- 230000000295 complement effect Effects 0.000 title claims abstract description 10
- 230000010354 integration Effects 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 title description 5
- 229910044991 metal oxide Inorganic materials 0.000 title description 3
- 150000004706 metal oxides Chemical class 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000003475 lamination Methods 0.000 claims description 81
- 239000011435 rock Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 20
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 15
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 10
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 6
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 6
- 239000000395 magnesium oxide Substances 0.000 claims description 6
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 39
- 230000009471 action Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 10
- 239000012212 insulator Substances 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000009933 burial Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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Abstract
本发明涉及为使用全金属栅极的互补金属氧化物半导体集成多阈值电压器件的方法和***。提供衬底,该衬底上已形成有第一区域和与所述第一区域互补类型的第二区域。在所述衬底之上沉积栅极电介质,并且在所述栅极电介质之上沉积第一全金属栅极叠层。去除所述第一区域之上的所述第一全金属栅极叠层以产生所得到的结构。与所述第一区域之上的所述栅极电介质相接触地在所得到的结构之上沉积第二全金属栅极叠层。密封所述第一和第二全金属栅极叠层。
Description
技术领域
本发明涉及电气、电子以及计算机领域,更具体地,涉及硅器件和集成技术等。
背景技术
特别地对于低功率(LP)应用而言,超过20nm节点的按比例缩小体技术(scalingbulk technology)面临着艰难的挑战,部分是由于密度、功率和性能的竞争性要求,并且部分是因为增加的器件变化和寄生效应。芯片上***(SoC)应用需要各种晶体管组来实现功率和性能之间的最佳权衡。
此外,随着间距继续按比例缩小,想要能够将接触着陆到正确的位置变得越来越难。全金属栅极技术使得能够实现自对准的接触(self-aligned contact)。对于SoC应用,多阈值电压(Vt)是重要的技术要求。诸如极薄绝缘体上硅(ETSOI)或FinFET(鳍型场效应晶体管)的完全耗尽器件通常需要功函数调制来获得不同的Vt,这不可能通过沟道掺杂实现。
发明内容
本发明的原理为使用全金属栅极的互补金属氧化物半导体提供了用于集成多阈值电压器件的技术。在一个方面中,一种示例性方法包括以下步骤:提供衬底,该衬底上已形成有第一区域和与所述第一区域互补类型的第二区域;在所述衬底之上沉积栅极电介质;在所述栅极电介质之上沉积第一全金属栅极叠层;去除所述第一区域之上的所述第一全金属栅极叠层 以产生所得到的结构;与所述第一区域之上的所述栅极电介质相接触地在所述所得到的结构之上沉积第二全金属栅极叠层;以及密封(encapsulate)所述第一和第二全金属栅极叠层。
在另一方面中,一种示例性电路结构包括:衬底,其上已形成有第一晶体管和第二晶体管,所述第一晶体管具有源极、漏极和沟道,所述第二晶体管具有源极、漏极和沟道且是与所述第一晶体管互补的类型。还包括:第一全金属栅极叠层,其形成在所述第一晶体管的沟道之上;第二全金属栅极叠层,其形成在所述第二晶体管的沟道之上;第一密封物(encapsulation),其包围所述第一全金属栅极叠层;第二密封物,其包围所述第二全金属栅极叠层;硅化的接触,其位于所述第一和第二密封物之间;以及自对准的接触,其从所述硅化的接触凸出。所述第一全金属栅极叠层由将所述第一晶体管调制到第一阈值电压的材料形成,并且所述第二全金属栅极叠层由将所述第二晶体管调制到不同于所述第一阈值电压的第二阈值电压的材料形成。
如本文中所使用的,“促进”一动作包括执行该动作、使该动作更容易、帮助执行该动作或者使得该动作被执行。因此,通过举例而并非限制,在一个计算机处理器上执行的指令可以通过发送适当的(一个或多个)命令以使得由一件半导体处理设备执行的动作被执行或者辅助该动作被执行,来促进由该件半导体处理设备执行的动作。为了避免疑问,当一个行动者通过并非执行一动作而促进该动作时,该动作仍由某个实体或实体组合执行。
本发明的技术可以提供显著的有益技术效果。例如,一个或多个实施例可以提供下述优点中的一个或多个:
·既实现Vt调制也实现自对准的接触
·通过材料和工艺使得Vt移动
·减少对沟道掺杂的需要或消除沟道掺杂(避免短沟道惩罚(penalty))
·减少对地平面/背栅的需要或消除地平面/背栅(避免严重的集成挑战)
·使得能以先栅极集成(gate-first integration)实现简单的工艺流程
·扩展到平面PDSOI(部分耗尽的SOI)/体和FinFET
通过下面对其示例性实施例的详细描述,本发明的这些和其它特征及优点将变得显而易见,将结合附图来阅读所述详细描述。
附图说明
图1示出了具有与自对准的接触(SAC)集成的全金属栅极(FMG)的两个晶体管的示意图;
图2示出了与图1的晶体管类似的具体详细实施例的横截面视图;以及
图3-10示出了制造图1和2的晶体管时的示例性步骤。
具体实施方式
如所述的,特别地对于低功率(LP)应用而言,超过20nm节点的按比例缩小体技术面临着艰难的挑战,部分是由于密度、功率和性能的竞争性要求,并且部分是因为增加的器件变化和寄生效应。芯片上***(SoC)应用需要各种晶体管组来实现功率和性能之间的最佳权衡。
此外,也如所述的,随着间距继续按比例缩小,想要能够将接触着陆到正确的位置变得越来越难。全金属栅极技术使得能够实现自对准的接触。对于SoC应用,多阈值电压(Vt)是重要的技术要求。诸如极薄绝缘体上硅(ETSOI)或FinFET(鳍型场效应晶体管)的完全耗尽器件通常需要功函数调制来获得不同的Vt,这不可能通过沟道掺杂实现。
一个或多个实施例为体或SOI(绝缘体上硅)技术提供了在同一芯片上实现多Vt器件(低、中和高Vt)的方法和工艺。一个或多个实施例比现有技术简单并且克服了当前的先栅极(gate-first)集成方案所遇到的若干挑战。一个或多个实施例也使得能够实现可用于自对准的接触的全金属栅极集成。一个或多个实施例可以扩展到诸如FinFET的非平面器件。
一个或多个实施例使用全金属栅极叠层来在同一芯片上实现多Vt器 件。一个或多个实例使得能够同时实现Vt调制和自对准的接触;通过材料和工艺的Vt移动;减少对沟道掺杂的需要或消除了沟道掺杂(避免短沟道惩罚);减少了对地平面/背栅的需要或消除了地平面/背栅(避免严重的集成挑战);能够以先栅极集成实现简单的工艺流程;和/或可扩展到平面PDSOI/体和FinFET技术。
图1示出了包括与自对准的接触(SAC)集成的全金属栅极(FMG)的示意图。注意,衬底112具有由硅或任何其它适当的半导体形成的沟道113。还要注意,一个或多个实施例可以使用各种技术实现;例如,体硅或该图中示出的绝缘体上硅(SOI)。栅极电介质以118示出,硅化的接触以119示出。全金属栅极叠层127包括第一金属层121、第二金属层123和第三金属层125。该全金属栅极叠层以栅极硬掩膜129(例如,SiN)结束并且在两侧具有隔离物124(例如,SiN)。自对准的接触以130示出并且它们被层间电介质(绝缘体)117分隔开。对于绝缘体117,适当材料的非限制性实例包括诸如氧化硅和氮化硅的电介质。例如,电介质膜可以被沉积或旋涂。可以例如使用已知的工艺由钨形成导电接触130,或使用已知的工艺由铝形成导电接触130。
因此,在一个或多个实施例中,全金属栅极(FMG)叠层具有绝缘体、若干个金属层并且然后被氮化硅或类似物覆盖。FMG由此被完全密封,以便不对工艺中稍后的接触敞开。氮化硅是隔离物和硬掩膜的优选材料,但是可以使用任何合适的绝缘体。
对于nMOS器件,高阈值电压(HVT)选项包括没有盖层的全金属栅极(FMG)叠层以及具有“P”盖层的FMG叠层。中阈值电压(MVT)选项包括具有“A”盖层的FMG叠层和具有“A”盖层和“P”盖层的FMG叠层。低阈值电压(LVT)选项包括FMG叠层和“A”盖层。
对于pMOS器件,HVT选项包括具有“A”盖层的FMG叠层;MVT选项包括FMG叠层和“A”盖层、FMG叠层、以及“A”盖层、以及“P”盖层、或者厚的FMG叠层;并且LVT选项包括薄FMG叠层。
在一些情况下,在nMOS和pMOS器件上都采用全金属栅极,并且 对于模拟和输入/输出(IO)器件也使用全金属栅极。在FMG叠层中使用盖层与金属厚度相结合来调制Vt。
现在应当注意图2,图2与第一说明性实施例相结合描绘了用于多Vt的FMG栅极叠层。如所述的,在nMOS和pMOS器件上都采用全金属栅极,并且对于模拟和IO器件也使用全金属栅极。在FMG叠层中使用盖层与金属厚度相结合来调制Vt。特别地,注意视图402和视图404,穿过1/4间隙nMOS区域410的横截面;视图406,穿过1/4间隙pMOS区域412的横截面;以及视图408,穿过中间间隙(mid gap)pMOS区域414的横截面。下面将解释符号“HVT pMOS”、“HVT nMOS”和“中间间隙nMOS”。区域410、412、414形成在合适的衬底(未示出)上并且被隔离区416、418分隔开。区域416、418例如可以使用公知的浅沟槽隔离工艺由氧化硅形成。注意界面层420,其可以在高k沉积之前由例如在硅衬底上生长的适当的氧化物或氧氮化物形成。还要注意氧化铪(HfO2)层422。
现在参考与图1类似的视图404。在1/4间隙nMOS区域410的顶上是界面层420和氧化铪层422。TiN层424-3对应于金属1,图1中的元件121;TaAlN-T3对应于金属2,图1中的元件123;并且钨层432对应于金属3,图1中的元件125。最后,SiN层434对应于图1中的硬掩膜129。
现在参考视图406。在1/4间隙pMOS区域412的顶上是界面层420和氧化铪层422;TiN层424-2、TaAlN-T2层428、TiN层424-3、TaAlN-T3层430、以及钨层432。最后,注意SiN(硬掩膜)层434。
现在参考视图408。在中间间隙pMOS区域414的顶上是界面层420和氧化铪层422;TiN层424-1、TaAlN-T1层426、TiN层424-2、TaAlN-T2层428、TiN层424-3、TaAlN-T3层430、以及钨层432。最后,注意SiN(硬掩膜)层434。
图3-10示出了制造图1和2的晶体管时的示例性步骤。在图3中,在所有器件上沉积栅极电介质。注意IL(界面层)420和氧化铪(高K电介质)422。氧化铪是优选的但非限制性的实例;备选方案包括介电常数大于3.9的任何适当的材料,包括诸如氧化锆、氧化镧或氧化钛的材料,这取决 于半导体的类型。
在图4中,在所有器件上沉积FMG叠层。注意TiN层424-1和TaAlN-T1层426。图4的叠层具有适合于中间间隙器件414的特性。
在图5中,进行光刻以打开pFET栅极叠层。注意可溶于显影剂的底部抗反射涂层(DBARC)501以及光致抗蚀剂503。在505示出了构图以打开pFET栅极叠层。
在图6中,蚀刻pFET器件上的金属,如607所示,并且该蚀刻在对于抗蚀剂有选择性的栅极电介质上停止;然后剥离抗蚀剂。
在图7中,为PMOS器件沉积接下来的材料。特别地,直接在区域412之上的pFET栅极电介质上沉积第二FMG叠层。
在图8中,进行光刻以打开nFET栅极叠层。注意可溶于显影剂的底部抗反射涂层(DBARC)801以及光致抗蚀剂803。在805示出了构图以打开pFET栅极叠层。
在图9中,蚀刻nFET器件上的金属,如807所示,并且该蚀刻在对于抗蚀剂有选择性的栅极电介质上停止;然后剥离抗蚀剂。
在图10中,在区域410之上沉积用于nMOS的第三FMG叠层。第三FMG叠层直接在nFET栅极电介质上。因此,图10示出了钨栅极432和栅极硬掩膜(氮化物)434的沉积。该步骤产生了图2中的402所示的最终结构,其中在最终产品中所有金属层被SiN密封。
各种备选实施例是可能的。例如,一些实施例使用盖层与FMG叠层中的金属厚度相结合来调制Vt。例如,在图4中,盖层可以被添加在层422与424-1之间;在图7中,盖层可以被添加在层422与424-2之间;并且在图10中,盖层可以被添加在层422与424-3之间。在下面的段落中提供盖层的例子。
盖层可以用来提供另外的nFET和pFET移动(shift),这取决于所采用的具体盖层。盖层的选择取决于相邻物。通常,如果与NFET相邻,盖层应当使用IIA和IIB族元素(例如氧化镧、氧化镁或氧化铍);如果与PFET相邻,盖层应当使用包含Al、Ge或Ti的材料(例如,氧化铝、 氧化钛)。但是,注意,这些应用会降低Vt。在一些情况下,可能期望提高Vt,在这种情况下,可以在NFET上采用PFET盖层。不同类型的盖层可以称为功函数降低盖层和功函数提高盖层。一般而言,盖层类似于能够用于调整Vt的“旋钮”。再次参考图2,区域404、406、408代表用于1/4间隙nMOS、1/4间隙pMOS和中间间隙pMOS的叠层。然而,这用于期望降低Vt的情况。如果期望提高Vt(HVT),所述应用可以被切换,并且叠层404可以用于HVT pMOS,叠层406可用于HVT nMOS。中间间隙叠层实质上两种情况都一样,正如记号“中间间隙pMOS”下的记号“中间间隙nMOS”所指示的。
考虑至此的讨论,可以理解,在一般意义上,根据本发明的一方面的示例性方法包括提供衬底112的步骤,该衬底112上形成有第一区域412和与第一区域互补的类型的第二区域410。另外的步骤包括在衬底之上沉积栅极电介质422;以及在栅极电介质之上沉积第一全金属栅极叠层424-1、426。可以理解,词语“第一”、“第二”、“第三”等等是为了方便,例如在权利要求书或说明书的一部分中标记为“第一”的区域或晶体管可以在权利要求书或说明书的另一部分中被称为“第二”。此外,术语“栅极叠层”可以在说明书或权利要求书中用来表示完成的栅极叠层或者在制造过程期间栅极叠层的中间部分。
另一步骤包括去除第一区域之上的第一全金属栅极叠层,如505、607所示,以产生例如如图6中所见的所得到的结构。另外的步骤包括与第一区域之上的栅极电介质相接触地在所得到的结构之上沉积第二全金属栅极叠层424-2、428;并且例如用钨和SiN432、434密封第一和第二全金属栅极叠层。
在一些情况下,如图6中所见的所得到的结构例如是第一所得到的结构,并且在衬底上已经形成有第三区域414。这种情况下另外的步骤可以包括例如:去除第二区域之上的第二全金属栅极叠层,如在805、807所见,以便产生例如在图9中所见的第二所得到的结构;与第二区域之上的栅极电介质相接触地在第二所得到的结构之上沉积第三全金属栅极叠层424-3、 430;以及例如用钨和SiN432、434密封第三全金属栅极叠层。
如图1中最佳地可见,所述密封步骤产生包围第一全金属栅极叠层的第一密封物和包围第二全金属栅极叠层的第二密封物(见124、129)。另外的步骤可以包括在第一和第二密封物之间形成硅化的接触;以及形成从所述硅化的接触凸出的自对准的接触130。
如所述的,可以在栅极电介质422与第一、第二和或第三全金属栅极叠层之间(例如,在栅极电介质422与层424-1、424-2和/或424-3之间)形成盖层。
如所述的,在一个或多个实施例中,第一和第二全金属栅极叠层的金属厚度被独立地调整以调制阈值电压(这也可以结合一个或多个盖层的使用实现)。
如所述的,在期望降低n型晶体管的阈值电压或者提高p型晶体管的阈值电压的情况下,帽层可以由栅极电介质之上的氧化铪、氧化镁和氧化铍中的至少一种形成;相反,在期望提高n型晶体管的阈值电压或者降低p型晶体管的阈值电压的情况下,帽层可以由栅极电介质之上的氧化铝和氧化钛中的至少一种形成。
在另一方面中,示例性电路结构包括其上形成有第一晶体管和第二晶体管的衬底112,第一晶体管具有源极、漏极和沟道113,第二晶体管具有源极、漏极和沟道113并且是与第一晶体管(例如,p型412)互补的类型(例如,n型410)。还包括形成在第一晶体管的沟道之上的第一全金属栅极叠层和形成在第二晶体管的沟道之上的第二全金属栅极叠层(总体上,见图1中的栅极叠层127以及图2中的示例性的不同类型的栅极叠层)。第一密封物包围第一全金属栅极叠层,并且第二密封物包围第二全金属栅极叠层(见例如图1中的元件124、129)。硅化的接触119位于第一和第二密封物之间;并且自对准的接触130从所述硅化的接触凸出。
第一全金属栅极叠层由将第一晶体管调制到第一阈值电压的材料形成,并且第二全金属栅极叠层由将第二晶体管调制到不同于第一阈值电压的第二阈值电压的材料形成。
可选地,在衬底上也形成具有源极、漏极和沟道的第三晶体管;第三全金属栅极叠层形成在第三晶体管的沟道之上;第三密封物包围第三全金属栅极叠层;另一硅化的接触位于第二与第三密封物之间;并且另一自对准的接触从所述另一硅化的接触凸出。总体上见图1,并且也见图2中的三个不同区域和三个不同栅极叠层。
第三全金属栅极叠层由将第三晶体管调制到不同于所述第一和第二阈值电压的第三阈值电压的材料形成。
再次地,可以将盖层和栅极电介质设置在晶体管的沟道与对应的全金属栅极叠层之间;所述盖层与所述第一全金属栅极叠层紧邻。
上文中描述的(一种或多种)方法用于集成电路芯片制造。制造者可以以原始晶片形式(即,作为具有多个未封装芯片的单晶片)、作为裸小片或以封装的形式分发所得到的集成电路芯片。在后者的情况中,以单芯片封装(例如,引线固定到母板的塑料载体或其他更高级别的载体)或多芯片封装(例如,具有一个或两个表面互连或掩埋互连的陶瓷载体)来安装芯片。在任何情况下,所述芯片然后都作为(a)中间产品(如母板)或(b)最终产品的一部分与其他芯片、分离电路元件和/或其他信号处理装置集成。最终产品可以是任何包括集成电路芯片的产品,范围从玩具和其他低端应用到具有显示器、键盘或其他输入设备及中央处理器的高级计算机产品。
本文中所用的术语,仅仅是为了描述特定的实施例,而不意图限定本发明。本文中所用的单数形式的“一”和“该”,旨在也包括复数形式,除非上下文中明确地另行指出。还要知道,“包含”一词在本说明书中使用时,说明存在所指出的特征、整体、步骤、操作、单元和/或组件,但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元和/或组件,以及/或者它们的组合。
下面在权利要求中的所有装置或步骤加功能要素的对应结构、材料、动作和等价物旨在包括用于与具体地要求保护的其他要求保护的要素组合地执行功能的任何结构、材料或动作。本发明的说明书是为了示例和说明 的目的而给出的,而不旨在以所公开的形式穷举或限制本发明。只要不脱离本发明的范围和精神,多种修改和变化对于本领域的普通技术人员而言是显而易见的。为了最好地解释本发明的原理和实际应用,且为了使本领域的其他普通技术人员能够理解本发明的具有适于所预期的特定用途的各种修改的各种实施例,选择和描述了实施例。
Claims (20)
1.一种形成电路结构的方法,包括:
提供衬底,该衬底上已形成有第一区域和与所述第一区域互补类型的第二区域;
在所述衬底之上沉积栅极电介质;
在所述栅极电介质之上沉积第一全金属栅极叠层;
去除所述第一区域之上的所述第一全金属栅极叠层以产生所得到的结构;
与所述第一区域之上的所述栅极电介质相接触地在所述所得到的结构之上沉积第二全金属栅极叠层;以及
密封所述第一和第二全金属栅极叠层。
2.根据权利要求1所述的方法,其中
所述所得到的结构包括第一所得到的结构;
所述衬底上已形成有第三区域;
该方法还包括:
去除所述第二区域之上的所述第二全金属栅极叠层以产生第二所得到的结构;
与所述第二区域之上的所述栅极电介质相接触地在所述第二所得到的结构之上沉积第三全金属栅极叠层;以及
密封所述第三全金属栅极叠层。
3.根据权利要求2所述的方法,其中所述密封步骤产生包围所述第一全金属栅极叠层的第一密封物和包围所述第二全金属栅极叠层的第二密封物,
该方法还包括:
在所述第一和第二密封物之间形成硅化的接触;以及
形成从所述硅化的接触凸出的自对准的接触。
4.根据权利要求3所述的方法,还包括在所述栅极电介质与所述第一全金属栅极叠层之间形成盖层。
5.根据权利要求3所述的方法,还包括在所述栅极电介质与所述第二全金属栅极叠层之间形成盖层。
6.根据权利要求3所述的方法,还包括在所述栅极电介质与所述第三全金属栅极叠层之间形成盖层。
7.根据权利要求3所述的方法,还包括独立地调整所述第一和第二全金属栅极叠层的金属厚度以调制阈值电压。
8.根据权利要求3所述的方法,其中所述第二区域包括n型区域,该方法还包括:在所述第二区域中在所述栅极电介质之上形成包含氧化镧、氧化镁和氧化铍中的至少一种的盖层以降低阈值电压。
9.根据权利要求3所述的方法,其中所述第二区域包括n型区域,该方法还包括:在所述第二区域中在所述栅极电介质之上形成包含氧化铝和氧化钛中的至少一种的盖层以提高阈值电压。
10.根据权利要求3所述的方法,其中所述第一区域包括p型区域,该方法还包括:在所述第一区域中在所述栅极电介质之上形成包含氧化铝和氧化钛中的至少一种的盖层以降低阈值电压。
11.根据权利要求3所述的方法,其中所述第一区域包括p型区域,该方法还包括:在所述第一区域中在所述栅极电介质之上形成包含氧化镧、氧化镁和氧化铍中的至少一种的盖层以提高阈值电压。
12.一种通过权利要求1所述的方法形成的电路结构,包括:
衬底,该衬底上已形成有:
第一晶体管,其具有源极、漏极和沟道;
第二晶体管,其具有源极、漏极和沟道并且是与所述第一晶体管互补的类型;
第一全金属栅极叠层,其形成在所述第一晶体管的所述沟道之上;
第二全金属栅极叠层,其形成在所述第二晶体管的所述沟道之上;
第一密封物,其包围所述第一全金属栅极叠层;
第二密封物,其包围所述第二全金属栅极叠层;
硅化的接触,其位于所述第一和第二密封物之间;以及
自对准的接触,其从所述硅化的接触凸出;
其中所述第一全金属栅极叠层由将所述第一晶体管调制到第一阈值电压的材料形成,并且所述第二全金属栅极叠层由将所述第二晶体管调制到不同于所述第一阈值电压的第二阈值电压的材料形成。
13.根据权利要求12所述的电路结构,还包括:
第三晶体管,其具有形成在所述衬底上的源极、漏极和沟道;
第三全金属栅极叠层,其形成在所述第三晶体管的所述沟道之上;
第三密封物,其包围所述第三全金属栅极叠层;
另一硅化的接触,其位于所述第二和第三密封物之间;以及
另一自对准的接触,其从所述另一硅化的接触凸出;
其中所述第三全金属栅极叠层由将所述第三晶体管调制到不同于所述第一和第二阈值电压的第三阈值电压的材料形成。
14.根据权利要求13所述的电路结构,还包括位于所述第一晶体管的所述沟道与所述第一全金属栅极叠层之间的栅极电介质和盖层,所述盖层紧邻所述第一全金属栅极叠层。
15.根据权利要求14所述的电路结构,其中所述第一晶体管包括p型晶体管,并且其中所述盖层包括氧化铝和氧化钛中的至少一种以降低所述第一晶体管的阈值电压。
16.根据权利要求14所述的电路结构,其中所述第一晶体管包括p型晶体管,并且其中所述盖层包括氧化镧、氧化镁和氧化铍中的至少一种以提高所述第一晶体管的阈值电压。
17.根据权利要求13所述的电路结构,还包括位于所述第二晶体管的所述沟道与所述第二全金属栅极叠层之间的栅极电介质和盖层,所述盖层紧邻所述第二全金属栅极叠层。
18.根据权利要求17所述的电路结构,其中所述第二晶体管包括n型晶体管,并且其中所述盖层包括氧化镧、氧化镁和氧化铍中的至少一种以降低所述第二晶体管的阈值电压。
19.根据权利要求17所述的电路结构,其中所述第二晶体管包括n型晶体管,并且其中所述盖层包括氧化铝和氧化钛中的至少一种以提高所述第二晶体管的阈值电压。
20.根据权利要求13所述的电路结构,还包括位于所述第三晶体管的所述沟道与所述第三全金属栅极叠层之间的栅极电介质和盖层,所述盖层紧邻所述第三全金属栅极叠层。
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