CN103632939A - Method for optimizing top rounded corner of power device groove - Google Patents
Method for optimizing top rounded corner of power device groove Download PDFInfo
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- CN103632939A CN103632939A CN201210289589.2A CN201210289589A CN103632939A CN 103632939 A CN103632939 A CN 103632939A CN 201210289589 A CN201210289589 A CN 201210289589A CN 103632939 A CN103632939 A CN 103632939A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 44
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000002203 pretreatment Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000010415 tropism Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 8
- 239000007789 gas Substances 0.000 abstract 1
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 21
- 210000003323 beak Anatomy 0.000 description 5
- 241000208340 Araliaceae Species 0.000 description 3
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 3
- 235000003140 Panax quinquefolius Nutrition 0.000 description 3
- 235000008434 ginseng Nutrition 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a method for optimizing a top rounded corner of a power device groove. A pad oxide layer and a silicon nitride layer are formed on a silicon substrate in turn; after the groove is formed, heat oxidation is performed on a formed device structure; the silicon nitride layer and the pad oxide layer are removed; various isotropic gases are applied to process the groove, and edge corners of the groove are rounded; a layer of sacrificial oxide layer grows on the surface of the silicon substrate and the internal surface of the groove, then the sacrificial oxide layer is removed and the edge corners of the groove are further rounded; a gate oxide layer used for isolation grows on the surface of the silicon substrate and the internal surface of the groove; gate electrode poly-silicon is deposited and back etched on the gate oxide layer of the upper end of the silicon substrate and in the groove; and an isolation layer is deposited on the upper end of the gate electrode poly-silicon which is arranged on the gate oxide layer of the upper end of the silicone substrate and arranged in the groove. Radius of curvature of the top corners of the groove can be improved so that the gate oxide layer of the device has better uniformity and reliability.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to the method for a kind of optimizing power device trenches top fillet.
Background technology
Slot type power device is because its ducting capacity is strong, and power consumption is little, little many advantages, gradually the success rate device main flow of waiting of chip area.As everyone knows, the gate insulation quality of slot type power device, particularly deep slot type power device not as planar device good.This is because the corner processing of groove is good not, causes quality of gate oxide uniformity not as planar power device.And such defect tends to cause some integrity problems of power device itself.
Due to trench etch process, often more sharp-pointed at the turning at groove top.After gate insulation layer growth finishes, also can experience some complicated thermal processs, and etching process, can make the quality of oxide layer of this part poor, easy fracture etc.By encapsulating the chip of rear test, in reliability of the gate oxide test process, due to the quality of gate oxide defect of groove top corner, can first puncture herein, affect device and use (referring to Fig. 1).In Fig. 1, by failure analysis, navigate to obtain gate oxide leakage, groove top oxide layer is too small because of radius of curvature, causes fracture, thereby brings gate oxide electric leakage or lowly puncture inefficacy.
Summary of the invention
The technical problem to be solved in the present invention is to provide the method for a kind of optimizing power device trenches top fillet, can improve the radius of curvature of groove top corner, thereby makes the gate oxide of device have better uniformity and reliability.
For solving the problems of the technologies described above, the method for optimizing power device trenches of the present invention top fillet, comprises the steps:
Step 3, remove described photoresist, and by described silicon nitride layer and cushion oxide layer as hard etching barrier layer, silicon substrate described in dry etching, forms groove;
Wherein, also comprise:
Step 4, the device architecture having formed is carried out to thermal oxidation after above-mentioned steps is processed;
Step 6, with isotropism gas, described groove is processed, by the corner cavetto of groove;
Step 7, at the surface of described silicon substrate and the inner surface of groove growth one deck sacrificial oxide layer, and then remove this sacrificial oxide layer, further by the corner cavetto of described groove;
Step 9, deposit return to carve gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove;
Step 10, the upper end deposit separator of gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove.
The another kind of technical scheme that the method for optimizing power device trenches of the present invention top fillet adopts, comprises the steps:
The first step, on silicon substrate, form successively cushion oxide layer and silicon nitride layer;
Second step, at described silicon nitride layer surface-coated photoresist, by photoetching, define with photoresist the figure of groove, adopt dry etching to carve and wear described silicon nitride layer;
The 3rd step, remove described photoresist, and the device architecture having formed after above-mentioned steps is processed is carried out to thermal oxidation;
The 4th step, using described silicon nitride layer as hard light shield, etching oxidation layer; Using described silicon nitride layer or oxide layer as hard light shield again, and silicon substrate described in dry etching, forms groove;
The 5th step, remove described silicon nitride layer and oxide layer; Described groove is waited to tropism's gas etching, by the corner cavetto of described groove;
The 6th step, at the surface of described silicon substrate and the inner surface of groove growth one deck sacrificial oxide layer, and then remove this sacrificial oxide layer, further the corner cavetto of groove;
The 7th step, at the gate oxide of the surface of described silicon substrate and the inner surface of groove growth one deck isolation use;
The 8th step, deposit return to carve gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove;
The 9th step, the upper end deposit separator of gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove.
The present invention is by the optimization to groove processing technique, at groove top, carry out partial thermal oxidation, thereby in groove making, good processing has been carried out in groove top, the radius of curvature of groove top corner is improved, thereby improve the grid reliability of the power device of groove structure, as the test of HTGB(high temp. grate bias voltage) ability, maintain other performances of device (as puncture voltage, conducting resistance) constant simultaneously; Better solved the ubiquitous grid of the power device source electric leakage problem of groove structure.
The present invention can be for trench gate IGBT(insulated gate bipolar transistor), the groove of the slot type power device such as MOS (metal-oxide layer-semiconductor) processes.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the gate oxide leakage slice map of failure analysis location;
Fig. 2 has applied ambipolar "off" transistor structural representation of insulated trench grid of the present invention;
Fig. 3 is traditional ambipolar "off" transistor structural representation of insulated trench grid;
Fig. 4 is the silicon chip schematic diagram of preparing;
Fig. 5 is deposit cushion oxide layer schematic diagram;
Fig. 6 is deposit silicon nitride layer schematic diagram;
Fig. 7 is the pattern schematic diagram that defines groove;
Fig. 8 forms groove schematic diagram;
Fig. 9 is the schematic diagram carrying out after thermal oxidation;
Figure 10 is the schematic diagram of removing silicon nitride layer and cushion oxide layer;
Figure 11 is the schematic diagram after groove being processed with isotropism gas;
Figure 12 is the schematic diagram of growth one deck sacrificial oxide layer;
Figure 13 is the schematic diagram of removing after sacrificial oxide layer;
Figure 14 is the schematic diagram after the gate oxide of growth isolation use;
Figure 15 is the schematic diagram after deposit gate electrode polysilicon;
Figure 16 is back to carve the schematic diagram after gate electrode polysilicon;
Figure 17 is the schematic diagram after deposit separator;
Figure 18 is the pictorial diagram that defines with photoresist groove;
Figure 19 removes photoresist schematic diagram;
Figure 20 is the schematic diagram carrying out after thermal oxidation;
Figure 21 is the schematic diagram after etching oxidation layer;
Figure 22 is the schematic diagram forming after groove;
Figure 23 is the schematic diagram of removing after silicon nitride layer and oxide layer.
Embodiment
Embodiment mono-
The method of described optimizing power device trenches top fillet comprises the steps:
Step 3, shown in Figure 6 after step 2 completes, adopts the silicon nitride layer 3 of chemical vapor deposition (CVD) one deck suitable thickness in described cushion oxide layer 2, and the thickness of this silicon nitride layer 3 can be
arrive
etc., specifically by required beak pattern, do not determined.
Step 4, shown in Figure 7 applies photoresist 4 on described silicon nitride 3 surfaces, defines the pattern of groove 5 by one deck light shield, adopts the method for dry etching, silicon nitride layer 3 and the cushion oxide layer 2 on silicon chip 1 surface described in etching.
Step 6, shown in Figure 9, carries out thermal oxidation to the device architecture having formed after above-mentioned steps is processed, and mode of oxidizing can be dry method, can be also wet method, can also be the combination that dry method adds wet method, and oxidizing temperature and time determine according to the design of device.Through this step process, form oxide layer beak region 6-1 and sacrificial oxide layer 6-2.
Step 7, shown in Figure 10, removes described silicon nitride 3 and cushion oxide layer 2.
Step 9, shown in Figure 12, at the surface of described silicon chip 1 and the inner surface of groove 5 growth one deck sacrificial oxide layer, and then removes this sacrificial oxide layer, further the corner cavetto of groove 5, as shown in figure 13.
Step 10, shown in Figure 14, at the gate oxide 7 of the surface of described silicon chip 1 and the inner surface of groove 5 growth one deck isolation use.
Step 12, shown in Figure 17, on the gate oxide 7 of described silicon chip 1 upper end and the upper end deposit separator 9 of the interior gate electrode polysilicon 8 of groove 5, then makes electrode.
Embodiment bis-
The method of described optimizing power device trenches top fillet comprises the steps:
Step 3, shown in Figure 6, the silicon nitride layer 3 of deposit one deck suitable thickness in described cushion oxide layer 2, the thickness of this silicon nitride layer 3 can be
arrive
etc., specifically by required beak pattern, do not determined.
Step 4, shown in Figure 18 applies photoresist 4 on the surface of described silicon nitride layer 3, by the photoetching figure of 4 definition grooves 5 with photoresist, adopts dry etching to carve and wears described silicon nitride layer 3.
Step 6, shown in Figure 20, carries out thermal oxidation to the device architecture having formed after above-mentioned steps is processed, and mode of oxidizing can be dry method, can be also wet method, can also be the combination that dry method adds wet method, and oxidizing temperature and time determine according to the design of device.
Step 7, ginseng as shown in Figure 21, are usingd described silicon nitride layer 3 as hard light shield, etching oxidation layer 2.
Step 9, ginseng as shown in Figure 23, are removed described silicon nitride and are surveyed layer 3 and oxide layer 2.
Step 10, shown in Figure 11, carries out isotropism gas etching to described groove 5, by the corner cavetto of groove 5.
Step 12, shown in Figure 14, at the gate oxide 7 of the surface of described silicon chip 1 and the inner surface of groove 5 growth one deck isolation use.
Ambipolar the "off" transistor structure of insulated trench grid that adopts said method to make is shown in Figure 2, and Fig. 3 is traditional ambipolar "off" transistor structure of insulated trench grid.Wherein, 11 is P type doped region, and 12 is N-type doped region, 13 is gate oxide, the gate oxide corner region of 13a for adopting method of the present invention to form, and 13b is traditional gate oxide corner region, 14 is spacer medium layer, and 15 is polygate electrodes, and 16 is electric field cutoff layer, 17 is P type doped region, 18a is collector electrode metal electrode, and 18b is emitter metal electrode, and E is emitter, C is collector electrode, and G is gate electrode.By the gate oxide corner region 13a through optimizing that adopts method of the present invention to form in comparison diagram 2, and traditional without the gate oxide corner region of optimizing in Fig. 3, the gate oxide stability that can visually see, has very large advantage.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.For example in some device design aspect contents, can intert in groove forming process described in the invention; as long as groove is made partly identical with the present invention; or without departing from the principles of the present invention, the distortion of doing and improvement, all should be considered as protection scope of the present invention.
Claims (10)
1. a method for optimizing power device trenches top fillet, comprises the steps:
Step 1, on silicon substrate, form successively cushion oxide layer and silicon nitride layer;
Step 2, at described silicon nitride layer surface-coated photoresist, by one deck light shield, define the pattern of groove, adopt the method for dry etching, silicon nitride layer and cushion oxide layer described in etching;
Step 3, remove described photoresist, and by described silicon nitride layer and cushion oxide layer as hard etching barrier layer, silicon substrate described in dry etching, forms groove; It is characterized in that, also comprise:
Step 4, the device architecture having formed is carried out to thermal oxidation after above-mentioned steps is processed;
Step 5, remove described silicon nitride layer and cushion oxide layer;
Step 6, with isotropism gas, described groove is processed, by the corner cavetto of groove;
Step 7, at the surface of described silicon substrate and the inner surface of groove growth one deck sacrificial oxide layer, and then remove this sacrificial oxide layer, further by the corner cavetto of described groove;
Step 8, at the gate oxide of the surface of described silicon substrate and the inner surface of groove growth one deck isolation use;
Step 9, deposit return to carve gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove;
Step 10, the upper end deposit separator of gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove.
2. the method for claim 1, is characterized in that: the thickness of described silicon substrate, resistivity and pre-treatment are determined by device property and designing requirement; Described pre-treatment comprises the processing that the own design of device in being produced on of terminal is wanted.
3. the method for claim 1, is characterized in that: described cushion oxide layer adopts chemical vapor deposition CVD or heat growth to form, and the thickness of this cushion oxide layer is
4. the method for claim 1, is characterized in that: described silicon nitride layer adopts chemical vapor deposition CVD to form, and the thickness of this silicon nitride layer is
5. the method for claim 1, is characterized in that: described thermal oxidation mode can be dry method, can be also wet method, can also be the combination that dry method adds wet method, and oxidizing temperature and time determine according to the design of device.
6. a method for optimizing power device trenches top fillet, comprises the steps:
The first step, on silicon substrate, form successively cushion oxide layer and silicon nitride layer;
Second step, at described silicon nitride layer surface-coated photoresist, by photoetching, define with photoresist the figure of groove, adopt dry etching to carve and wear described silicon nitride layer; It is characterized in that, also comprise:
The 3rd step, remove described photoresist, and the device architecture having formed after above-mentioned steps is processed is carried out to thermal oxidation;
The 4th step, using described silicon nitride layer as hard light shield, etching oxidation layer; Using described silicon nitride layer or oxide layer as hard light shield again, and silicon substrate described in dry etching, forms groove;
The 5th step, remove described silicon nitride layer and oxide layer; Described groove is waited to tropism's gas etching, by the corner cavetto of described groove;
The 6th step, at the surface of described silicon substrate and the inner surface of groove growth one deck sacrificial oxide layer, and then remove this sacrificial oxide layer, further the corner cavetto of groove;
The 7th step, at the gate oxide of the surface of described silicon substrate and the inner surface of groove growth one deck isolation use;
The 8th step, deposit return to carve gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove;
The 9th step, the upper end deposit separator of gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove.
7. method as claimed in claim 6, is characterized in that: the thickness of described silicon substrate, resistivity and pre-treatment are determined by device property and designing requirement; Described pre-treatment comprises the processing that the own design of device in being produced on of terminal is wanted.
8. method as claimed in claim 6, is characterized in that: described cushion oxide layer adopts chemical vapor deposition CVD or heat growth to form, and the thickness of this cushion oxide layer is
9. method as claimed in claim 6, is characterized in that: described silicon nitride layer adopts chemical vapor deposition CVD to form, and the thickness of this silicon nitride layer is
10. method as claimed in claim 6, is characterized in that: described thermal oxidation mode can be dry method, can be also wet method, can also be the combination that dry method adds wet method, and oxidizing temperature and time determine according to the design of device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210289589.2A CN103632939A (en) | 2012-08-15 | 2012-08-15 | Method for optimizing top rounded corner of power device groove |
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| CN201210289589.2A CN103632939A (en) | 2012-08-15 | 2012-08-15 | Method for optimizing top rounded corner of power device groove |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616982A (en) * | 2015-01-13 | 2015-05-13 | 株洲南车时代电气股份有限公司 | Method for etching trench gate |
| CN105428407A (en) * | 2015-11-16 | 2016-03-23 | 株洲南车时代电气股份有限公司 | IGBT device and forming method therefor |
| CN107994076A (en) * | 2016-10-26 | 2018-05-04 | 深圳尚阳通科技有限公司 | The manufacture method of groove grid super node device |
| CN110137082A (en) * | 2018-02-09 | 2019-08-16 | 天津环鑫科技发展有限公司 | A kind of optimization method of power device groove pattern |
| CN112447507A (en) * | 2019-08-30 | 2021-03-05 | 株洲中车时代半导体有限公司 | GOI test sample wafer manufacturing method for improving trench gate breakdown characteristics |
| CN112802742A (en) * | 2021-03-24 | 2021-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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| US20010006836A1 (en) * | 1994-02-04 | 2001-07-05 | Katsumi Nakamura | Method of forming a trench mos gate on a power semiconductor device |
| CN101320689A (en) * | 2007-06-07 | 2008-12-10 | 和舰科技(苏州)有限公司 | Method for forming plough groove structure of plough groove type power transistor |
| CN101621031A (en) * | 2008-06-20 | 2010-01-06 | 飞兆半导体公司 | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
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2012
- 2012-08-15 CN CN201210289589.2A patent/CN103632939A/en active Pending
Patent Citations (3)
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| US20010006836A1 (en) * | 1994-02-04 | 2001-07-05 | Katsumi Nakamura | Method of forming a trench mos gate on a power semiconductor device |
| CN101320689A (en) * | 2007-06-07 | 2008-12-10 | 和舰科技(苏州)有限公司 | Method for forming plough groove structure of plough groove type power transistor |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616982A (en) * | 2015-01-13 | 2015-05-13 | 株洲南车时代电气股份有限公司 | Method for etching trench gate |
| CN105428407A (en) * | 2015-11-16 | 2016-03-23 | 株洲南车时代电气股份有限公司 | IGBT device and forming method therefor |
| CN105428407B (en) * | 2015-11-16 | 2018-07-13 | 株洲南车时代电气股份有限公司 | A kind of IGBT device and forming method thereof |
| CN107994076A (en) * | 2016-10-26 | 2018-05-04 | 深圳尚阳通科技有限公司 | The manufacture method of groove grid super node device |
| CN110137082A (en) * | 2018-02-09 | 2019-08-16 | 天津环鑫科技发展有限公司 | A kind of optimization method of power device groove pattern |
| CN112447507A (en) * | 2019-08-30 | 2021-03-05 | 株洲中车时代半导体有限公司 | GOI test sample wafer manufacturing method for improving trench gate breakdown characteristics |
| CN112802742A (en) * | 2021-03-24 | 2021-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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Application publication date: 20140312 |