CN103617772B - Display panel and method of testing thereof - Google Patents
Display panel and method of testing thereof Download PDFInfo
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- CN103617772B CN103617772B CN201310559525.4A CN201310559525A CN103617772B CN 103617772 B CN103617772 B CN 103617772B CN 201310559525 A CN201310559525 A CN 201310559525A CN 103617772 B CN103617772 B CN 103617772B
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Abstract
A kind of display panel and method of testing thereof, display panel has viewing area and perimeter circuit district, and display panel comprises active assembly array substrate, subtend substrate and the display dielectric layer between active assembly array substrate and subtend substrate.Active assembly array substrate comprises multi-strip scanning line and a plurality of data lines, multiple pixel cell, shared electrode layer and many p-wires.Sweep trace and data line are crisscross arranged in viewing area, define multiple pixel region.Multiple pixel cell is arranged in pixel region respectively, and each pixel cell is electrically connected with corresponding sweep trace and data line.Shared electrode layer is cover data line at least.P-wire is arranged in viewing area, and each p-wire at least overlaps with data line, and between shared electrode layer and data line.
Description
Technical field
The invention relates to a kind of panel and method of testing thereof, and relate to a kind of display panel and method of testing thereof especially.
Background technology
Generally speaking, display panel is made up of active assembly array substrate, subtend substrate and the display dielectric layer be configured between this two substrates.Wherein, after completing the processing procedure of active assembly array substrate, usually electrical detection can be carried out, to guarantee that active assembly array does not have an impact the defect of display quality in processing procedure process.Further, when detecting the defect that can affect display quality, further can find out the position of generation defect and repairing, so can improve the yield of processing procedure.
But, when the data line in active assembly array substrate and shared electrode are short-circuited situation, many online data are distributed in because shared electrode is electrical connected with array way usually, therefore cannot differentiate that the position that defect occurs is to repair from testing result, and increase the cost of deficient manufacturing procedure loss.Therefore, how under data line and shared electrode are short-circuited situation, interpretation that can be correct goes out to occur the position of defect, is problem urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of display panel and method of testing thereof, when data line and shared short circuit between electrodes, the sweep trace coordinate be short-circuited corresponding to position can be detected.
Display panel of the present invention, has viewing area and perimeter circuit district, and display panel comprises active assembly array substrate, subtend substrate and the display dielectric layer between active assembly array substrate and subtend substrate.Active assembly array substrate comprises multi-strip scanning line and a plurality of data lines, multiple pixel cell, shared electrode layer and many p-wires.Sweep trace and data line are crisscross arranged in viewing area, define multiple pixel region.Multiple pixel cell is arranged in pixel region respectively, and each pixel cell is electrically connected with corresponding sweep trace and data line.Shared electrode layer is cover data line at least.P-wire is arranged in viewing area, and each p-wire at least overlaps with data line, and between shared electrode layer and data line.
The method of testing of display panel of the present invention, the method comprises provides display panel as above.Input test signal is to one of them of p-wire.Test result signal is received from the data line of the p-wire corresponded to wherein, wherein, when test result signal is activation, judge that the data line corresponding to a p-wire is wherein electrically connected with shared electrode layer and the p-wire be positioned between the two, and then learn the position that data line and shared electrode layer corresponding to a p-wire are wherein short-circuited.
Based on above-mentioned, because the present invention arranges p-wire between shared electrode layer and data line.When data line and shared short circuit between electrodes, can by input test signal to one of them of p-wire, and receive test result signal from the data line of corresponding p-wire simultaneously, wherein, when test result signal is activation, then can judge that the data line of corresponding p-wire and shared electrode layer and the p-wire be positioned between the two are electrically connected, and by the position that the data line and shared electrode layer of learning p-wire are short-circuited, and then determine the sweep trace coordinate be short-circuited corresponding to position.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the upper schematic diagram of display panel according to an embodiment of the invention;
Fig. 2 is the diagrammatic cross-section of Fig. 1 along profile line I-I ';
Fig. 3 is the upper schematic diagram that is short-circuited of display panel data line and shared electrode according to an embodiment of the invention;
The diagrammatic cross-section of profile line II-II ' of Fig. 4 to be Fig. 3 along data line and shared electrode be short-circuited position.
[primary clustering symbol description]
D1: first direction
D2: second direction
I-I ': profile line position
II-II ': the profile line position be short-circuited
U: pixel region
10: display panel
100: active assembly array substrate
102: viewing area
110: substrate
112: signal bonding pad
112a: the first signal bonding pad
112b: secondary signal connection pad
120a, 120b, 120c, 120d: sweep trace
130a, 130b, 130c, 130d: data line
140: pixel cell
140a: driving component
140b: pixel electrode
150: shared electrode layer
160: p-wire
160a: connecting portion
160b: finger section
160c: test connection pad
170: gate insulation layer
180: the first insulation courses
190: the second insulation courses
200: subtend substrate
300: display dielectric layer.
Embodiment
Fig. 1 is the upper schematic diagram of display panel according to an embodiment of the invention.Fig. 2 is the diagrammatic cross-section of Fig. 1 along profile line I-I '.Referring to Fig. 1 and Fig. 2, in the present embodiment, display panel 10 has viewing area 102 and perimeter circuit district 104, and comprises active assembly array substrate 100, subtend substrate 200 and the display dielectric layer between active assembly array substrate 100 and subtend substrate 200 300.
Active assembly array substrate 100 comprises substrate 110, multi-strip scanning line 120a to 120d, a plurality of data lines 130a to 130d, multiple pixel cell 140, shared electrode layer 150 and many p-wires 160.
Specifically, in the viewing area 102 on active assembly array substrate 100, each sweep trace 120a to 120d is parallel to each other and extend along first direction D1, and each data line 130a to 130d is parallel to each other and extend along second direction D2.First direction D1 is different from second direction D2, therefore sweep trace 120a to 120d and data line 130a to 130d are interlaced with each other, and interlaced with each other by sweep trace 120a to 120d and data line 130a to 130d, viewing area 102 can be defined as multiple pixel region U.In pixel region U, correspondence is provided with a pixel cell 140 respectively.Pixel cell 140 is at least electrically connected with wherein one of sweep trace 120a to 120d and a row culture wherein of data line 130a to 130d.Specifically, the pixel electrode 140b that pixel cell 140 can comprise driving component 140a and be electrically connected with driving component 140a, wherein driving component 140a is electrically connected with above-mentioned corresponding sweep trace and data line.The structure of above-mentioned pixel cell 140 is only and illustrates, the present invention does not limit quantity and the shape of driving component 140a and pixel electrode 140b in pixel cell 140, nor limits the quantity of sweep trace and the data line be electrically connected with pixel cell 140.
Shared electrode layer 150 to be configured in all pixel region U and to be patterned.Be arranged in each pixel region U shared electrode layer 150 its be such as have multiple opening with expose driving component 140a and part pixel electrode 140b.Because the shared electrode layer 150 being arranged in adjacent pixel regions U is connected to each other, therefore at least have the shared electrode layer 150 of part and overlap with the sweep trace 120a to 120d of the data line 130a to 130d of part and part.In the present embodiment, shared electrode layer 150 and pixel electrode 140b are all configured on same substrate 110, and therefore display panel 10 is such as marginal field suitching type (FringeFieldSwitching, FFS) display panel.
P-wire 160 at least overlaps with data line 130a to 130d, and between shared electrode layer 150 and data line 130a to 130d.Specifically, p-wire 160 comprises multiple connecting portion 160a and is connected to multiple finger section 160b of connecting portion 160a, as shown in fig. 1.Connecting portion 160a is arranged in parallel with each other and extends along first direction D1.These connecting portions 160a arranges along second direction D2 to be roughly covered with whole viewing area 102, and is arranged in parallel with each sweep trace 120a to 120d.
In the crossover place that connecting portion 160a and each data line 130a to 130d projects at grade, p-wire 160 also extends along second direction D2 towards adjacent connecting portion 160a from connecting portion 160a and forms finger section 160b.Each finger section 160b at least with the overlapping of the wherein part of a data line 130a to 130d.In other words, the finger section 160b of p-wire 160, between data line 130c and shared electrode layer 150, overlaps with data line 130a to 130d to make the shared electrode layer 150 of at least part.
In the present embodiment, finger section 160b is connected with wherein a junction 160a and extends toward next connecting portion 160a and be not attached to next connecting portion 160a, and therefore the length of each finger section 160b is about in fact the length of a pixel cell 140.With another viewpoint, these finger section 160b of same p-wire and a wherein pixel cell arranged 140 are alternately arranged, and the connecting portion 160a be connected with these finger section 160b is disposed adjacent with the sweep trace 120a to 120d being electrically connected to this row pixel cell 140 above-mentioned, therefore, the coordinate of the corresponding wherein sweep trace 120a to 120b of coordinate meeting of each p-wire 160.
Specifically, Fig. 2 is the diagrammatic cross-section of Fig. 1 along profile line I-I '.Please refer to Fig. 2, be sequentially configured with gate insulation layer 170, data line 130c, the first insulation course 180, the finger section 160b of p-wire 160, the second insulation course 190 and shared electrode layer 150 in substrate 110.The finger section 160b of p-wire 160 between data line 130c and shared electrode layer 150, and accompanies between finger section 160b and data line 130c between the first insulation course 180, finger section 160b and shared electrode layer 150 and accompanies the second insulation course 190.Therefore, in the ordinary course of things, finger section 160b, data line 130c and shared electrode layer 150 is electrical independently state each other.
In the present embodiment, the perimeter circuit district 104 on active assembly array substrate 100 can divide into driven unit setting area 104a and test suite setting area 104b.Driven unit setting area 104a and test suite setting area 104b lays respectively at the relative both sides of viewing area 102, but is not limited thereto, and also can be positioned at phase the same side of viewing area 102.Below for convenience of describing, the situation only laying respectively at the relative both sides of viewing area 102 for driven unit setting area 104a and test suite setting area 104b is illustrated.
As shown in Figure 1, multiple test connection pad 160c is configured with in the 104b of test suite setting area.Each test connection pad 160c is electrically connected with corresponding one of them connecting portion 160a respectively.At this, because each test connection pad 160c all has identical function, therefore represent with same-sign 160c.When general non-detection, p-wire 160 is electrical floating state, without being connected to other signal input apparatus, but being not limited thereto, also p-wire 160 can being designed to have fixed signal when non-detection.Below for convenience of describing, will be only that electrically floating situation illustrates for p-wire 160.
Perimeter circuit district 104 on active assembly array substrate 100 is also configured with multiple signal bonding pad 112.Signal bonding pad 112 can divide into the first signal bonding pad 112a of serial connection odd number bar data line 130a and 130c, and the secondary signal connection pad 112b of serial connection even number bar data line 130b and 130d, but the series-mounting of signal bonding pad and quantity are not limited thereto.As shown in Figure 1, signal bonding pad 112 and data line 130a to 130d can be different rete, and in order to cross-over connection demand to each other, and signal bonding pad 112 is electrically connected with corresponding data line 130a to 130d respectively.
After active assembly array substrate 100 completes, usually can start to carry out electrical detection program, the active assembly array substrate 100 according to Fig. 1 illustrates by detection method.Please refer to Fig. 1 and Fig. 2, test signal can be inputted respectively each test connection pad 160c, and detected by signal bonding pad 112 and whether have signal to export, but the transmission method of test signal is not limited thereto.Also can be that test signal is inputted each signal bonding pad 112 respectively, and whether have signal to export by each test connection pad 160c detection.For convenience of describing, below with by test signal by inputting each test connection pad 160c, and to be illustrated by the mode of signal bonding pad 112 Received signal strength.
For example, Fig. 3 is in the display panel according to the embodiment of the present invention, the upper schematic diagram that data line and shared electrode are short-circuited.Fig. 4 is the diagrammatic cross-section of Fig. 3 along profile line II-II '.Referring to Fig. 3 and Fig. 4, be short-circuited between data line 130a and shared electrode layer 150, the position of its location of short circuit II-II ' as shown in Figure 3.Now, be short-circuited between data line 130a and shared electrode layer 150, that is the insulation course 180 and 190 be sandwiched between data line 130a and shared electrode layer 150 is destroyed, data line 130a and shared electrode layer 150 are electrical connected.And the finger section 160b being configured at the p-wire 160 between data line 130a and shared electrode layer 150 is also electrical connected with data line 130a and shared electrode layer 150.
To test connection pad 160c sequentially input test signal, and receive detection signal in signal bonding pad 112 simultaneously.For example, when corresponding to sweep trace 120a to Article 1 p-wire 160() input test signal time, test result signal can be received by data line 130a, now test result signal is not activation (such as not receiving current signal from the first signal bonding pad 112a of correspondence), therefore can learn the part of the data line 130a to 130d corresponding to those pixel cells 140 be connected with sweep trace 120a, there is no short-circuit conditions and occur.
When corresponding to sweep trace 120c to Article 3 p-wire 160() input test signal time, test result signal can be received by data line 130a, now test knot news signal is activation (such as receiving current signal from the first signal bonding pad 112a of correspondence), therefore can judge that the finger section 160b of Article 3 p-wire 160 and data line 130a and shared electrode layer 150 are electrical connected, therefore can learn that the coordinate of p-wire 160 of position occurs in short circuit, and and then learn the coordinate of the sweep trace 120c corresponding to it.In other words, can learn that the part of the data line 130a to 130d corresponding to those pixel cells 140 be connected with sweep trace 120c has short-circuit conditions to occur.
Then, such as can again through unit short-circuit rods (Cellshortingbar, CST) visual examination is carried out in design, can learn the coordinate of data line 130a finding short circuit, therefore the above-mentioned detection method of mat can determine the coordinate of sweep trace 120c and the data line 130a be short-circuited accurately.
In sum, on active assembly array substrate in display panel of the present invention each sweep trace corresponding pixel cell in, overlap between the locations of structures of data line and shared electrode layer and the finger section of a p-wire is set, and utilize the connecting portion of p-wire to be mutually connected in series along the direction of parallel scan lines, each p-wire is electrically connected a test connection pad respectively in non-display area, and each data line is also serially connected with signal bonding pad in non-display area.It can thus be appreciated that, when complete active assembly array complete after for carrying out electrical detection, a test signal can be inputted respectively in each test connection pad, and in signal bonding pad detect whether receive signal.Accordingly, when the data line in active assembly array substrate and shared electrode are short-circuited, the sweep trace coordinate be short-circuited can be determined accurately, can conveniently carry out repairing by this and improve the yield of processing procedure.
Claims (9)
1. a display panel, have viewing area and perimeter circuit district, this display panel comprises:
Active assembly array substrate, comprising:
Multi-strip scanning line and a plurality of data lines, be crisscross arranged to define multiple pixel region in this viewing area;
Multiple pixel cell, is arranged in those pixel regions respectively, and respectively this pixel cell is electrically connected with this corresponding sweep trace and this data line;
Shared electrode layer, at least covers those data lines; And
Many p-wires, are arranged in this viewing area, and respectively this p-wire at least overlaps with those data lines, and between this shared electrode layer and those data lines;
Subtend substrate, is arranged with this active assembly array substrate subtend; And
Display dielectric layer, is arranged between this active assembly array substrate and this subtend substrate;
Described respectively this p-wire comprises connecting portion and is connected to multiple finger section of this connecting portion, respectively this finger section and those data lines wherein one overlap.
2. display panel as claimed in claim 1, it is characterized in that, the bearing of trend of this connecting portion is parallel with the bearing of trend of this sweep trace.
3. display panel as claimed in claim 1, it is characterized in that, respectively the length of this finger section is essentially the length of a pixel cell.
4. display panel as claimed in claim 1, it is characterized in that, those p-wires are electrically floating.
5. display panel as claimed in claim 1, is characterized in that, accompany the first insulation course between those p-wires and this shared electrode layer, and accompany the second insulation course between those p-wires and those data lines.
6. display panel as claimed in claim 1, it is characterized in that, this perimeter circuit district comprises driven unit setting area and the test suite setting area of the not homonymy being positioned at this viewing area, and this display panel also comprises multiple test connection pad, be arranged at this test suite setting area, respectively this p-wire extends to this test suite setting area to be electrically connected to one of them test connection pad from this viewing area.
7. display panel as claimed in claim 1, it is characterized in that, also comprise many bus bars and multiple signal bonding pad, be arranged in this perimeter circuit district, respectively this bus bar is electrically connected to one of them signal bonding pad, and wherein those data lines are electrically connected to a wherein bus bar respectively.
8. a method of testing for display panel, is characterized in that, comprising:
There is provided display panel, have viewing area and perimeter circuit district, this display panel comprises:
Active assembly array substrate, comprising:
Multi-strip scanning line and a plurality of data lines, be crisscross arranged to define multiple pixel region in this viewing area;
Multiple pixel cell, is arranged in those pixel regions respectively, and respectively this pixel cell is electrically connected with this corresponding sweep trace and this data line;
Shared electrode layer, at least covers those data lines; And
Many p-wires, are arranged in this viewing area, and respectively this p-wire at least overlaps with those data lines, and between this shared electrode layer and those data lines;
Subtend substrate, is arranged with this active assembly array substrate subtend; And
Display dielectric layer, is arranged between this active assembly array substrate and this subtend substrate;
Input test signal is to one of them of those p-wires;
Test result signal is received from this data line corresponding to this p-wire wherein, wherein, when this test result signal is activation, judge to correspond to this data line of this p-wire wherein and this shared electrode layer and this p-wire be positioned between the two to be electrically connected, and then learn the position that this data line and this shared electrode layer corresponding to this p-wire are wherein short-circuited.
9. the method for testing of display panel as claimed in claim 8, it is characterized in that, respectively this p-wire comprises connecting portion and is connected to multiple finger section of this connecting portion, respectively wherein overlapping of this finger section and those data lines, and the bearing of trend of this connecting portion is parallel with the bearing of trend of this sweep trace, the method for testing of described display panel also comprises:
Input this test signal this connecting portion to this p-wire wherein;
This test result signal is received from this data line corresponding to this p-wire wherein, wherein, when this test result signal is activation, this data line judging to correspond to this p-wire wherein and this shared electrode layer and this data line of this p-wire be positioned between the two are connected, and then learn the position that this data line and this shared electrode layer corresponding to this p-wire are wherein short-circuited.
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Families Citing this family (6)
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| CN104464587B (en) * | 2014-12-31 | 2017-04-19 | 深圳市华星光电技术有限公司 | Array substrate and detection circuit thereof |
| CN105425096B (en) * | 2015-12-16 | 2018-05-18 | 友达光电（苏州）有限公司 | display device and test method |
| CN109669094A (en) * | 2018-12-19 | 2019-04-23 | 上海帆声图像科技有限公司 | The detection device and method of signal wire in a kind of display screen |
| CN109872669A (en) * | 2019-04-19 | 2019-06-11 | 京东方科技集团股份有限公司 | Array substrate, display master blank, array substrate preparation method and test method |
| CN112669737B (en) * | 2020-12-22 | 2023-07-14 | 武汉天马微电子有限公司 | Display panel, crack detection method thereof and display device |
| CN112882263A (en) * | 2021-03-11 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246074B1 (en) * | 1998-09-30 | 2001-06-12 | Lg.Philips Lcd Co., Ltd. | Thin film transistor substrate with testing circuit |
| JP2006047962A (en) * | 2004-07-30 | 2006-02-16 | Sunplus Technology Co Ltd | Tft-lcd source driver with built-in test circuit |
| WO2009050106A1 (en) * | 2007-10-10 | 2009-04-23 | Robert Bosch Gmbh | Test device, display device and method for testing the validity of display signals |
| CN101728397A (en) * | 2008-10-22 | 2010-06-09 | 元太科技工业股份有限公司 | Active component array substrate and detection method thereof |
| CN102566102A (en) * | 2012-02-29 | 2012-07-11 | 南京中电熊猫液晶显示科技有限公司 | Method for repairing line defects of liquid crystal panels |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101090255B1 (en) * | 2004-11-16 | 2011-12-06 | 삼성전자주식회사 | Panel and test method for display device |
| KR102038983B1 (en) * | 2012-05-04 | 2019-11-01 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus, method for inspecting the organic light emitting display apparatus and apparatus for inspeting the organic light emitting display apparatus |
-
2013
- 2013-11-12 CN CN201310559525.4A patent/CN103617772B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246074B1 (en) * | 1998-09-30 | 2001-06-12 | Lg.Philips Lcd Co., Ltd. | Thin film transistor substrate with testing circuit |
| JP2006047962A (en) * | 2004-07-30 | 2006-02-16 | Sunplus Technology Co Ltd | Tft-lcd source driver with built-in test circuit |
| WO2009050106A1 (en) * | 2007-10-10 | 2009-04-23 | Robert Bosch Gmbh | Test device, display device and method for testing the validity of display signals |
| CN101728397A (en) * | 2008-10-22 | 2010-06-09 | 元太科技工业股份有限公司 | Active component array substrate and detection method thereof |
| CN102566102A (en) * | 2012-02-29 | 2012-07-11 | 南京中电熊猫液晶显示科技有限公司 | Method for repairing line defects of liquid crystal panels |
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Effective date of registration: 20230619 Address after: Lake 558, Fen Hu Town, Wujiang District, Jiangsu, Suzhou Patentee after: Wujiang FenHu technology entrepreneurship Service Co.,Ltd. Address before: No. 555 Jiangxing East Road, Tongli District, Wujiang Economic Development Zone, Suzhou City, Jiangsu Province, 215217 Patentee before: CPTW (WUJIANG) Co.,Ltd. Patentee before: Chunghwa Picture Tubes, Ltd. |