CN103595581A - Failure generating device used for digital protection communication test - Google Patents
Failure generating device used for digital protection communication test Download PDFInfo
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- CN103595581A CN103595581A CN201310552345.3A CN201310552345A CN103595581A CN 103595581 A CN103595581 A CN 103595581A CN 201310552345 A CN201310552345 A CN 201310552345A CN 103595581 A CN103595581 A CN 103595581A
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Abstract
The invention discloses a failure generating device used for a digital protection communication test. The failure generating device is characterized in that the failure generating device comprises a control chip FPGA and three Ethernet physical layer chips 88E1111. The first Ethernet physical layer chip 88E1111 and the second Ethernet physical layer chip 88E1111 are connected with an electric interface RJ45 and an optical port module SFP respectively and different communication interfaces are selected through wire jumpers; the third Ethernet physical layer chip 88E1111 is only provided with an electric interface RJ 45 which is used as an internet access for communication between the failure generating device and a PC. The failure generating device used for the digital protection communication test breaks through the limit that at present, an RTDS can only conduct protection function testing on a digital protection device, realizes combined simulation of process layer communication failures and electric system failures and can test the functions of the digital protection device more comprehensively; due to the design of double-channel data transmission, the failure generating device can have access to a process layer network more conveniently and the failure condition of any transmission line in the process layer communication network can be simulated. In addition, the failure generating device has no influence on other communication of the process layer.
Description
Technical field
The present invention relates to Automation Technology of Digitized Transformer field, thereby be a kind ofly can determine whether electric power system breaks down and the device of analog digital Substation process-level communication failure test digital protection communication performance specifically.
Background technology
Digital transformer substation is that change has occurred information interaction mode for a remarkable difference of traditional transformer station.Be that the traditional electromagnetic transformer signal of telecommunication value of being sampled message replaces, traditional switch state signal is replaced by GOOSE message.Because being in operation, the process layer devices such as electronic mutual inductor, intelligent breaker, merge cells and the network switch may there are some faults, cause the sampling value message or the GOOSE message that in network, transmit to make a mistake, as frame losing, error code, incorrect order, step-out etc.Although the probability that above-mentioned process layer communication failure occurs is not high, digital protection device must correctly be processed and tackle, and avoids protective device to occur the phenomenon of malfunction or tripping.
Within 1993, First electric power system Real Time Digital Simulator RTDS has been developed in Canadian Manitoba high voltage direct current research center, and for meeting digital transformer substation dynamic real-time simulator, RTDS has been equipped with the communication card GTNET that follows IEC61850 standard thereafter.Nowadays RTDS has been widely used in the dynamic closed loop test system of digital protection, but RTDS analog digital Substation process-level communication failure not, thereby the communication performance that cannot test digital protection device.
According to the problems referred to above, for realize to digitlization protective device carry out more comprehensively, more effective test, need to study a kind of practical value that has, for the fault generating means of digital protection communication test.
Summary of the invention
Based on above-mentioned technical problem; the present invention proposes a kind of fault generating means for digital protection communication test; can determine whether electric power system breaks down and analog digital Substation process-level communication failure, thereby realize the device of test digital protection communication performance.
The present invention proposes a kind of fault generating means for digital protection communication test, and this device comprises control chip FPGA and three ethernet physical layer chip 88E1111; First, second ethernet physical layer chip 88E1111 is connected with respectively electrical interface RJ45 and light mouth module SFP, by wire jumper, selects different communication interfaces; Three-ethernet physical chip 88E1111 is only furnished with the network interface that electrical interface RJ45 communicates by letter with PC as fault generating means.Wherein: between described first, second ethernet physical layer chip 88E1111, realize binary channels and receive/send out transfer of data, the workflow of every passage all realizes message reception, message is processed and message repeating.
Each channel setting in described binary channels a FIFO group, this FIFO group is comprised of 8 message buffering FIFO and 2 message status indication FIFO, message status indication FIFO is divided into again idle condition indication FIFO and ready state indication FIFO; Each message buffering FIFO is fixed with a sequence number, and with a timer.
Two three fast Ethernet IP kernels have been used in the transmitting-receiving of described binary channels data.
In described sampling value message, some voltage datas are set up data window sequence, according to the comentropy size of this sequence, determine whether electric power system breaks down.The algorithm steps of asking for sampling value message voltage data comentropy is as follows:
V
i＝v
i+1-v
i(i＝1,2,…,n-1) (1)
Step 3, by the increment sequence { V obtaining in step 2
i(i=1,2 ..., each data in n-1) are carried out square operation, obtain energy sequence V
i 2(i=1,2 ..., n-1);
Step 4, suc as formula the probability distribution of (2) calculating energy sequence.
Step 5, suc as formula (3), calculate the comentropy of current data window.
The floating number multiply accumulating device of asking for the algorithm employing of sampling value message voltage data comentropy is divided into floating number multiplication and the cumulative two parts of floating number: floating number multiplication is divided into two level production lines.The first order is carried out index and is added and mantissa's phase multiplication; The second level is to the result the multiplying each other processing of standardizing.The cumulative three class pipeline that is divided into of floating number.The first order is carried out index to rank to the floating number being added; Mantissa's summation is carried out to the floating number being added in the second level; The third level is to the result the being added processing of standardizing.
Fault generating means is arranged on any one position in process-level network.
Described device in use also comprises:
Configuring chip, is connected with control chip, is read the configuration information of relevant test by control chip;
Test interface, can comprise two kinds of interfaces of JTAG and AS, is connected, for the input as communication test, output interface with control chip;
Power module, for powering to control chip;
Man-machine interaction unit, comprises charactron, button, for the man-machine interaction of control chip;
Storage chip, for the relevant process such as control/test of control chip and the storage of result data
Compared with prior art, the present invention has the following advantages:
1. coordinate with RTDS can analog digital Substation process-level communication failure in the present invention.The communication performance that the dynamic closed loop test platform of digital protection device of being built by the present invention and RTDS can be tested digital protection device effectively, has broken through current RTDS and can only carry out to digitlization protective device the limitation of defencive function test.
2. electric voltage exception point when the present invention adopts the method for certain voltage data comentropy in analytical sampling value message to obtain fast electric power system fault generation; and take this abnormity point as opportunity manufacture process layer communication failure; realize the associative simulation of process layer communication failure and electric power system fault, can more fully test the function of digital protection device.
3. the binary channels data transmission scheme that the present invention realizes, not only makes fault generating means access procedure layer network easily, can also simulation process layer communication network in any transmission lines failure condition.On process layer, other communications can not produce any impact in the present invention in addition.
Accompanying drawing explanation
Fig. 1 is the fault generating means hardware configuration schematic diagram for digital protection communication test of the present invention;
Fig. 2 is the fault generating means binary channels data transmission scheme principle schematic for digital protection communication test of the present invention;
Fig. 3 is that the present invention is for the fault generating means multiply accumulating device pipeline organization figure of digital protection communication test;
Fig. 4 is that the present invention is for the fault generating means fault setting principle schematic diagram of digital protection communication test.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
As shown in Figure 1, the fault generating means for digital protection communication test mainly consists of control chip FPGA and three ethernet physical layer chip 88E1111.Wherein first, second ethernet physical layer chip 88E1111 is connected with respectively electrical interface RJ45 and light mouth module SFP, by wire jumper, can select different communication interfaces; Three-ethernet physical chip 88E1111 is only furnished with the network interface that electrical interface RJ45 communicates by letter with PC as fault generating means.Fault generating means can be arranged on any one position in process-level network, thereby realizes analog digital Substation process-level communication failure condition.
This device in use also comprises:
Configuring chip, is connected with control chip, is read the configuration information of relevant test by control chip;
Test interface, can comprise two kinds of interfaces of JTAG and AS, is connected, for the input as communication test, output interface with control chip;
Power module, for powering to control chip;
Man-machine interaction unit, comprises charactron, button, for the man-machine interaction of control chip;
Storage chip, for the relevant process such as control/test of control chip and the storage of result data.
As shown in Figure 2, at the fault generating means for digital protection communication test of the present invention, realized binary channels transfer of data.The binary channels data transmission scheme that the present invention realizes is on a set of hardware unit, to realize two completely independently to receive and dispatch path, the receiving terminal that is exactly specifically the first physical chip forms a path to the transmitting terminal of the second physical chip, and the receiving terminal of the second physical chip forms another path to the transmitting terminal of the first physical chip.Message for buffer memory receives respectively at being provided with two FIFO groups in the binary channels connecting with three fast Ethernet IP kernels between two phy chips, is used in the two passes of two chip chambers.Each FIFO group is comprised of 8 message buffering FIFO and 2 message status indication FIFO, and message status indication FIFO is divided into again idle condition indication FIFO and ready state indication FIFO.Each message buffering FIFO is fixed with a sequence number, and with a timer.Two three fast Ethernet IP kernels have been used in the transmitting-receiving of binary channels data.Three fast Ethernet IP kernels are the soft core of altera corp's exploitation, realize MAC layer function, and it can be connected with physical chip by various MAC layer interfaces.
The workflow of every passage is all divided into three steps: receive message, process message and E-Packet.Receive message and be responsible for obtaining from three fast Ethernet IP kernel receiving terminals the message having received, judge whether this message is to need message to be processed.If judgment result is that and not need words to be processed, from idle condition indication FIFO, obtain an available message buffering FIFO sequence number, message is write direct in this message buffering FIFO.If judgment result is that and need words to be processed, the corresponding communication failure of control command manufacture of assigning according to PC, communication failure is divided into 3 kinds: 1. message is abnormal, after the message receiving being revised accordingly, from idle condition indication FIFO, obtain an available message buffering FIFO sequence number again, amended message is written in this message buffering FIFO; 2. message is overtime, from idle condition indication FIFO, obtains an available message buffering FIFO sequence number, and message is write direct in message buffering FIFO, sets a period of time, analog message time-out time to the timer of this message buffering FIFO simultaneously; 3. message dropping, directly abandons message.When timer time corresponding to message buffering FIFO arrives, message buffering FIFO sequence number is added in ready state indication FIFO.E-Packet and be responsible for obtaining message buffering FIFO sequence number from ready state indication FIFO, forward successively the message in the corresponding message buffering FIFO of sequence number, the message buffering FIFO sequence number having forwarded writes in idle condition indication FIFO again.
As shown in Figure 3; for Power System Faults Detection algorithm of the present invention and hardware realization thereof; invention has realized communication among process layers of digitalized fault and electric power system fault associative simulation; manufacture process layer communication failure when electric power system fault generation being detected, can test digital protection correctly tackle electric power system fault in the situation that communication message makes a mistake.
The present invention has designed the less floating number multiply accumulating device of a kind of pipeline series, uses this floating number multiply accumulating device can calculate fast the comentropy of certain voltage data in sampling value message.Floating number multiply accumulating device is divided into floating number multiplication and cumulative two parts of floating number.
The present invention adopts the method for voltage data comentropy in calculating sampling value message to detect electric power system fault.With some voltage datas in sampling value message, set up data window sequence, according to the comentropy size of this sequence, determine in window whether have abnormity point, if there is abnormity point, represent that electric power system breaks down.The algorithm steps of asking for sampling value message voltage data comentropy is as follows:
1. by the some voltage data { v in n (general n=8) sampling value message
i(i=1,2 ..., n) as the data window of comentropy.
2. voltage data step being obtained in is 1. done difference preliminary treatment, forms increment sequence { V
i(i=1,2 ..., n-1).
V
i＝v
i+1-v
i(i＝1,2,…,n-1) (1)
3. increment sequence { V step being obtained in 2.
i(i=1,2 ..., each data in n-1) are carried out square operation, obtain energy sequence V
i 2(i=1,2 ..., n-1).
4. suc as formula the probability distribution of (2) calculating energy sequence.
5. suc as formula (3), calculate the comentropy of current data window.
In order to realize this algorithm, the present invention has designed the less floating number multiply accumulating device of a kind of pipeline series.As shown in Figure 3, this floating number multiply accumulating device is divided into floating number multiplication and the cumulative two parts of floating number.Floating number multiplication is divided into two level production lines.The first order is carried out index and is added and mantissa's phase multiplication; The second level is to the result the multiplying each other processing of standardizing.The cumulative three class pipeline that is divided into of floating number.The first order is carried out index to rank to the floating number being added; Mantissa's summation is carried out to the floating number being added in the second level; The third level is to the result the being added processing of standardizing.Whether selector effectively determines to adopt A port data or B port data according to reset signal.
In the present invention, use the specific embodiment of floating number multiply accumulating device computing information entropy to be described below:
Specifically, floating number a
nand b
nmultiply each other and need mantissa to multiply each other and index addition, the result multiplying each other also needs the processing of standardizing.Therefore, floating number multiplication needs two level production lines.Floating number is cumulative to be needed successively through the summation of Dui Jie, mantissa and normalization processing 3 level production lines.When reset signal is effective, selector is all selected the data of B port; When reset signal is invalid, selector is all selected the data of A port.
When the present invention uses floating number multiply accumulating device computing information entropy, first wushu (1) makes v into
i+1+ (1) * v
i, make x
n=v
i+1, a
n=-1, b
n=v
i, when reset signal is effective, can directly use multiply accumulating device arithmetic expression (1).In formula (2), calculate V
i 2among the calculating of summation, complete, but must after summation meter is calculated, just carry out division arithmetic, make a here
n=V
i, b
n=V
i, x
n=0.Division arithmetic and the logarithm operation IP kernel of altera corp's exploitation used in the calculating of formula (3).
As shown in Figure 4, for fault setting principle figure of the present invention, the instruction that this fault plan of establishment is assigned PC and by information of voltage entropy, calculated to electric power system fault situation comprehensively analyze, the associative simulation of implementation procedure layer communication failure and electric power system fault easily.
The process layer fault setting principle figure of the present invention's design is comprised of sampled value buffering, comentropy counting circuit, electric power system fault flag bit register, associative simulation flag bit register, fault type register 1, fault type register 2.The triad number of fault type register represents that respectively message is abnormal, message is overtime, message dropping (" 0 " is fault-free, and " 1 " is for there being fault).When PC is assigned instruction for " 00000 ", front two " 00 " represents to remove fault, associative simulation flag bit is " 0 " (" 0 " is non-associative simulation, and " 1 " is associative simulation), and fault type register 1 and fault type register 2 become " 000 " at once; When PC is assigned simple fault instruction " 10*** ", associative simulation flag bit is " 0 ", and fault type register 1 and fault type register 2 become " * * * " at once; When PC is assigned associative simulation fault instruction " 11*** " is set, associative simulation flag bit is " 1 ", fault type register 1 is " * * * " at once, when electric power system fault flag bit is " 1 " (voltage falls constantly), the data in fault type register 1 just pass in fault type register 2.
In sum, a kind of fault generating means for digital protection communication test disclosed by the invention has been realized the emulation of process-level network communication failure well, and can coordinate the fault of electric power system to realize associative simulation.The present invention has good practical value, and the performance test of digital protection and improvement are had great significance.
Claims (7)
1. for a fault generating means for digital protection communication test, it is characterized in that, this device comprises control chip FPGA and three ethernet physical layer chip 88E1111; First, second ethernet physical layer chip 88E1111 is connected with respectively electrical interface RJ45 and light mouth module SFP, by wire jumper, selects different communication interfaces; Three-ethernet physical chip 88E1111 is only furnished with the network interface that electrical interface RJ45 communicates by letter with PC as fault generating means.Wherein: between described first, second ethernet physical layer chip 88E1111, realize binary channels and receive/send out transfer of data, the workflow of every passage all realizes message reception, message is processed and message repeating.
2. the fault generating means for digital protection communication test as claimed in claim 1, it is characterized in that, each channel setting in described binary channels a FIFO group, this FIFO group is comprised of 8 message buffering FIFO and 2 message status indication FIFO, and message status indication FIFO is divided into again idle condition indication FIFO and ready state indication FIFO; Each message buffering FIFO is fixed with a sequence number, and with a timer.
3. the fault generating means for digital protection communication test as claimed in claim 1, is characterized in that, two three fast Ethernet IP kernels have been used in the transmitting-receiving of described binary channels data.
4. the fault generating means for digital protection communication test as claimed in claim 1; it is characterized in that; in described sampling value message, some voltage datas are set up data window sequence, according to the comentropy size of this sequence, determine whether electric power system breaks down.The algorithm steps of asking for sampling value message voltage data comentropy is as follows:
Step 1, by the some voltage data { v in n sampling value message
i(i=1,2 ..., n) as the data window of comentropy.
Step 2, the voltage data obtaining in step 1 is done to difference preliminary treatment, form increment sequence { V
i(i=1,2 ..., n-1).
V
i＝v
i+1-v
i(i＝1,2,…,n-1) (1)
Step 3, by the increment sequence { V obtaining in step 2
i(i=1,2 ..., each data in n-1) are carried out square operation, obtain energy sequence V
i 2(i=1,2 ..., n-1);
Step 4, suc as formula the probability distribution of (2) calculating energy sequence.
Step 5, suc as formula (3), calculate the comentropy of current data window.
5. the fault generating means for digital protection communication test as claimed in claim 4; it is characterized in that, the floating number multiply accumulating device of asking for the algorithm employing of sampling value message voltage data comentropy is divided into floating number multiplication and the cumulative two parts of floating number: floating number multiplication is divided into two level production lines.The first order is carried out index and is added and mantissa's phase multiplication; The second level is to the result the multiplying each other processing of standardizing.The cumulative three class pipeline that is divided into of floating number.The first order is carried out index to rank to the floating number being added; Mantissa's summation is carried out to the floating number being added in the second level; The third level is to the result the being added processing of standardizing.
6. the fault generating means for digital protection communication test as claimed in claim 1, is characterized in that, fault generating means is arranged on any one position in process-level network.
7. the fault generating means for digital protection communication test as claimed in claim 1, is characterized in that, described device in use also comprises:
Configuring chip, is connected with control chip, is read the configuration information of relevant test by control chip;
Test interface, can comprise two kinds of interfaces of JTAG and AS, is connected, for the input as communication test, output interface with control chip;
Power module, for powering to control chip;
Man-machine interaction unit, comprises charactron, button, for the man-machine interaction of control chip;
Storage chip, for the relevant process such as control/test of control chip and the storage of result data.
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Application publication date: 20140219 |