CN103594123A - Non-volatile memory and adjustment method thereof - Google Patents
Non-volatile memory and adjustment method thereof Download PDFInfo
- Publication number
- CN103594123A CN103594123A CN201310625597.4A CN201310625597A CN103594123A CN 103594123 A CN103594123 A CN 103594123A CN 201310625597 A CN201310625597 A CN 201310625597A CN 103594123 A CN103594123 A CN 103594123A
- Authority
- CN
- China
- Prior art keywords
- information
- current
- volatility memorizer
- school
- adjusting information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Secondary Cells (AREA)
Abstract
The invention provides a non-volatile memory and an adjustment method thereof. The non-volatile memory comprises a configuration information memory unit, a control logic unit, a test pattern control module and a test circuit. The test circuit is added into the circuit of a traditional non-volatile memory; when the non-volatile memory is powered up, the test circuit begins to work, detects working condition information of the non-volatile memory in real time and generates corresponding adjustment information according to the working condition information, and then adjustment is carried out on the non-volatile memory according to the adjustment information. Since the test circuit does not need to be connected with external equipment for input of an external instruction, the adjustment information can be generated in real time, so automatic adjustment of the non-volatile memory is realized, test time is substantially saved and test cost is reduced.
Description
Technical field
The present invention relates to a kind of non-volatility memorizer and correcting and regulating method thereof, belong to semiconductor memory field.
Background technology
Non-volatility memorizer is owing to being subject to the impact of the factors such as temperature variation of process corner and working environment, its performance can produce a certain amount of skew, be that voltage in non-volatile memory circuit, electric current etc. can change, therefore, need to carry out school tune to non-volatility memorizer, just can make non-volatility memorizer reach initial designs index request.
Traditional non-volatile memory circuit structure as shown in Figure 1, mainly comprises: storage array (Cell Array), configuration information storage unit (NVR), column decode circuitry (X decoder), array decoding circuit (Y decoder), steering logic (Control Logic), inputoutput buffer (IO Buffer), sense amplifier (SA), address buffer (Address Buffer), test pattern control module (Test Mode), electric current and voltage external interface (V/I Monitor) etc.
Traditional non-volatility memorizer is carrying out school timing, must, by the external unit input instruction being connected with electric current and voltage external interface, make non-volatility memorizer enter test pattern and obtain school adjusting information, and then carry out school tune according to the school adjusting information obtaining.This correcting and regulating method needs constantly from outside, to input instruction, and the test duration is long, and testing apparatus and cost of labor are relatively high.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of non-volatility memorizer and correcting and regulating method thereof, in the circuit of traditional non-volatility memorizer, add testing circuit, by testing circuit, detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, thus having realized the automatic school tune of non-volatility memorizer, technical scheme is as follows:
, comprising: configuration information storage unit, steering logic unit, test pattern control module and testing circuit, wherein:
Described testing circuit is connected with described steering logic unit, for detecting in real time the work state information of non-volatility memorizer, generates corresponding school adjusting information, and export described school adjusting information to steering logic unit according to described work state information;
Described steering logic unit, for described school adjusting information and canonical reference information are compared, when described school adjusting information and canonical reference information are when inconsistent, according to described school adjusting information, non-volatility memorizer is carried out to school tune, wherein, the initial state information that described canonical reference information is described non-volatility memorizer;
Test pattern control module, is stored in described configuration information storage unit for controlling described steering logic unit by described school adjusting information.
Process corner and state of temperature information when preferably, described work state information is non-volatility memorizer work.
Preferably, described steering logic unit, is further used for, when described school adjusting information and canonical reference information are when inconsistent, producing control signal, and described control signal is used for activating described test pattern control module.
Preferably, described school adjusting information is the information of school tune that the electric current in the whole circuit of non-volatility memorizer, voltage, capacitor's capacity or metal-oxide-semiconductor quantity are carried out.
Preferably, described test circuit comprises: the first current source, the second current source, a PMOS pipe, a NMOS pipe, voltage-current converter, current comparator, bank of latches and school adjusting information scrambler, wherein:
The input end of described the first current source is connected with power supply, and the output terminal of described the first current source is connected with the source electrode of a described PMOS pipe, and the drain electrode of a described PMOS pipe is connected with earth terminal, and grid and the drain electrode of a described PMOS pipe are joined;
The input end of described the second current source is connected with power supply, and the output terminal of described the second current source is connected with the drain electrode of a described NMOS pipe, and the source electrode of a described NMOS pipe is connected with earth terminal, and the drain and gate of a described NMOS pipe joins;
A described source electrode for PMOS pipe and the input end of described voltage-current converter are connected, and for the voltage transitions that a described PMOS is managed to source electrode, are the first electric current;
The first input end of described current comparator is connected with the output terminal of described voltage-current converter, the second input end of described current comparator is connected with the grid of a described NMOS pipe, described current comparator is for obtaining n first mirror image current by described the first current ratio mirror image, and the n that the current ratio mirror image in a described NMOS pipe is obtained second image current, and described n first mirror image current compared with described n corresponding the second image current respectively, obtain n comparative result, wherein, n is greater than 2 positive integer;
The input end of described bank of latches is connected with the n of described current comparator output terminal, for latching n comparative result of described current comparator output;
The input end of described school adjusting information scrambler is connected with the output terminal of described bank of latches, and described school adjusting information scrambler is for by the described n comparative result generating digital school adjusting information of encoding, and offers described steering logic unit.
Preferably, described voltage-current converter comprises: the 2nd NMOS pipe and the 2nd PMOS pipe, wherein:
The grid of described the 2nd NMOS pipe is the input end of described voltage-current converter, the source ground of described the 2nd NMOS pipe, described the 2nd NMOS pipe drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, drain electrode and the grid of described the 2nd PMOS pipe join, the output terminal that the grid of described the 2nd PMOS pipe is described voltage-current converter.
Preferably, described current comparator comprises: n PMOS pipe and n NMOS manage, and n is greater than 2 integer, wherein:
The source electrode of n PMOS pipe is all connected with direct supply, and the grid of n PMOS pipe is connected as the first input end of current comparator, and the source electrode of n NMOS pipe is all connected with earth terminal, and the grid of n NMOS pipe is connected as the second input end of current comparator;
The drain electrode of n PMOS pipe is connected as the output terminal of described current comparator with the drain electrode of NMOS pipe corresponding in n NMOS pipe respectively.
, be applied to non-volatility memorizer, comprising:
Detect the work state information of described non-volatility memorizer, and generate corresponding school adjusting information according to described work state information;
More described school adjusting information and canonical reference information, when described school adjusting information and canonical reference information are when inconsistent, be stored in configuration information storage unit by described school adjusting information;
According to described school adjusting information, described non-volatility memorizer is carried out to school tune.
Preferably, also comprise:
Read the school adjusting information in described configuration information storage unit, according to described school adjusting information, non-volatility memorizer is carried out to school tune.
From above technical scheme provided by the invention, non-volatility memorizer provided by the invention and correcting and regulating method thereof, in the circuit of traditional non-volatility memorizer, added testing circuit, after non-volatility memorizer powers on, testing circuit is started working, detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, because test circuit does not need to connect external unit input external command, can generate in real time school adjusting information, thereby adjust in the automatic school of having realized non-volatility memorizer, greatly saved the test duration, reduced testing cost.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the circuit structure diagram of traditional non-volatility memorizer;
Fig. 2 is the circuit structure diagram of the disclosed non-volatility memorizer of the embodiment of the present invention;
Fig. 3 is the structural drawing of the disclosed testing circuit of the embodiment of the present invention;
Fig. 4 is the process flow diagram of the disclosed correcting and regulating method of the embodiment of the present invention.
Embodiment
In order to make those skilled in the art person understand better the technical scheme in the application, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Embodiment based in the application, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all should belong to the scope of the application's protection.
The embodiment of the invention discloses a kind of non-volatility memorizer, its circuit structure as shown in Figure 2, comprise: configuration information storage unit 201, steering logic unit 202, test pattern control module 203 and test circuit 204, compare with traditional non-volatility memorizer, it has added test circuit 204 in circuit, and test circuit 204 is connected with steering logic unit 202.
Described test circuit 204, for detecting in real time the work state information of non-volatility memorizer, generates corresponding school adjusting information according to described work state information, and exports described school adjusting information to steering logic unit 202.
Wherein, process corner and state of temperature information when work state information is non-volatility memorizer work, the foundation of school adjusting information and process corner and state of temperature information corresponding relation, be by the breadth length ratio of PMOS pipe P1-Pn reasonable in design and NMOS pipe N1-Nn, make in different process corner different with the school adjusting information under working temperature.
School adjusting information in register is not longer-term storage, school adjusting information in power-off late register may disappear, therefore, need high-ranking officers' adjusting information to be stored in the configuration information storage unit 201 of non-volatility memorizer, this is because the information in configuration information storage unit 201 can not lost after power-off.After non-volatility memorizer powers on again, the processor in the system of non-volatility memorizer place can read school adjusting information, and according to school adjusting information, non-volatility memorizer be carried out to school tune from described configuration information storage unit 201.
Test pattern control module 203, when described school adjusting information and canonical reference information are when inconsistent, steering logic unit 202 produces control signal and activates test pattern control module 203, make non-volatility memorizer enter test pattern, and control described steering logic unit 202 high-ranking officers' adjusting informations and be stored in configuration information storage unit 201, after having stored, test pattern control module 203 is closed, and non-volatility memorizer exits test pattern.
Certainly, in other embodiments, test pattern control module 203 also has other functions, does not repeat them here.
Adjust in the school to non-volatility memorizer described in arbitrary embodiment disclosed by the invention, is all that the quantity of electric current, voltage, resistance value, capacitor's capacity or metal-oxide-semiconductor in the whole circuit of non-volatility memorizer is carried out to school tune.
The circuit structure of the testing circuit in above-described embodiment as shown in Figure 3, mainly comprises: the first current source 301, the second current source 302, a PMOS pipe Pt, a NMOS pipe Nt, voltage-current converter 303, current comparator 304, bank of latches 305 and school adjusting information scrambler 306.
The input end of the first current source 301 is connected with direct supply, and the output terminal of the first current source 301 is connected with the source electrode of a PMOS pipe Pt, and the drain electrode of a PMOS pipe Pt is connected with earth terminal, and grid and the drain electrode of a PMOS pipe Pt are joined.
The input end of the second current source 302 is connected with power supply, and the output terminal of the second current source 302 is connected with the drain electrode of a NMOS pipe Nt, and the source electrode of a NMOS pipe Nt is connected with earth terminal, and the drain and gate of a NMOS pipe Nt joins.
Concrete, the identical It that is of electric current that the first current source 301 produces with the second current source 302.The one PMOS pipe Pt is identical with the breadth length ratio of a NMOS pipe Nt, and described breadth length ratio is the ratio of channel width with the channel length of MOS device.
When non-volatility memorizer powers on, the flow through source electrode of the described PMOS pipe Pt that connects in diode mode of the output current It of described the first current source 301, the flow through drain electrode of the described NMOS pipe Nt that connects in diode mode of the output current It of described the second current source 302.
Voltage-current converter 303 comprises: the 2nd PMOS pipe P0, the 2nd NMOS pipe N0, wherein, the grid of the 2nd NMOS pipe P0 is the source electrode that the input end of voltage-current converter 303 connects a described PMOS pipe Pt, the source ground of the 2nd NMOS pipe N0, the drain electrode of the 2nd NMOS pipe N0 is connected with the drain electrode of the 2nd PMOS pipe P0, drain electrode and the grid of the 2nd PMOS pipe P0 join, and the grid of the 2nd PMOS pipe P0 is the output terminal of voltage-current converter 303.Voltage-current converter 303 is the first electric current I p0 for the voltage transitions that a described PMOS is managed to source electrode.
The source electrode of n PMOS pipe is all connected with direct supply, and the grid of n PMOS pipe is connected as the first input end of current comparator 304, is connected with the output terminal of voltage-current converter 303.
The source electrode of n NMOS pipe is connected with earth terminal, and the grid of n NMOS pipe is connected as the second input end of current comparator 304, is connected with the grid of a described NMOS pipe Nt.
The drain electrode of n PMOS pipe is connected with the drain electrode of n NMOS pipe respectively, the output terminal that is current comparator with points of common connection n NMOS pipe n PMOS pipe.
Concrete, the drain electrode of P1 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2, the like, the drain electrode of Pn is connected with the drain electrode of Nn.
The input end of bank of latches 305 is connected with n output terminal of current comparator 304 respectively, for latching n comparative result of current comparator 304 outputs.
The input end of school adjusting information scrambler 306 is connected with the output terminal of bank of latches 305, for generating digital school adjusting information that a described n comparative result is encoded, and offers described steering logic unit 202.
The non-volatility memorizer that the embodiment of the present invention provides, in the circuit of traditional non-volatility memorizer, add testing circuit, after non-volatility memorizer powers on, testing circuit is started working, detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, because test circuit does not need to connect external unit input external command, can generate in real time school adjusting information, thereby adjust in the automatic school of having realized non-volatility memorizer, greatly reduced the test duration, reduced testing cost.
The embodiment of the invention also discloses a kind of method that adjust in school, the non-volatility memorizer in application above-described embodiment, the process flow diagram of the method as shown in Figure 4, comprises the following steps:
Step 401: detect the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information.
After non-volatility memorizer powers on, testing circuit is started working, constantly detect the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to work state information, process corner and state of temperature information when wherein, described work state information is non-volatility memorizer work.
Step 402: more described school adjusting information and canonical reference information, when described school adjusting information and canonical reference information are when inconsistent, be stored in configuration information unit by described school adjusting information.
Wherein, canonical reference information is corresponding to the initial state information of described non-volatility memorizer.When school adjusting information exports to behind steering logic unit, steering logic unit can high-ranking officers' adjusting information and canonical reference information compare, when school adjusting information and canonical reference information are when inconsistent, high-ranking officers' adjusting information is stored in configuration information storage unit.
Step 403: described non-volatility memorizer is carried out to school tune according to described school adjusting information.
When school adjusting information and canonical reference information are when inconsistent, steering logic unit can carry out school tune according to described school adjusting information to described non-volatility memorizer in real time.After power-off, the school adjusting information being stored in configuration information storage unit can not disappear, after again powering on, the processor in steering logic unit or non-volatility memorizer place system can read the school adjusting information in configuration information storage unit, and again carries out school tune according to described school adjusting information.
The disclosed correcting and regulating method of the present embodiment, can detect in real time the work state information of non-volatility memorizer, and generate corresponding school adjusting information according to described work state information, and then according to described school adjusting information, non-volatility memorizer is carried out to school tune, having realized the automatic school of non-volatility memorizer adjusts, greatly saved the test duration, reduced testing cost.
The above is only the application's embodiment; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the application's protection domain.
Claims (9)
1. a non-volatility memorizer, is characterized in that, comprising: configuration information storage unit, steering logic unit, test pattern control module and testing circuit, wherein:
Described testing circuit is connected with described steering logic unit, for detecting in real time the work state information of non-volatility memorizer, generates corresponding school adjusting information, and export described school adjusting information to steering logic unit according to described work state information;
Described steering logic unit, for described school adjusting information and canonical reference information are compared, when described school adjusting information and canonical reference information are when inconsistent, according to described school adjusting information, non-volatility memorizer is carried out to school tune, wherein, the initial state information that described canonical reference information is described non-volatility memorizer;
Test pattern control module, is stored in described configuration information storage unit for controlling described steering logic unit by described school adjusting information.
2. non-volatility memorizer according to claim 1, is characterized in that, process corner and state of temperature information when described work state information is non-volatility memorizer work.
3. non-volatility memorizer according to claim 1, it is characterized in that described steering logic unit is further used for when described school adjusting information and canonical reference information are when inconsistent, produce control signal, described control signal is used for activating described test pattern control module.
4. according to the non-volatility memorizer described in claim 1-3 any one, it is characterized in that, described school adjusting information is the information of school tune that the electric current in the whole circuit of non-volatility memorizer, voltage, capacitor's capacity or metal-oxide-semiconductor quantity are carried out.
5. non-volatility memorizer according to claim 1, it is characterized in that, described test circuit comprises: the first current source, the second current source, a PMOS pipe, a NMOS pipe, voltage-current converter, current comparator, bank of latches and school adjusting information scrambler, wherein:
The input end of described the first current source is connected with power supply, and the output terminal of described the first current source is connected with the source electrode of a described PMOS pipe, and the drain electrode of a described PMOS pipe is connected with earth terminal, and grid and the drain electrode of a described PMOS pipe are joined;
The input end of described the second current source is connected with power supply, and the output terminal of described the second current source is connected with the drain electrode of a described NMOS pipe, and the source electrode of a described NMOS pipe is connected with earth terminal, and the drain and gate of a described NMOS pipe joins;
A described source electrode for PMOS pipe and the input end of described voltage-current converter are connected, and for the voltage transitions that a described PMOS is managed to source electrode, are the first electric current;
The first input end of described current comparator is connected with the output terminal of described voltage-current converter, the second input end of described current comparator is connected with the grid of a described NMOS pipe, described current comparator is for obtaining n first mirror image current by described the first current ratio mirror image, and the n that the current ratio mirror image in a described NMOS pipe is obtained second image current, and described n first mirror image current compared with described n corresponding the second image current respectively, obtain n comparative result, wherein, n is greater than 2 positive integer;
The input end of described bank of latches is connected with the n of described current comparator output terminal, for latching n comparative result of described current comparator output;
The input end of described school adjusting information scrambler is connected with the output terminal of described bank of latches, and described school adjusting information scrambler is for by the described n comparative result generating digital school adjusting information of encoding, and offers described steering logic unit.
6. non-volatility memorizer according to claim 5, is characterized in that, described voltage-current converter comprises: the 2nd NMOS pipe and the 2nd PMOS pipe, wherein:
The grid of described the 2nd NMOS pipe is the input end of described voltage-current converter, the source ground of described the 2nd NMOS pipe, described the 2nd NMOS pipe drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, drain electrode and the grid of described the 2nd PMOS pipe join, the output terminal that the grid of described the 2nd PMOS pipe is described voltage-current converter.
7. non-volatility memorizer according to claim 6, is characterized in that, described current comparator comprises: n PMOS pipe and n NMOS manage, and n is greater than 2 integer, wherein:
The source electrode of n PMOS pipe is all connected with direct supply, and the grid of n PMOS pipe is connected as the first input end of current comparator, and the source electrode of n NMOS pipe is all connected with earth terminal, and the grid of n NMOS pipe is connected as the second input end of current comparator;
The drain electrode of n PMOS pipe is connected as the output terminal of described current comparator with the drain electrode of NMOS pipe corresponding in n NMOS pipe respectively.
8. a correcting and regulating method, is applied to non-volatility memorizer, it is characterized in that, the method comprises:
Detect the work state information of described non-volatility memorizer, and generate corresponding school adjusting information according to described work state information;
More described school adjusting information and canonical reference information, when described school adjusting information and canonical reference information are when inconsistent, be stored in configuration information storage unit by described school adjusting information;
According to described school adjusting information, described non-volatility memorizer is carried out to school tune.
9. correcting and regulating method according to claim 8, is characterized in that, also comprises:
Read the school adjusting information in described configuration information storage unit, according to described school adjusting information, non-volatility memorizer is carried out to school tune.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310625597.4A CN103594123B (en) | 2013-11-28 | 2013-11-28 | Non-volatility memorizer and correcting and regulating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310625597.4A CN103594123B (en) | 2013-11-28 | 2013-11-28 | Non-volatility memorizer and correcting and regulating method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103594123A true CN103594123A (en) | 2014-02-19 |
| CN103594123B CN103594123B (en) | 2016-09-14 |
Family
ID=50084224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310625597.4A Active CN103594123B (en) | 2013-11-28 | 2013-11-28 | Non-volatility memorizer and correcting and regulating method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103594123B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139891A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Method and device for calibrating analogue integrated circuit |
| CN114758713A (en) * | 2022-06-14 | 2022-07-15 | 之江实验室 | Circuit and method for accelerating durability test of ferroelectric memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102203875A (en) * | 2008-09-30 | 2011-09-28 | Lsi公司 | Methods and apparatus for soft data generation for memory devices using reference cells |
| CN103339676A (en) * | 2011-01-31 | 2013-10-02 | 飞思卡尔半导体公司 | Integrated circuit device, voltage regulation circuitry and method for regulating a voltage supply signal |
| CN103348574A (en) * | 2010-12-03 | 2013-10-09 | 马维尔国际贸易有限公司 | Process and temperature insensitive inverter |
-
2013
- 2013-11-28 CN CN201310625597.4A patent/CN103594123B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102203875A (en) * | 2008-09-30 | 2011-09-28 | Lsi公司 | Methods and apparatus for soft data generation for memory devices using reference cells |
| CN103348574A (en) * | 2010-12-03 | 2013-10-09 | 马维尔国际贸易有限公司 | Process and temperature insensitive inverter |
| CN103339676A (en) * | 2011-01-31 | 2013-10-02 | 飞思卡尔半导体公司 | Integrated circuit device, voltage regulation circuitry and method for regulating a voltage supply signal |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139891A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Method and device for calibrating analogue integrated circuit |
| CN105139891B (en) * | 2015-09-11 | 2023-04-18 | 四川易冲科技有限公司 | Method and device for calibrating analog integrated circuit |
| CN114758713A (en) * | 2022-06-14 | 2022-07-15 | 之江实验室 | Circuit and method for accelerating durability test of ferroelectric memory |
| CN114758713B (en) * | 2022-06-14 | 2022-10-14 | 之江实验室 | Circuit and method for accelerating durability test of ferroelectric memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103594123B (en) | 2016-09-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8291248B2 (en) | Non-volatile semiconductor memory device with power saving feature | |
| CN104217744A (en) | Current sensing amplifier and sensing method thereof | |
| TW201519250A (en) | Semiconductor storage device and memory system | |
| US20120087192A1 (en) | Non-Volatile Memory Device with Program Current Clamp and Related Method | |
| TW201503131A (en) | Memory storage circuit and method of driving memory storage circuit | |
| KR100875006B1 (en) | Flash memory device and program voltage control method | |
| KR20150079909A (en) | Low voltage current reference generator for a sensing amplifier | |
| CN104467405A (en) | Charge pump circuit and storage device | |
| CN102855931A (en) | Memory and reading circuit thereof | |
| KR20140104203A (en) | Circuit for generating reference voltage | |
| CN104134461B (en) | A kind of reading circuit structure of hybrid memory cell | |
| CN103594123A (en) | Non-volatile memory and adjustment method thereof | |
| US20170070225A1 (en) | Power gating devices and methods | |
| JP3751594B2 (en) | Semiconductor memory device | |
| US9666258B2 (en) | Bit line clamp voltage generator for STT MRAM sensing | |
| US20170131910A1 (en) | Register having non-volatile memory for backing up and restoring volatile memory | |
| US9046551B2 (en) | Voltage detection circuit and internal voltage generator using the same | |
| US20180061502A1 (en) | Memory array, and method for reading, programming and erasing memory array | |
| EP2498258B1 (en) | Non-volatile memory device with program current clamp and related method | |
| US6813186B2 (en) | Nonvolatile semiconductor memory device | |
| CN106952664B (en) | A kind of flash memory sense amplifier | |
| TWI704564B (en) | Memory device and power control circuit thereof | |
| TWI375225B (en) | Memory and reading method thereof | |
| CN106409340B (en) | Write voltage generation circuit and memory device | |
| KR102453779B1 (en) | Sense Amplifier and Storage Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |