CN103579109B - A kind of manufacture method of integrated optoelectronic circuit - Google Patents
A kind of manufacture method of integrated optoelectronic circuit Download PDFInfo
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- CN103579109B CN103579109B CN201310534726.9A CN201310534726A CN103579109B CN 103579109 B CN103579109 B CN 103579109B CN 201310534726 A CN201310534726 A CN 201310534726A CN 103579109 B CN103579109 B CN 103579109B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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Abstract
The present invention relates to semiconductor technology, particularly relate to the manufacture method of a kind of integrated optoelectronic circuit. Manufacture method of the present invention mainly comprises the following steps: silicon chip is processed, and makes a part for silicon chip possess oxide layer; Silicon chip have the part of oxide layer and the part of non-oxidation layer isolate; On silicon chip, the part of non-oxidation layer manufactures photoelectric device, manufactures electronic device in oxide layer, and described photoelectric device is for adopting vertical structure, and electronic device adopts SOI technology. Beneficial effects of the present invention, for making photodiode and integrated circuit modules be integrated on same chip, effectively reduces encapsulation difficulty and cost, reduces ghost effect, improve reliability. Present invention is particularly suitable for the manufacture of integrated optoelectronic circuit.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to the manufacture method of a kind of integrated optoelectronic circuit.
Background technology
Integrated optoelectronic circuit (optoelectronicintegratedcircuit, OEIC), is photoelectric device and electronic device are integrated, to realize the integrated circuit of certain specific function in optical communication system or optical information processing system.
Conventional common integrated optoelectronic circuit is all adopt the manufacture method with the silica-based process compatible of traditional standard to carry out single-chip integration, and such integration mode decreases the assembling link in hybrid circuit, and its reliability and speed have also been obtained obvious optimization. But, photoelectric device in this integration mode and the electric isolating effect between electronic device are poor, photo-generated carrier produced by photoelectric device and the carrier in electronic device can interfere, additionally, common process also needs to consider the compatibling problem between photoelectric device and electronic device process. And the single chip integrated partial SOI process of integrated optoelectronic circuit employing in this paper makes, by techniques such as SIMOX or SDB, chip is isolated into SOI basic mode block and conventional silicon substrate region, its integrated circuit modules utilizes standard SOI process to be produced on SOI basic mode block, and photoelectric device adopts vertical structure to be produced on conventional silicon substrate region, two modules are interconnected by metal. Adopt the integrated optoelectronic circuit of integration mode herein, can the respective advantage of comprehensive photoelectric device and integrated circuit modules effectively, decrease process compatible problem, it is achieved the optimization of performance simultaneously.
Summary of the invention
To be solved by this invention, it is simply that for the process integration issues of existing integrated optoelectronic circuit, it is proposed that longitudinal photodetector and integrated circuit modules in a kind of integrated optoelectronic circuit adopt SOI technology to carry out single chip integrated method.
This invention address that above-mentioned technical problem be the technical scheme is that the manufacture method of a kind of integrated optoelectronic circuit, it is characterised in that comprise the following steps:
A. silicon chip is processed, make a part for silicon chip possess oxide layer;
B., silicon chip have the part of oxide layer and the part of non-oxidation layer isolate;
C. on silicon chip, the part of non-oxidation layer manufactures photoelectric device, manufactures electronic device in oxide layer, and described photoelectric device is for adopting vertical structure, and electronic device adopts SOI technology.
Concrete, step a's method particularly includes:
A1. using silicon chip as Semiconductor substrate 301, the epitaxial layer 302 of Semiconductor substrate 301 arranges mask plate 303, carry out O +ion implanted, the epitaxial layer 302 of the non-mask film covering version 303 in surface is formed oxide layer 304;
A2. by heat treatment, oxide layer 304 is formed insulating barrier 305;
A3. mask plate 303 is removed.
Further, step b method particularly includes:
Adopting groove etched, etch multiple sealing coat 306 on insulating barrier 305, the epitaxial layer 302 on insulating barrier 305 is isolated into multiple part by described sealing coat 306.
Concrete, step a's method particularly includes:
A1. the silicon chip 402 of the silicon chip 401 and non-oxidation layer that have oxide layer through and being bonded to soi structure;
A2. by a part for the soi structure of synthesis in wet etching removal step a1, being specially the silicon chip 402 removing part non-oxidation layer and the silicon chip 401 having oxide layer being connected with this part, the part of the removed silicon chip 401 having oxide layer includes the oxide layer of this part;
A3. the structure growing epitaxial layers 403 obtained in step a2;
A4. glossing is adopted to be worked into required thickness the structure obtained in step a3.
Further, step b method particularly includes:
The oxide layer of silicon chip 401 having oxide layer arranges multiple sealing coat, the silicon chip in oxide layer is isolated into multiple part.
Further, described arrange multiple sealing coat be adopt by etch formed trench isolations or formed V-groove isolation mode isolate.
Beneficial effects of the present invention is so that photodiode and integrated circuit modules are integrated on same chip, effectively reduces encapsulation difficulty and cost, reduces ghost effect, improves reliability.
Accompanying drawing explanation
Fig. 1 is the structural representation of embodiment 1;
Fig. 2 is the schematic cross-section of embodiment 1;
Fig. 3 be embodiment 1 manufacturing process flow in mask film covering version 303 carry out the schematic diagram of O +ion implanted;
Fig. 4 be embodiment 1 manufacturing process flow in formed oxide layer 304 schematic diagram;
Fig. 5 be embodiment 1 manufacturing process flow in formed insulating barrier 305 schematic diagram;
Fig. 6 be embodiment 1 manufacturing process flow in remove schematic diagram after mask plate 303;
Fig. 7 be embodiment 1 manufacturing process flow in etching sealing coat 306 schematic diagram;
Fig. 8 be embodiment 2 manufacturing process flow in the silicon chip 401(N+ having oxide layer is adulterated) with the silicon chip 402 of non-oxidation layer through being bonded to the schematic diagram of soi structure;
Fig. 9 be embodiment 2 manufacturing process flow in wet etching remove soi structure a part after schematic diagram;
Figure 10 be embodiment 2 manufacturing process flow in schematic diagram after grown epitaxial layer;
Figure 11 be embodiment 2 manufacturing process flow in adopt glossing to be worked into the schematic diagram after required thickness;
Figure 12 be embodiment 2 manufacturing process flow in by schematic diagram after trench isolations;
Figure 13 be embodiment 2 manufacturing process flow in isolated by V-groove after schematic diagram.
Detailed description of the invention
Below in conjunction with drawings and Examples, technical scheme is described in detail:
The present invention, on the Process ba-sis of general integrated optoelectronic circuit, improves manufacture method so that photodiode and integrated circuit modules are integrated on same chip, effectively reduces encapsulation difficulty and cost, reduces ghost effect, improves reliability.Compared with mainstream technology, the invention have the advantages that the integrated electro integrated circuit of employing, it is possible to effectively reduce encapsulation difficulty and cost, reduce ghost effect, and improve reliability; The photodiode adopted is fabricated to vertical structure, effectively improves the response speed of photodiode; The integrated circuit modules adopted is that SOI technology makes, and its parasitic capacitance is little, without latch-up, and can reduce the power consumption of circuit; The integration mode of the integrated optoelectronic circuit adopted, can realize optimization by the performance of photodiode and integrated circuit modules effectively.
Embodiment 1:
As it is shown in figure 1, this example is integrated optoelectronic circuit, including two parts: photodiode and follow-up CMOS amplifying circuit. Wherein photodiode is the PIN pipe of a longitudinal direction, the CMOS technology compatible with SOI make, and follow-up CMOS amplifying circuit through specifically connecting to form by several NMOS tube, PMOS, resistance and electric capacity, is made by SOI technology and formed.
Wherein, photodiode 101, including the anode 102 of PIN pipe, for receiving illumination, metal connecting line 103 is the metal connecting line connecing anode, is coated with one layer of anti-reflecting layer 104 on anode 102, for promoting the quantum efficiency of diode, negative electrode does overleaf, is not illustrated in Fig. 1; In Fig. 1, CMOS amplifying circuit only shows device architecture two kinds basic, wherein NMOS tube 105 includes source class 108, grid 109 and drain electrode 110, PMOS 106 includes source class 111, grid 112 and drain electrode 113, and all of metal-oxide-semiconductor is all separated by SiO2107, and is made on one layer of SiO2 insulating barrier.
As shown in Figure 2, cross section for the part of devices of this example illustrates figure, wherein A-A ' section be in Fig. 1 photodiode along the cross-sectional view of A-A ', N+ substrate 201 is as the negative electrode of PIN pipe, N-epitaxial layer 202 is the I layer in PIN pipe, P+ doped layer 204 is as the anode of PIN pipe, and metal electrode 203 and 206 is connected on front and back respectively; B-B ' section is the cross-sectional view in Fig. 1 along CMOS amplifying circuit B-B ' section, whole circuit is made on SiO2 insulating barrier 214, each device is isolated by one layer of SiO2 shallow slot 207, NMOS tube includes grid 209, source electrode 208 and drain electrode 207, and PMOS includes grid 212, source 211 and drain electrode 213.
As shown in Fig. 3-Fig. 7, for the manufacturing process of this example:
This example adopts SIMOX technique to make, and specifically comprises the following steps that
1, the epitaxial layer 302 in Semiconductor substrate 301 will need the region making photodiode to cover with mask 303, and carries out O +ion implanted, as shown in Figure 3;
2, after O +ion implanted, define initial oxide layer 304, as shown in Figure 4;
3, after Overheating Treatment, form required insulating barrier 305, as shown in Figure 5;
4, mask 303 is got rid of, as shown in Figure 6;
5, utilize groove etched, produce one layer of sealing coat 306 and cmos circuit part and photodiode are partly or completely isolated out, also the device isolation in cmos circuit is come, as shown in Figure 7 simultaneously.
After partial SOI process flow process completes, it is possible to the longitudinal photodiode carrying out routine makes the making with cmos circuit. Concrete longitudinal photodiode makes, mentioned by having in the Chinese patent that publication number is CN101069288A.
Embodiment 2:
As shown in Fig. 8-Figure 13, this example adopts Direct Bonding (SDB) fabrication techniques silicon chip substrate, concretely comprises the following steps:
1. will one side have the silicon chip 401(N+ of oxide layer adulterate) be bonded to soi structure with the silicon chip 402 of non-oxidation layer process, as shown in Figure 8;
2. removed the silicon layer and oxide layer that need to make the region of photodiode by wet etching, as shown in Figure 9;
3. grown epitaxial layer 403, as shown in Figure 10;
4. epitaxial layer adopt glossing to required thickness, as shown in figure 11;
5. adopt the mode of lateral isolation, photoelectric device region and integrated circuit zone isolation are left, it is possible to the mode of employing has trench isolations (as shown in figure 12) and V-groove isolation (as shown in figure 13).
Above processing technology and material should determine according to actual process environment.
Claims (2)
1. the manufacture method of an integrated optoelectronic circuit, it is characterised in that comprise the following steps:
A. silicon chip is processed, make a part for silicon chip possess oxide layer; Particularly as follows:
A1. the silicon chip (402) of the silicon chip (401) and non-oxidation layer that have oxide layer through and being bonded to soi structure;
A2. by a part for the soi structure of synthesis in wet etching removal step a1, being specially the silicon chip (402) removing part non-oxidation layer and the silicon chip (401) having oxide layer being connected with this part, the part of the removed silicon chip (401) having oxide layer includes the oxide layer of this part;
A3. the structure growing epitaxial layers (403) obtained in step a2;
A4. glossing is adopted to be worked into required thickness the structure obtained in step a3;
B., silicon chip have the part of oxide layer and the part of non-oxidation layer isolate; It is specially and multiple sealing coat is set in the oxide layer of the silicon chip (401) having oxide layer, the silicon chip in oxide layer is isolated into multiple part;
C. on silicon chip, the part of non-oxidation layer manufactures photoelectric device, manufactures electronic device in oxide layer; Described photoelectric device adopts vertical structure, and for longitudinal P IN photodiode, electronic device adopts SOI technology.
2. the manufacture method of a kind of integrated optoelectronic circuit according to claim 1, it is characterised in that described arrange multiple sealing coat be adopt by etch formed V-groove isolation mode isolate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310534726.9A CN103579109B (en) | 2013-11-01 | 2013-11-01 | A kind of manufacture method of integrated optoelectronic circuit |
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| CN201310534726.9A CN103579109B (en) | 2013-11-01 | 2013-11-01 | A kind of manufacture method of integrated optoelectronic circuit |
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| CN103579109A CN103579109A (en) | 2014-02-12 |
| CN103579109B true CN103579109B (en) | 2016-06-08 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1564308A (en) * | 2004-03-19 | 2005-01-12 | 中国科学院上海微***与信息技术研究所 | Upper silicon structure of insulation layer and its prepn. method |
| CN1748312A (en) * | 2003-02-19 | 2006-03-15 | 信越半导体股份有限公司 | Method for manufacturing soi wafer and soi wafer |
| US7338848B1 (en) * | 2004-10-20 | 2008-03-04 | Newport Fab, Llc | Method for opto-electronic integration on a SOI substrate and related structure |
| CN101566705A (en) * | 2009-06-12 | 2009-10-28 | Nano科技(北京)有限公司 | Optoelectronic integrated circuit and substrate preparation method |
| CN101996947A (en) * | 2009-08-19 | 2011-03-30 | 中国科学院半导体研究所 | Method for integrating silicon-based photoelectric device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1748312A (en) * | 2003-02-19 | 2006-03-15 | 信越半导体股份有限公司 | Method for manufacturing soi wafer and soi wafer |
| CN1564308A (en) * | 2004-03-19 | 2005-01-12 | 中国科学院上海微***与信息技术研究所 | Upper silicon structure of insulation layer and its prepn. method |
| US7338848B1 (en) * | 2004-10-20 | 2008-03-04 | Newport Fab, Llc | Method for opto-electronic integration on a SOI substrate and related structure |
| CN101566705A (en) * | 2009-06-12 | 2009-10-28 | Nano科技(北京)有限公司 | Optoelectronic integrated circuit and substrate preparation method |
| CN101996947A (en) * | 2009-08-19 | 2011-03-30 | 中国科学院半导体研究所 | Method for integrating silicon-based photoelectric device |
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