CN103559095B - Method of data synchronization for the double-core multiple processor structure of relay protection field - Google Patents
Method of data synchronization for the double-core multiple processor structure of relay protection field Download PDFInfo
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- CN103559095B CN103559095B CN201310526722.6A CN201310526722A CN103559095B CN 103559095 B CN103559095 B CN 103559095B CN 201310526722 A CN201310526722 A CN 201310526722A CN 103559095 B CN103559095 B CN 103559095B
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Abstract
The invention discloses the method for data synchronization of a kind of double-core multiple processor structure being applied to relay protection field, including the step of the data syn-chronization between the step of the double-core data syn-chronization within first processor and first processor and the second processor；The method of data synchronization that the inventive method provides, according to the particularity of relay protection field task priority, data syn-chronization tool validity and real-time, makes protective relaying device can timely respond to guidance command, improves protective relaying device performance.
Description
Technical field
The present invention relates to synchronous processing field of data, particularly relate to a kind of double-core multiple processor structure for relay protection field
Method of data synchronization.
Background technology
In relay protection field, automation equipment is in addition to real-time guard field apparatus, in addition it is also necessary to the station level main frame of transformer station
Set up data communication, effectively realize data on send and issue.After especially relay protection enters the Microcomputer Protection epoch, communication rule
Procotol about relys more on operating system, has higher requirement the real-time of device with the reliability communicated.If
Data syn-chronization between device inner treater does not have the sampled data needed for validity and real-time, protection algorism not in time, fail and
Time response guidance command, protection device performance can be affected.
The outdated data produced to prevent factor data asynchronous, the most all can increase data syn-chronization when processor data exchanges
Function, especially between multi-CPU, the data syn-chronization of general chip chamber is realized by STD bus mode or twoport cache way,
But STD bus is retrained by hardware interface and speed, be not suitable for the communication between multi-CPU；And twoport cache chip is suitable only for
The communication of dual processors, and increase hardware cost.And for the system platform of double-core multiple processor structure, double-core CPU should be realized
Internal communication, realizes the communication between CPU again, and above common way exists certain drawback.
Summary of the invention
The technical problem to be solved in the present invention is for defect of the prior art, it is provided that a kind of double for relay protection field
The method of data synchronization of core multiple processor structure.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of method of data synchronization of the double-core multiple processor structure for relay protection field, double including within first processor
The step of the data syn-chronization between the step of Nuclear Data synchronization and first processor and the second processor；
The step of the double-core data syn-chronization within first processor is as follows:
In the level cache of first processor, i.e. sheet, shared storage area and the L2 cache of first processor, i.e. off-chip are shared
Storage opens up the circle queue of the first core and the second core respectively as data exchange zone in region；The data structure of described queue includes
Message header and message array, message header record information updating writes sequence number and information updating reads sequence number；
First processor determines data syn-chronization priority, including high priority and low priority according to the task grade received；
When task grade is high priority, can select shared storage area in sheet is data exchange zone, if the first core needs to synchronize
Second core, the first core can the corresponding message in more new film internal memory storage area territory, and update message header write sequence number, interrupt the second core to touch
Send out the second core with DMA(Direct Memory Access) mode receives, and the second core judges the read-write sequence number of message header, reception
The message not synchronized the reading sequence number updating message header；If the second core needs to synchronize the first core, step is identical；
When task grade is low priority, can select off-chip shared storage area is data exchange zone, if the first core needs to synchronize
Second core, the first core can update the corresponding message in off-chip storage region, and update the sequence number of writing of message header, and pass through internal interrupt
Second core is to notify the second core synchrodata, and the second core judges the read-write sequence number of message header, receives the message not synchronized and renewal disappears
The reading sequence number of breath head；If the second core needs to synchronize the first core, step is identical；
The step of the data syn-chronization between first processor and the second processor is as follows:
3 FIFO area are opened up, respectively as the first core and first processor with first processor inside the second processor
The second core and public exchange data field；Be respectively used to synchronize A/D sampled data, pair time data and status information；
Second processor determines data syn-chronization priority according to the task grade received, including priority 1, priority 2 and preferential
Level 3；
If first processor needs to synchronize the second processor, then carry out following step:
When task grade is priority 1, the first core of first processor and the second processor carry out interrupting synchronizing；Described interruption is same
The process of step is:
When task grade is priority 2, the second core of first processor and the second processor carry out interrupting synchronizing；
When task grade is priority 3, first processor and the second processor carry out inquiry mode synchronization；
When the second processor receives task and completes to need to synchronize first processor, the data syn-chronization of the second processor after data update
Module performs in state machine mode；If state machine is in idle condition, then enter corresponding synchronous regime according to task priority,
Synchronize first processor according to the corresponding method of synchronization, and etc. after return signal to be synchronized, reenter idle condition；State machine is such as
Fruit is in synchronous regime, then according to task priority, high priority can seize synchronous state machine, can hang up current sync, synchronizes
After end, recover low priority synchronous regime.
The principle of the present invention is: platform architecture is that dual core processor 1 and processor 2, the first core of processor 1 and the second core lead to
Crossing shared drive mode to communicate, be divided into 2 priority by communication response speed, higher priority sync mode is by the first core and the
The dma mode communication of two cores, shares spatial cache in sheet, for data such as the accidents that synchronous exchange real-time is higher；
The low priority method of synchronization is communicated by the internal interrupt mode that the first core and second are internuclear, shares the memory space of off-chip, is used for
The data such as the state variable that synchronous exchange real-time is relatively low.Processor 1 is connected by EMIFA bus with processor 2, the first core
Share EBI with the second core, be divided into 3 priority by real-time communication demand, corresponding to 3 FIFO within processor 2
District, be respectively used to synchronize A/D sampled data, pair time data and status information.Data synchronization mechanism adaptive task priority.
The beneficial effect comprise that: the method for data synchronization using the inventive method to provide, appoint according to relay protection field
The particularity of business priority, data syn-chronization tool validity and real-time, make protective relaying device can timely respond to guidance command, carry
High protective relaying device performance.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with drawings and Examples, the invention will be further described.
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, to this
Bright it is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not used to
Limit the present invention.
As it is shown in figure 1, the processor 1 that the present invention relates to uses OMAP family chip, processor 2 to use XILINX series
Chip.Double-core OMAP chip internal ARM and DSP data syn-chronization two ways: in sheet shared drive dma mode and
The interrupt mode of off-chip shared drive.OMAP chip and fpga chip data syn-chronization have three kinds of modes, and OMAP responds FPGA
According to priority it is divided into: dma mode interrupts DSP, exterior I O interruption ARM, ARM/DSP active inquiry synchronous mark；FPGA
Data syn-chronization according to data syn-chronization priority response OMAP.
Double-core OMAP chip internal ARM and DSP data syn-chronization, it is achieved method is as follows: in sheet, 128K shares and deposits
The circle queue of ARM and DSP is the most all opened up as data exchange zone, queue in storage area territory and off-chip 4M shared storage area
Data structure include that message header and message array, message header record information updating are write sequence number and information updating and read sequence number.If
ARM needs synchronization DS P, according to task hierarchical selection data syn-chronization priority.During high priority, ARM can more new film internal memory
The corresponding message in storage area territory, and update the sequence number of writing of message header, interrupting DSP and receive to trigger its dma mode, DSP judges
The read-write sequence number of message header, receives the message not synchronized the reading sequence number updating message header；During low priority, off-chip 4M can be selected
Space is data exchange zone, and by internal interrupt DSP to notify DSP synchrodata.If DSP needs to synchronize ARM,
Consistent with said method.
The data syn-chronization of OMAP Yu FPGA, it is achieved method is as follows: open up 3 FIFO area inside FPGA, make respectively
For with DSP and ARM and public exchange data field.Between FPGA with OMAP Tong Bu, can be corresponding according to task hierarchical selection
The method of synchronization, DSP with FPGA including priority 1 interrupts Tong Bu, ARM with FPGA of priority 2 interrupts Tong Bu,
The inquiry mode of ARM/DSP with FPGA of priority 3 is Tong Bu.The data simultaneous module of FPGA performs in state machine mode,
It is defaulted as idle condition, when FPGA receives task and completes to need to synchronize OMAP, if state machine is in sky after data update
Not busy state, then enter corresponding synchronous regime according to task priority, synchronizes OMAP data according to the corresponding method of synchronization, and waits
After synchronizing return signal, from newly entering idle condition；If state machine is in synchronous regime, current sync can be hung up, high preferential
Level can seize synchronous state machine, after EOS, recovers low priority synchronous regime.
It should be appreciated that for those of ordinary skills, can be improved according to the above description or be converted, and institute
There are these modifications and variations all should belong to the protection domain of claims of the present invention.
Claims (2)
1. the method for data synchronization for the double-core multiple processor structure of relay protection field; step including the data syn-chronization between the step of the double-core data syn-chronization within first processor and first processor and the second processor; it is characterized in that, the step of the double-core data syn-chronization within first processor is as follows:
In the level cache of first processor, i.e. sheet, shared storage area and the L2 cache of first processor, i.e. off-chip shared storage area open up the circle queue of the first core and the second core respectively as data exchange zone；The data structure of described queue includes that message header and message array, message header record information updating write sequence number and information updating reads sequence number；
First processor determines data syn-chronization priority, including high priority and low priority according to the task grade received；
When task grade is high priority, can select shared storage area in sheet is data exchange zone, if the first core needs to synchronize the second core, first core can the corresponding message in more new film internal memory storage area territory, and update message header write sequence number, interrupting the second core and receive synchrodata to trigger the second core, the second core judges the read-write sequence number of message header, receives the message not synchronized the reading sequence number updating message header；If the second core needs to synchronize the first core, step is identical；
When task grade is low priority, can select off-chip shared storage area is data exchange zone, if the first core needs to synchronize the second core, first core can update the corresponding message in off-chip storage region, and update message header write sequence number, and by internal interrupt the second core to notify the second core synchrodata, the second core judges the read-write sequence number of message header, receive the message not synchronized the reading sequence number updating message header；If the second core needs to synchronize the first core, step is identical；
The step of the data syn-chronization between first processor and the second processor is as follows:
3 FIFO districts are opened up, respectively as the second core and public exchange data field with first core and first processor of first processor inside the second processor；Be respectively used to synchronize A/D sampled data, pair time data and status information；
Second processor determines data syn-chronization priority, including priority 1, priority 2 and priority 3 according to the task grade received；
If first processor needs to synchronize the second processor, then carry out following step:
When task grade is priority 1, the first core of first processor and the second processor carry out interrupting synchronizing；The process that described interruption synchronizes is:
When task grade is priority 2, the second core of first processor and the second processor carry out interrupting synchronizing；
When task grade is priority 3, first processor and the second processor carry out inquiry mode synchronization；
When the second processor receives task and completes to need to synchronize first processor after data update, and the data simultaneous module of the second processor performs in state machine mode；If state machine is in idle condition, then enter corresponding synchronous regime according to task priority, synchronize first processor according to the corresponding method of synchronization, and etc. after return signal to be synchronized, reenter idle condition；If state machine is in synchronous regime, then according to task priority, high priority can seize synchronous state machine, can hang up current sync, after EOS, recovers low priority synchronous regime.
2., according to the method for data synchronization of the double-core multiple processor structure described in claim 1, it is characterised in that when task grade is high priority, when the second core receives synchrodata, the second core is with DMA(Direct
Memory Access) mode receives.
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| CN104536350B (en) * | 2014-12-31 | 2017-04-12 | 浙江中控技术股份有限公司 | Work, standby and preemption type real-time multi-task controller and redundancy synchronous method thereof |
| JP5949977B1 (en) | 2015-02-19 | 2016-07-13 | 日本電気株式会社 | Information processing apparatus, information processing method, main processor core, program, information processing method, sub-processor core |
| CN108572926B (en) * | 2017-03-13 | 2022-02-22 | 阿里巴巴集团控股有限公司 | Method and device for synchronizing caches of central processing units |
| CN111464447B (en) * | 2020-04-08 | 2021-08-13 | 苏州盛科通信股份有限公司 | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips |
| CN112613691B (en) * | 2020-11-09 | 2022-07-29 | 贵州电网有限责任公司 | Chip relay protection universal device |
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| CN101840390A (en) * | 2009-03-18 | 2010-09-22 | 中国科学院微电子研究所 | Hardware synchronous circuit structure suitable for multiprocessor system and implementation method thereof |
| CN102270189A (en) * | 2011-06-17 | 2011-12-07 | 西安电子科技大学 | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system |
| CN102334104A (en) * | 2011-08-15 | 2012-01-25 | 华为技术有限公司 | Synchronous processing method and device based on multicore system |
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| CN101840390A (en) * | 2009-03-18 | 2010-09-22 | 中国科学院微电子研究所 | Hardware synchronous circuit structure suitable for multiprocessor system and implementation method thereof |
| CN102270189A (en) * | 2011-06-17 | 2011-12-07 | 西安电子科技大学 | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system |
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