CN103545215A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103545215A
CN103545215A CN201210247385.2A CN201210247385A CN103545215A CN 103545215 A CN103545215 A CN 103545215A CN 201210247385 A CN201210247385 A CN 201210247385A CN 103545215 A CN103545215 A CN 103545215A
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layer
masking layer
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drain region
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CN103545215B (zh
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朱慧珑
梁擎擎
钟汇才
吴昊
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Institute of Microelectronics of CAS
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Priority to PCT/CN2012/079081 priority patent/WO2014012263A1/zh
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Abstract

本申请公开了一种半导体器件及其制造方法。一示例方法包括：在衬底上依次形成牺牲层和半导体层；在半导体层上形成第一掩蔽层；以第一掩蔽层为掩模，形成进入衬底的开口；经由所述开口，选择性去除至少一部分牺牲层，并在其中填充绝缘体材料；在所述开口中形成源区和漏区之一；在衬底上形成第二掩蔽层；以第二掩蔽层为掩模，形成源区和漏区中另一个；去除第二掩蔽层的一部分；以及形成栅介质层，并在第二掩蔽层的剩余部分的侧壁上以侧墙的形式形成栅导体。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了使用包括高K栅介质和金属栅导体的栅堆叠。为避免栅堆叠的性能退化，包括这种栅堆叠的半导体器件通常利用替代栅工艺来制造。替代栅工艺涉及在栅侧墙之间限定的孔隙中形成高K栅介质和金属栅导体。然而，由于器件尺寸的缩小，要在如此小的孔隙中形成高K栅介质和金属导体越来越困难。
另一方面，在极薄绝缘体上半导体(ET-SOI)衬底上形成的半导体器件具有良好的短沟道效应控制和相对小的随机掺杂剂波动。但是，ET-SOI衬底是昂贵的。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成牺牲层和半导体层；在半导体层上形成第一掩蔽层；以第一掩蔽层为掩模，形成进入衬底的开口；经由所述开口，选择性去除至少一部分牺牲层，并在其中填充绝缘体材料；在所述开口中形成源区和漏区之一；在衬底上形成第二掩蔽层；以第二掩蔽层为掩模，形成源区和漏区中另一个；去除第二掩蔽层的一部分；以及形成栅介质层，并在第二掩蔽层的剩余部分的侧壁上以侧墙的形式形成栅导体。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；位于衬底上的埋入绝缘体层；位于埋入绝缘体层上的半导体层；以及在衬底上形成的源区、漏区和在半导体层上形成的栅堆叠，其中，所述栅堆叠包括：栅介质；和栅导体，所述栅导体以侧墙形式形成于位于栅堆叠一侧的电介质层或者栅侧墙的侧壁上。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-12是示出了根据本公开实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
在常规工艺中，在利用“伪”栅堆叠以及该伪栅堆叠两侧的侧墙在衬底中制造出源区和漏区之后，保留两侧的侧墙而在侧墙之间限定出孔隙，通过填充孔隙来形成真正的栅堆叠。与此不同，在本公开中，提出了一种“替代侧墙”工艺。在形成源区和漏区之后，保留在源区和漏区之一一侧存在的材料层，并在该保留的材料层的侧壁上以侧墙的形式形成栅堆叠(特别是，栅导体)。从而可以在较大的空间(具体地，大致为栅区+源区和漏区中另一个的区域)上来形成栅堆叠，相比于仅在侧墙之间的小孔隙中形成栅堆叠的常规工艺，可以使得工艺更加容易进行。
根据本发明的实施例，可以利用掩蔽层来在衬底上的有源区中形成源区和漏区。具体地，例如可以利用第一掩蔽层来掩蔽有源区，露出有源区的一部分，可以对该部分进行处理以形成源区和漏区之一。另外，可以利用第二掩蔽层来掩蔽有源区，露出有源区的另一部分，可以对该另一部分进行处理以形成源区和漏区中另一个。
第一和第二掩蔽层可以按各种方式来形成，只要它们能够掩蔽有源区并露出有源区的相应部分，从而在源/漏形成工艺中充当掩模。另外，第二掩蔽层可以包括第一掩蔽层的一部分。
在如上所述形成源区和漏区之后，可以对第二掩蔽层进行构图，以去除第二掩蔽层的一部分，从而进一步露出有源区的又一部分。可以在露出的该又一部分上来形成栅堆叠。例如，栅堆叠可以通过侧墙工艺来形成。为了便于第二掩蔽层的构图，第二掩蔽层优选地包括由不同材料构成的若干部分，这些部分中的至少一些相对于彼此可以具有刻蚀选择性，从而可以选择性去除其中的一些部分。
另外，在本公开中，可以利用牺牲层来限定埋入绝缘体层。例如，在衬底上可以依次形成牺牲层和半导体层。然后，形成开口以露出牺牲层，并选择性去除牺牲层的至少一部分。通过在由于去除牺牲层而形成的空腔中填充绝缘体材料，来形成埋入绝缘体层。
这种埋入绝缘体的形成可以与替代侧墙工艺相结合。例如，可以以第一掩蔽层为掩模，来形成开口，并经由所述开口形成埋入绝缘体层。然后，通过在该开口中形成(例如，通过外延生长)半导体材料，来形成源区或漏区。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底100。该衬底100可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底100上，例如可以通过外延生长，依次形成牺牲层102和半导体层104。牺牲层102例如可以包括SiGe(Ge原子百分比例如为约10％-30％)，厚度为约10-50nm。半导体层104可以包括与衬底100相同或不同的材料；在本示例中包括Si，厚度为约5-30nm。
在衬底100上，可以形成有浅沟槽隔离(STI)106，用以隔离单独器件的有源区。STI 106例如可以包括氧化物(例如，氧化硅)。这里需要指出的是，在以下描述的示例中，为方便说明，仅描述了形成单个器件的情况。但是本公开不局限于此，而是可以应用于形成两个或更多器件的情况。
可选地，在半导体层104的表面上例如通过沉积形成一薄氧化物层(未示出)。该氧化物层例如具有5-10nm的厚度，可以在随后用来形成界面层(IL)。
接着，如图2所示，在半导体层104上例如通过沉积形成厚度约为100-200nm的第一掩蔽层108。例如，第一掩蔽层108可以包括氮化物(例如，氮化硅)，且可以通过例如反应离子刻蚀(RIE)被构图为覆盖有源区的一部分(该部分大致对应于随后形成的源区或漏区以及沟道区部分)。此时，可以进行源/漏形成工艺，来在该露出的有源区部分中形成源区和漏区之一。
具体地，可以以第一掩蔽层108为掩模，通过选择性刻蚀，来形成延伸进入衬底100的开口110。这种选择性刻蚀例如可以通过TMAH、KOH、EDP、N2H4·H2O溶液对半导体层104(例如，Si)和牺牲层102(例如，SiGe)进行各向异性刻蚀来完成。
由于开口110的形成，露出了牺牲层102。根据本公开的一实施例，可以通过以绝缘体材料将牺牲层102(全部或部分地)替代，来形成埋入绝缘体层，以便进一步改善器件性能。具体地，如图3所示，可以经由开口100，通过湿法刻蚀，相对于衬底100和半导体层104(例如，Si)选择性刻蚀牺牲层102(例如，SiGe)，来至少部分地去除牺牲层102，从而形成空隙(该空隙与开口在图3中一起示出为110′)。优选地，该空隙延伸超过要形成的栅区到达另一侧的源区或漏区。然后，如图4所示，例如可以通过再生长(例如，通过在氧气气氛中氧化)或沉积(例如，化学气相淀积(CVD))来形成氧化物并进行回蚀，来在空隙中填充绝缘体材料112(在该示例中为氧化物)。
然后，如图5所示，在开口100中例如通过外延生长形成源区和漏区之一114。例如，源区和漏区之一114可以包括与半导体层104不同成分的半导体材料，从而例如由于两者之间的晶格常数不同而在将要在半导体层104中形成的沟道区中产生应力。对于p型器件，源/漏区114可以带压应力；而对于n型器件，源/漏区114可以带拉应力。例如，在半导体层104包括Si的情况下，对于p型器件，源/漏区114可以包括SiGe(例如，Ge原子百分比为约15-75％)；而对于n型器件，源/漏区114可以包括Si:C(例如，C原子百分比为约0.2-2％)。在外延生长源/漏区114的同时，可以进行原位掺杂，以将其掺杂为相应的导体类型。
本领域技术人员可以想到多种方式来形成这种带应力的源/漏区，在此不再赘述。
当然，本公开不限于形成带应力的源/漏区。例如，可以在开口110中通过外延生长形成与半导体层104相同的半导体材料(例如，Si)并通过相应的掺杂来形成源/漏区。
接下来，如图6所示，在衬底100上形成第二子掩蔽层116。第二子掩蔽层116例如可以包括氧化物(如氧化硅)。然后可以进行平坦化处理例如化学机械抛光(CMP)，以露出第一掩蔽层108，以便随后进行处理。
随后，如图7所示，可以通过相对于第二子掩蔽层116(例如，氧化硅)，选择性刻蚀第一掩蔽层108(例如，氮化硅)，以去除第一掩蔽层108。这种选择性刻蚀例如可以通过湿法刻蚀(例如，热磷酸)或者通过湿法/RIE组合刻蚀来进行。
此时，根据本公开的一实施例，可以以第二子掩蔽层116为掩模，进行阱注入(如图7中的箭头所示)，以在埋入绝缘体层112下方的衬底100中形成非对称阱118。这里需要指出的是，图7中的虚线框118仅仅是为了图示方便而示出为规则的矩形形状。实际上，阱118的形状由注入工艺决定，并且可能没有明确的边界。这种非对称阱118可以有效地方式器件的穿通(punch-through)效应，并可以减小带间泄漏(band-to-band leakage)。这里需要指出的是，阱118的形成对于最终的半导体器件而言并非是必要的。
然后，如图8所示，在第二子掩蔽层116的侧壁上可以形成侧墙120。例如，侧墙120被形成为具有约8-30nm的宽度，以覆盖有源区的一部分(该部分大致对应于随后形成的栅区)。侧墙120例如可以包括氮化物(例如，氮化硅)。存在多种手段来形成侧墙，在此不对侧墙的形成进行详细描述。
这样，第二子掩蔽层116和侧墙120(构成“第二掩蔽层”)露出了有源区的一部分。此时，可以第二掩蔽层为掩模进行源/漏形成工艺，来在该露出的有源区部分中形成源区和漏区中另一个。
根据本公开的一实施例，可以形成带应力的源/漏区，以改善器件性能。具体地，如图9所示，以第二掩蔽层(116+120)为掩模，对半导体层104、(由于延伸超过栅区)可能存在的绝缘体材料112、可能存在的牺牲层102的剩余部分以及衬底100进行选择性刻蚀，来形成延伸进入衬底100的开口122。例如，可以通过TMAH溶液，对半导体层104(例如，Si)进行各向异性刻蚀；然后，可以通过RIE，对可能存在的绝缘体材料112(例如，氧化物)进行刻蚀；随后，可以利用TMAH溶液进行，对可能存在的牺牲层102和衬底100各向异性刻蚀。然后，如图10所示，在开口122中例如通过外延生长形成源区和漏区中另一个124。例如，源/漏区124可以包括与半导体层104不同成分的半导体材料，从而例如由于两者之间的晶格常数不同而在将要在半导体层104中形成的沟道区中产生应力。对于p型器件，源/漏区124可以带压应力；而对于n型器件，源/漏区124可以带拉应力。例如，在半导体层104包括Si的情况下，对于p型器件，源/漏区124可以包括SiGe(例如，Ge原子百分比为约15-75％)；而对于n型器件，源/漏区124可以包括Si:C(例如，C原子百分比为约0.2-2％)。在外延生长源/漏区114的同时，可以进行原位掺杂，以将其掺杂为相应的导体类型。
本领域技术人员可以想到多种方式来形成这种带应力的源/漏区，在此不再赘述。
当然，本公开不限于形成带应力的源/漏区。例如，可以在开口122中通过外延生长形成与半导体层104相同的半导体材料(例如，Si)并通过相应的掺杂来形成源/漏区。
随后，可以通过选择性刻蚀，去除第二掩蔽层的一部分。例如，侧墙120(例如，氮化硅)可以通过热磷酸来选择性去除。这样，就在第二子掩蔽层116的一侧留下了较大的空间(大致对应于栅区+所述源区和漏区中另一个的区域)，从而可以容易地进行栅堆叠的形成。
然后，如图11所示，形成栅堆叠。具体地，例如可以通过沉积形成栅介质层126。例如，栅介质层126可以包括高K栅介质材料如HfO2，厚度可以为约2-4nm。在栅介质层130上，可以以侧墙的形式形成栅导体130。在形成栅导体时，例如可以通过控制侧墙形成工艺中的参数如沉积厚度、RIE参数等，使得所形成的侧墙形式的栅导体130宽度为约10-35nm，从而基本上位于下方已经形成的源区和漏区之间。例如，栅导体130可以包括金属栅导体材料如Ti、Co、Ni、Al、W及其合金等。优选地，在栅介质层126和栅导体130之间还可以形成功函数调节层128。功函数调节层128例如可以包括TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTa、NiTa、MoN、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSi、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx及其组合，厚度可以约为2-10nm。图11中示出的栅介质层126和功函数调节层128是以栅导体130为掩模进行选择性刻蚀后的形式。
此后，如图12所示，可以通过沉积形成层间电介质层132，并进行平坦化处理如CMP。层间电介质层132可以包括氧化物(例如，氧化硅)、氮化物或其组合。然后，可以形成与源区和漏区相对应的接触部136。接触部136例如可以包括金属如W、Cu等。根据一实施例，为了增强接触，还可以在源区和漏区中形成金属硅化物层134，从而接触部136通过金属硅化物层134与源区和漏区接触。金属硅化物层134例如可以包括NiPtSi。存在多种手段来形成金属硅化物层134和接触部136，在此不再赘述。
这样，就得到了根据本公开实施例的示例半导体器件。如图12所示，该半导体器件形成在衬底+埋入绝缘体层+半导体层的结构(类似于SOI衬底)上，包括源区和漏区(114、124)以及栅堆叠(126，128，130)。埋入绝缘体层112可以包括夹于源区和漏区之间的空腔中的绝缘体材料，这种空腔例如是通过牺牲层来限定的。栅堆叠，尤其是其中的栅导体130，以侧墙的形式形成于栅堆叠一侧(图12中的左侧)的掩蔽层(或者说，电介质层)116的侧壁上。源区和漏区114、124可以带应力。在本发明的一个实施例中，该半导体器件还可以包括环绕栅堆叠的栅侧墙结构。在本公开的一个实施例中，该半导体器件还可以包括在衬底中形成的非对称阱118，所述非对称阱远离栅堆叠所述一侧(图12中的左侧)的源区或漏区延伸。在本发明的一个实施例中，该非对称阱位于源区，从而能够有效避免器件穿透以及减少带-带之间的漏电流。
这里需要指出的是，本公开的第一掩蔽层和第二掩蔽层的形式和形成方式不限于以上示例。例如，第一掩蔽层并非如图2所示那样露出图中左侧的有源区部分，而是可以露出图中右侧的有源区部分。另外，在图6所示的结构中，可以并非完全去除第一掩蔽层，而是可以在第二子掩蔽层的侧壁上留下一部分第一掩蔽层，类似于图8所示的侧墙(这种示例下，不能形成图7所示的非对称阱)。另外，在图10所示的结构中，可以并非完全去除侧墙，而是可以在第二子掩蔽层的侧壁上留下侧墙的一部分，这一部分侧墙例如可以充当随后形成的栅堆叠的栅侧墙。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (15)

1.一种制造半导体器件的方法，包括：
在衬底上依次形成牺牲层和半导体层；
在半导体层上形成第一掩蔽层；
以第一掩蔽层为掩模，形成进入衬底的开口；
经由所述开口，选择性去除至少一部分牺牲层，并在其中填充绝缘体材料；
在所述开口中形成源区和漏区之一；
在衬底上形成第二掩蔽层；
以第二掩蔽层为掩模，形成源区和漏区中另一个；
去除第二掩蔽层的一部分；以及
形成栅介质层，并在第二掩蔽层的剩余部分的侧壁上以侧墙的形式形成栅导体。
2.根据权利要求1所述的方法，其中，形成第二掩蔽层的操作包括：
在衬底上形成第二子掩蔽层，并平坦化以露出第一掩蔽层；
去除第一掩蔽层；以及
在第二子掩蔽层的侧壁上形成侧墙，
其中，所述第二子掩蔽层和侧墙构成所述第二掩蔽层。
3.根据权利要求2所述的方法，在去除第一掩蔽层之后，以及在第二子掩蔽层的侧壁上形成侧墙之前，还包括：
以第二子掩蔽层为掩模，进行阱注入。
4.根据权利要求2所述的方法，其中，去除第二掩蔽层的一部分包括：
去除所述侧墙的至少一部分。
5.根据权利要求1所述的方法，其中，在所述开口中形成源区和漏区之一包括：
在所述开口中外延生长能够在半导体层中施加应力的半导体材料。
6.根据权利要求5所述的方法，其中，形成源区和漏区中另一个包括：
以第二掩蔽层为掩模，形成进入衬底的另一开口；以及
在所述另一开口中外延生长能够在半导体层中施加应力的所述半导体材料。
7.根据权利要求2所述的方法，其中，
第一掩蔽层包括氮化物；
第二子掩蔽层包括氧化物；以及
侧墙包括氮化物。
8.一种半导体器件，包括：
衬底；
位于衬底上的埋入绝缘体层；
位于埋入绝缘体层上的半导体层；以及
在衬底上形成的源区、漏区和在半导体层上形成的栅堆叠，
其中，所述栅堆叠包括：
栅介质；和
栅导体，所述栅导体以侧墙形式形成于位于栅堆叠一侧的电介质层或者栅侧墙的侧壁上。
9.根据权利要求8所述的半导体器件，其中，埋入绝缘体层包括夹于源区和漏区之间的空腔中的绝缘体材料。
10.根据权利要求8所述的半导体器件，其中，源区和漏区分别包括：延伸至衬底、能够在半导体层中施加应力的半导体材料填充部。
11.根据权利要求8所述的半导体器件，还包括：
在衬底中形成的非对称阱，所述非对称阱远离栅堆叠所述一侧的源区或漏区延伸。
12.根据权利要求9所述的半导体器件，其中，衬底和半导体层包括Si，牺牲层包括SiGe。
13.根据权利要求10所述的半导体器件，其中，半导体材料填充部包括SiGe或Si:C。
14.根据权利要求9所述的半导体器件，其中，绝缘体材料包括氧化物。
15.根据权利要求8所述的半导体器件，还包括：设置在栅介质层和栅导体之间的功函数调节层。
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