CN103531535A - 一种修复超低介质常数薄膜侧壁损伤的方法 - Google Patents

一种修复超低介质常数薄膜侧壁损伤的方法 Download PDF

Info

Publication number
CN103531535A
CN103531535A CN201310525014.0A CN201310525014A CN103531535A CN 103531535 A CN103531535 A CN 103531535A CN 201310525014 A CN201310525014 A CN 201310525014A CN 103531535 A CN103531535 A CN 103531535A
Authority
CN
China
Prior art keywords
dielectric constant
constant film
ultralow dielectric
repairing
ultralow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310525014.0A
Other languages
English (en)
Other versions
CN103531535B (zh
Inventor
曾绍海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Original Assignee
Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Integrated Circuit Research and Development Center Co Ltd filed Critical Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority to CN201310525014.0A priority Critical patent/CN103531535B/zh
Publication of CN103531535A publication Critical patent/CN103531535A/zh
Priority to PCT/CN2014/084099 priority patent/WO2015062331A1/zh
Priority to US14/758,307 priority patent/US9337017B2/en
Application granted granted Critical
Publication of CN103531535B publication Critical patent/CN103531535B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02101Cleaning only involving supercritical fluids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/0231Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to electromagnetic radiation, e.g. UV light
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/1052Formation of thin functional dielectric layers
    • H01L2221/1057Formation of thin functional dielectric layers in via holes or trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本发明公开了一种修复超低介质常数薄膜侧壁损伤的方法,包括在半导体衬底上沉积超低介质常数薄膜;干法刻蚀所述超低介质常数薄膜以在其中形成侧壁结构;采用含-CH3的不饱和烃的化学药液进行湿法清洗;以及进行紫外线照射。本发明能够修复超低介质常数薄膜侧壁的损伤,从而恢复超低介质常数薄膜中的孔径和孔隙率,使有效介质常数保持最小。

Description

一种修复超低介质常数薄膜侧壁损伤的方法
技术领域
本发明涉及半导体集成电路领域,特别涉及一种修复超低介质侧壁损伤的处理方法。
背景技术
在半导体集成电路工业中,高性能的集成电路芯片需要尽可能低的连线电容电阻的信号延迟和信号串扰,为此,需要在低电阻率的铜金属线以及连线的层间及线间填充低介质常数材料来达到降低寄生电容,从而达到提高器件的目的。近十年来,半导体工业界对超低介质常数材料的研究日益增多,在集成电路工艺中,超低介质常数材料必须满足诸多条件,例如:足够的机械强度以支撑多层连线的架构,高杨氏系数,高击穿电压,低漏电,高热稳定性,良好的粘合强度,低吸水性,低薄膜应力,高平坦化能力,低热张系数以及化学机械抛光工艺的兼容性等。
掺杂碳和微孔均是降低介电常数k值的有效手段,目前45nm以下技术,普遍采用的超低介质常数介质材料是掺碳的多孔氧化硅薄膜,形成Si-C键。其中,掺杂碳的二氧化硅介电常数与密度呈线性关系,密度的降低有利于K值得降低;微孔材料的介电常数与材料密度和孔隙率有关,孔隙率越高K值越小。
然而,随着介质材料介质常数不断降低的要求,介电材料的孔隙率和含碳量不断增加,结构变得越来越疏松。在后续干法刻蚀工艺过程中,刻蚀过程中的等离子(plasma)会在侧壁处把Si-C键破坏,随后的湿法清洗中使用的化学品药液都是含-OH的基团,这些-OH会取代Si-C中的C,形成Si-OH,从而使超低介质常数(ULK)的孔隙率降低,孔直径减小,从而导致介质常数K的增加;同时,由于-OH容易吸附空气中的水汽等杂质,在后续工艺温度下,容易消耗超低介质(ULK)中的Si,在导致介质常使K值升高的同时,使特征尺寸CD变大。
发明内容
本发明的主要目的在于提供一种修复超低介质常数薄膜侧壁损伤的方法,能够修复超低介质常数薄膜由于刻蚀带来的侧壁损伤而导致的介电常数升高,保持刻蚀后关键尺寸CD不会增大,同时该工艺和现有业界工艺兼容。
为达成上述目的,本发明提供一种修复超低介质常数薄膜侧壁损伤的方法,该方法包括如下步骤:在半导体衬底上沉积超低介质常数薄膜,所述超低介质常数薄膜为掺碳的多孔氧化硅薄膜;干法刻蚀所述超低介质常数薄膜以在其中形成侧壁结构;采用含-CH3的不饱和烃的化学药液进行湿法清洗,所述含-CH3的不饱和烃与所述超低介质常数薄膜中的硅形成Si-O-C(Re)x;以及进行紫外线照射,以使Si-O-C(Re)x中的O-C键断裂,而形成–Si(CH3)3的物质。
可选的,所述湿法清洗的温度为20~40摄氏度,清洗时间为15秒~80秒。
可选的,所述紫外线照射的温度为380~500摄氏度,照射时间为10秒~25秒。
可选的,所述紫外线照射在氢气环境中进行,所述氢气的流量为80sccm~120sccm。
可选的,所述超低介质常数薄膜通过等离子增强化学气相沉积而成。
可选的,所述等离子增强化学气相沉积的反应气体为甲基二乙氧基硅烷和氧气,腔体温度为350~480摄氏度;直流功率为350~600瓦。
可选的,所述侧壁结构为所述大马士革结构的通孔及沟槽的侧壁。
本发明一种修复超低介质常数薄膜侧壁损伤的方法的有益效果在于,能够恢复超低介质常数薄膜(ULK)中的孔径和孔隙率,使有效介质常数(K值)保持最小。此外本发明所采用的湿法化学品选择性强、实现成本低;所用的在外线照射设备能和现有设备兼容。
附图说明
图1本发明一实施例的修复超低介质常数薄膜侧壁损伤的方法的流程图。
图2A~图2C是本发明一实施例的修复超低介质常数薄膜侧壁损伤的方法的剖面示意图。
具体实施方式
为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例,本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。此外,本发明利用示意图进行了详细的表述,在详述本发明实例时,为了便于说明,示意图不依照一般比例局部放大,不应以此作为对本发明的限定。
请参考图1,本发明提供的修复超低介质常数薄膜侧壁损伤的方法包括以下步骤:
步骤S01:在半导体衬底上沉积超低介质常数薄膜;
步骤S02:干法刻蚀所述超低介质常数薄膜以在其中形成侧壁结构;
步骤S03:采用含-CH3的不饱和烃的化学药液进行湿法清洗;
步骤S02:进行紫外线照射(UV-cure)。
接下来将结合图2A~图2C详述本发明修复超低介质常数薄膜侧壁损伤的过程。
首先,请参考图2A,首先在半导体衬底上沉积超低介质常数薄膜,其中超低介质常数薄膜101为掺碳的多孔氧化硅薄膜,其可通过等离子增强化学气相沉积(PECVD)在半导体衬底100上淀积而成,反应气体为甲基二乙氧基硅烷(DEMS)和氧气(O2),腔体温度为350~480摄氏度;反应直流功率为350~600瓦。
接下来,参考图2B,通过干法刻蚀在超低介质常数薄膜101中形成一侧壁结构,在本实施例中是通过业界通用的干法刻蚀的方法在超低介质常数薄膜101中刻出一个大马士革结构102;大马士革结构的形成方法为本领域技术人员所熟知,在此不作赘述。在刻蚀过程中等离子体(plasma)会在超低介质常数薄膜101的侧壁(即大马士革结构102的通孔及沟槽的侧壁)处把掺碳的多孔氧化硅的Si-C键破坏。
然后采用含-CH3的不饱和烃的化学药液进行湿法清洗,清洗温度为20~40摄氏度,清洗时间为15秒~80秒。此时,含-CH3的不饱和烃会取代已经被破坏的Si-C键中的C,与Si形成Si-O-C(Re)x。
请继续参考图2C,对上述结构进行紫外照射(UV-cure),其中紫外线照射的温度为380~500摄氏度,照射时间为10秒~25秒。本实施例中,紫外线照射在氢气(H2)环境中进行,氢气的流量为80sccm~120sccm。经紫外线照射后,紫外线光强的能量将使得Si-O-C(Re)x中的O-C键断裂,而形成–Si(CH3)3的物质,如下式所示
从而Si-O-Si的环状增加,恢复超低介质常数薄膜(ULK)中的孔径和孔隙率,使有效介质常数(K值)保持最小。
在完成上述步骤后,可继续执行形成CMOS器件的铜后道的其他工艺,这些工艺步骤可以采用本领域技术人员所熟悉的方法形成,在此不作赘述。
综上所述,相较于现有技术,本发明的修复超低介质常数薄膜侧壁损伤的方法能够恢复超低介质常数薄膜(ULK)中的孔径和孔隙率,使有效介质常数(K值)保持最小;且采用的湿法刻蚀的化学药液选择性强、实现成本低;进行紫外线照射的设备也能够和现有设备兼容。因此,本发明所提供的修复超低介质侧壁损伤的制备方法,制作简单,易于集成,且与CMOS工艺具有很好的兼容性,具有很大的应用价值。
虽然本发明已以较佳实施例揭示如上,然所述诸多实施例仅为了便于说明而举例而已,并非用以限定本发明,本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰,本发明所主张的保护范围应以权利要求书所述为准。

Claims (7)

1.一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述方法包括以下步骤:
在半导体衬底上沉积超低介质常数薄膜,所述超低介质常数薄膜为掺碳的多孔氧化硅薄膜;
干法刻蚀所述超低介质常数薄膜以在其中形成侧壁结构;
采用含-CH3的不饱和烃的化学药液进行湿法清洗,所述含-CH3的不饱和烃与所述超低介质常数薄膜中的硅形成Si-O-C(Re)x;以及
进行紫外线照射,以使Si-O-C(Re)x中的O-C键断裂,而形成–Si(CH3)3的物质。
2.根据权利要求1所述的一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述湿法清洗的温度为20~40摄氏度,清洗时间为15秒~80秒。
3.根据权利要求1所述的一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述紫外线照射的温度为380~500摄氏度,照射时间为10秒~25秒。
4.根据权利要求1所述的一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述紫外线照射在氢气环境中进行,所述氢气的流量为80sccm~120sccm。
5.根据权利要求1所述的一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述超低介质常数薄膜通过等离子增强化学气相沉积而成。
6.根据权利要求5所述的一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述等离子增强化学气相沉积的反应气体为甲基二乙氧基硅烷和氧气,腔体温度为350~480摄氏度;直流功率为350~600瓦。
7.根据权利要求1所述的一种修复超低介质常数薄膜侧壁损伤的方法,其特征在于,所述侧壁结构为大马士革结构的通孔及沟槽的侧壁。
CN201310525014.0A 2013-10-30 2013-10-30 一种修复超低介质常数薄膜侧壁损伤的方法 Active CN103531535B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310525014.0A CN103531535B (zh) 2013-10-30 2013-10-30 一种修复超低介质常数薄膜侧壁损伤的方法
PCT/CN2014/084099 WO2015062331A1 (zh) 2013-10-30 2014-08-11 一种修复超低介电常数薄膜侧壁损伤的方法
US14/758,307 US9337017B2 (en) 2013-10-30 2014-08-11 Method for repairing damages to sidewalls of an ultra-low dielectric constant film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310525014.0A CN103531535B (zh) 2013-10-30 2013-10-30 一种修复超低介质常数薄膜侧壁损伤的方法

Publications (2)

Publication Number Publication Date
CN103531535A true CN103531535A (zh) 2014-01-22
CN103531535B CN103531535B (zh) 2018-10-16

Family

ID=49933432

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310525014.0A Active CN103531535B (zh) 2013-10-30 2013-10-30 一种修复超低介质常数薄膜侧壁损伤的方法

Country Status (3)

Country Link
US (1) US9337017B2 (zh)
CN (1) CN103531535B (zh)
WO (1) WO2015062331A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015062331A1 (zh) * 2013-10-30 2015-05-07 上海集成电路研发中心有限公司 一种修复超低介电常数薄膜侧壁损伤的方法
CN104979275A (zh) * 2014-04-04 2015-10-14 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6441499B2 (ja) * 2015-10-28 2018-12-19 東京エレクトロン株式会社 基板処理方法、基板処理装置、基板処理システム及び記憶媒体

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100261349A1 (en) * 2006-10-30 2010-10-14 Novellus Systems, Inc. Uv treatment for carbon-containing low-k dielectric repair in semiconductor processing
CN102074500A (zh) * 2009-11-12 2011-05-25 诺发***有限公司 半导体处理中用于k恢复及表面清洁的紫外线及还原处理
US20130098869A1 (en) * 2011-10-20 2013-04-25 Se-Hwan Yu Method for Forming Minute Pattern and Method for Forming Minute Pattern Mask

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7314828B2 (en) * 2005-07-19 2008-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Repairing method for low-k dielectric materials
US8465991B2 (en) * 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US20090263977A1 (en) * 2008-04-16 2009-10-22 Rogojina Elena V Selective functionalization of doped group iv surfaces using lewis acid/lewis base interaction
CN102324400A (zh) * 2011-09-28 2012-01-18 上海华力微电子有限公司 铜互连结构的制作方法
CN103531535B (zh) 2013-10-30 2018-10-16 上海集成电路研发中心有限公司 一种修复超低介质常数薄膜侧壁损伤的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100261349A1 (en) * 2006-10-30 2010-10-14 Novellus Systems, Inc. Uv treatment for carbon-containing low-k dielectric repair in semiconductor processing
CN102074500A (zh) * 2009-11-12 2011-05-25 诺发***有限公司 半导体处理中用于k恢复及表面清洁的紫外线及还原处理
US20130098869A1 (en) * 2011-10-20 2013-04-25 Se-Hwan Yu Method for Forming Minute Pattern and Method for Forming Minute Pattern Mask

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015062331A1 (zh) * 2013-10-30 2015-05-07 上海集成电路研发中心有限公司 一种修复超低介电常数薄膜侧壁损伤的方法
US9337017B2 (en) 2013-10-30 2016-05-10 Shanghai Ic R&D Center Co., Ltd Method for repairing damages to sidewalls of an ultra-low dielectric constant film
CN104979275A (zh) * 2014-04-04 2015-10-14 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法
CN104979275B (zh) * 2014-04-04 2020-03-10 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法

Also Published As

Publication number Publication date
US9337017B2 (en) 2016-05-10
CN103531535B (zh) 2018-10-16
WO2015062331A1 (zh) 2015-05-07
US20150340227A1 (en) 2015-11-26

Similar Documents

Publication Publication Date Title
KR102494277B1 (ko) 유동성 유전체 재료들을 이용한 트렌치 격리를 위한 기법들
JP2009016672A (ja) 半導体装置の製造方法、半導体装置、半導体製造装置及び記憶媒体。
US20050158884A1 (en) Method Of In-Situ Treatment of Low-K Films With a Silylating Agent After Exposure to Oxidizing Environments".
CN102142393B (zh) 互连结构的形成方法
WO2006025500A1 (ja) 半導体装置の製造方法およびこれを用いて形成された半導体装置
US20110097821A1 (en) Method for tunably repairing low-k dielectric damage
CN104282619B (zh) 硅通孔的形成方法
CN103531535A (zh) 一种修复超低介质常数薄膜侧壁损伤的方法
KR20080110521A (ko) 저유전율 절연막의 데미지 회복 방법 및 반도체 장치의제조 방법
CN103871961B (zh) 互连结构及其制造方法
CN101901781A (zh) 处理方法
CN104979271A (zh) 互连结构的形成方法
CN105336674B (zh) 互连结构及其形成方法
CN102623395A (zh) 一种低介电常数薄膜表面处理方法
CN102903667B (zh) 半导体器件的形成方法
CN104134630A (zh) 一种减少超低介质常数薄膜侧壁损伤的方法
CN103426745B (zh) 半导体结构的形成方法
US7393795B2 (en) Methods for post-etch deposition of a dielectric film
CN103531531B (zh) 一种用于制造半导体器件的方法
CN103474342A (zh) 修复介质层损伤的方法
CN105720005B (zh) 超低k介质层的形成方法
CN100369234C (zh) 形成半导体装置的方法
CN105304554B (zh) 互连结构的形成方法
KR101632513B1 (ko) 광 보조 프로세스에서 손상 감소를 위한 시스템 및 방법
WO2010067395A1 (ja) 半導体装置の製造方法及びその製造装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant