CN103531467A - Semiconductor device and forming method thereof - Google Patents

Semiconductor device and forming method thereof Download PDF

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Publication number
CN103531467A
CN103531467A CN201210225965.1A CN201210225965A CN103531467A CN 103531467 A CN103531467 A CN 103531467A CN 201210225965 A CN201210225965 A CN 201210225965A CN 103531467 A CN103531467 A CN 103531467A
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Prior art keywords
semiconductor device
fin structure
semiconductor substrate
formation method
groove
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CN201210225965.1A
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CN103531467B (en
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宋化龙
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Abstract

The present invention provides a semiconductor device and a forming method thereof, wherein the method comprises the following steps: providing a semiconductor substrate; defining a groove through a lithography process and etching the semiconductor substrate for forming a groove; forming a silicon oxide layer which covers the semiconductor substrate; eliminating partial silicon oxide layer in the groove and exposing partial semiconductor substrate; forming a semiconductor layer on the exposed semiconductor substrate; and etching the silicon oxide layer for forming a fin structure and an insulating structure for insulating the fin structure; wherein, by means of the groove which is defined through the lithography process, the section width is larger than the section width of the subsequently formed insulating structure, thereby reducing requirement to the lithography process.

Description

Semiconductor device and forming method thereof
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of semiconductor device and forming method thereof.
Background technology
Since integrated circuit invention, its performance steadily improves always.The raising of performance is mainly to realize by constantly dwindling the size of integrated circuit (IC)-components.At present, the characteristic size of integrated circuit (IC)-components (as MOSFET) has narrowed down to nanoscale.Under this yardstick, the various basic restrictions with actual start to occur, make the development that is based upon the integrated circuit technique on silicon planar CMOS technology just suffer unprecedented challenge.It is generally acknowledged, through great efforts, CMOS technology is still likely advanced to even 10 nm technology node of 20 nanometers, but after tens nanometer nodes, traditional planar CMOS technology will be difficult to further develop, and new technology must produce in good time.In the middle of proposed various new technologies, multiple-grid MOS device technology is considered to be hopeful most the technology being applied after tens nanometer nodes.Compare with tradition list gate device, multiple-grid device has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
At present, the fin FET in many grate MOS devices (Fin Field Effect Transistor) can be realized by conventional silicon planar CMOS technique because of its self-alignment structure, thereby becomes most promising many grate MOS devices.
In the forming process of fin FET, the formation of fin structure is a very important technical process wherein.Please refer to Fig. 1 a～1e, the generalized section of device in its forming process that is existing fin structure.
As shown in Figure 1a, provide Semiconductor substrate 10, in described Semiconductor substrate 10, be formed with hard mask layer 11.
As shown in Figure 1 b, utilize photoetching process definition isolation channel, hard mask layer 11 and Semiconductor substrate 10 described in etching, form isolation channel 12.
As shown in Fig. 1 c, fill described isolation channel 12, form isolation channel packed layer 13.
As shown in Figure 1 d, described isolation channel packed layer 13 is carried out back to carving technology, form isolation structure 14.
As shown in Fig. 1 e, remove hard mask layer 11, form fin structure 15.
In the forming process of above-mentioned fin structure, need to use photoetching process definition isolation channel, this isolation channel is the isolated area of adjacent two fin structures, its cross-sectional width equals the cross-sectional width of described isolation structure, and along with the continuous pursuit to integrated circuit (IC)-components performance, it is more and more less that this isolation channel size also will become, utilize the isolation channel size that photoetching process need to define will become more and more less, thus, photoetching process has been proposed to great challenge.
Therefore,, in the ever-reduced situation of integrated circuit (IC)-components size, how to have reduced to will hoping for success of photoetching process a major issue that more and more perplexs people.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device and forming method thereof, to reduce the requirement to photoetching process.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising:
Semiconductor substrate is provided;
Utilize photoetching process definition groove, Semiconductor substrate forms groove described in etching;
Form the silicon oxide layer that covers described Semiconductor substrate;
Remove the partial oxidation silicon layer in described groove, expose part semiconductor substrate;
In the Semiconductor substrate of exposing, form semiconductor layer;
Silicon oxide layer described in etching, forms fin structure and isolates the isolation structure of described fin structure.
Optionally, in the formation method of described semiconductor device, the cross-sectional width of described groove is the cross-sectional width sum of one or more fin structure and a plurality of isolation structures.
Optionally, in the formation method of described semiconductor device, the cross-sectional width of described groove is the cross-sectional width sum of a fin structure and two isolation structures.
Optionally, in the formation method of described semiconductor device, the thickness of described semiconductor layer is identical with the degree of depth of described groove.
Optionally, in the formation method of described semiconductor device, the material of described Semiconductor substrate is silicon or germanium silicon.
Optionally, in the formation method of described semiconductor device, utilize epitaxy technique to form described semiconductor layer.
Optionally, in the formation method of described semiconductor device, the material of described semiconductor layer is silicon or germanium silicon.
Optionally, in the formation method of described semiconductor device, silicon oxide layer described in etching, after forming fin structure and isolating the isolation structure of described fin structure, also comprises: described fin structure is carried out to annealing process.
Optionally, in the formation method of described semiconductor device, utilize hydrogen to carry out annealing process to described fin structure.
Optionally, in the formation method of described semiconductor device, utilize hydrogen and argon gas to carry out annealing process to described fin structure.
Optionally, in the formation method of described semiconductor device, utilize dry etch process to remove the partial oxidation silicon layer in described groove, expose part semiconductor substrate.
Accordingly, the present invention also provides a kind of formed semiconductor device of formation method of above-mentioned semiconductor device, comprising:
Semiconductor substrate;
Be formed at the fin structure in described Semiconductor substrate; And
The isolation structure of isolating described fin structure.
In semiconductor device provided by the invention and forming method thereof, utilize the defined groove of photoetching process, its cross-sectional width is greater than the cross-sectional width of the isolation structure of follow-up formation, has reduced thus the requirement to photoetching process.
Accompanying drawing explanation
Fig. 1 a～1e is the generalized section of device in the forming process of existing fin structure;
Fig. 2 is the schematic flow sheet of formation method of the semiconductor device of the embodiment of the present invention;
Fig. 3 a～3f is the generalized section of device in the formation method of semiconductor device of the embodiment of the present invention.
Embodiment
Semiconductor device the present invention being proposed below in conjunction with the drawings and specific embodiments and forming method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, the schematic flow sheet of the formation method of its semiconductor device that is the embodiment of the present invention.As shown in Figure 2, the formation method of described semiconductor device comprises the steps:
S20: Semiconductor substrate is provided;
S21: utilize photoetching process definition groove, Semiconductor substrate forms groove described in etching;
S22: form the silicon oxide layer that covers described Semiconductor substrate;
S23: remove the partial oxidation silicon layer in described groove, expose part semiconductor substrate;
S24: form semiconductor layer in the Semiconductor substrate of exposing;
S25: silicon oxide layer described in etching, forms fin structure and isolate the isolation structure of described fin structure.
Concrete, please refer to Fig. 3 a～3f, the generalized section of device in the formation method of its semiconductor device that is the embodiment of the present invention.
As shown in Figure 3 a, provide Semiconductor substrate 30, the material of described Semiconductor substrate 30 can be silicon, germanium silicon.In the present embodiment, in described Semiconductor substrate 30, be formed with hard mask layer 31, the material of described hard mask layer 31 can be silicon nitride, and described hard mask layer 31 can form by chemical vapor deposition method.In other embodiments of the invention, in described Semiconductor substrate 30, also can form photoresist layer, utilize photoresist layer as the mask layer of subsequent etching technique.
Then, as shown in Figure 3 b, utilize photoetching process definition groove, Semiconductor substrate 30 forms grooves 300 described in etching.Concrete, can first utilize photoetching process to form the hard mask layer of patterning, the hard mask layer of this patterning exposes part semiconductor substrate 30; Then, the Semiconductor substrate 30 that etching exposes forms groove 300 in described Semiconductor substrate 30.In the present embodiment, the degree of depth of described groove 300 is 50nm～800nm, and in other embodiments of the invention, the degree of depth of described groove 300 also can be less than 50nm or be greater than 800nm, and the application does not limit this.
At this, the cross-sectional width of the defined groove 300 of described photoetching process is greater than the cross-sectional width of the isolation structure of follow-up formation.This point, the subsequent descriptions by present specification will be clearer.In the formation method at semiconductor device provided by the invention, utilize the cross-sectional width of the defined groove 300 of photoetching process to be greater than the cross-sectional width of the isolation structure of follow-up formation, thereby reduced the dimension precision requirement of photoetching process, reduced the requirement to photoetching process.
Then, as shown in Figure 3 c, form silicon oxide layer 32, described silicon oxide layer 32 covers described Semiconductor substrate 30.That is, described silicon oxide layer 32 covers the surface of described Semiconductor substrate 30, and certainly, described silicon oxide layer 32 has covered the surface of the Semiconductor substrate 30 of exposing in described groove 300.Concrete, described silicon oxide layer 32 can form by semiconductor technologies such as chemical vapor deposition methods.
Then, as shown in Figure 3 d, remove the partial oxidation silicon layer 32 in described groove 300, expose part semiconductor substrate 30.Preferably, by dry etch process, remove the partial oxidation silicon layer 32 in described groove 300, at this, utilize the anisotropic properties of dry etch process, can avoid the use to mask plate, thereby reduce process costs.Wherein, the etching gas of described dry etch process can be Cl 2, O 2, CF 4deng etching gas, the application does not limit this.Certainly, in other embodiments of the invention, also can remove the partial oxidation silicon layer 32 in described groove 300 by wet-etching technology.
Then, as shown in Figure 3 e, in the Semiconductor substrate 30 of exposing, form semiconductor layer 33.Easy to know, at this, in the Semiconductor substrate 30 of exposing, form semiconductor layer 33, namely at the interior formation semiconductor layer 33 of groove 300.Wherein, the material of described semiconductor layer 33 is silicon or germanium silicon.Preferably, utilize epitaxy technique to form described semiconductor layer 33, by epitaxy technique, can access the lattice semiconductor layer 33 identical with described Semiconductor substrate 30 of arranging, thereby improve the performance of formed integrated circuit (IC)-components.Certainly, in other embodiments of the invention, also can form described semiconductor layer 33 by depositing operation.
In the present embodiment, the thickness of described semiconductor layer 33 is identical with the degree of depth of described groove 300, and the thickness of described semiconductor layer 33 is 50nm～800nm.Seen in Fig. 3 e, described semiconductor layer 33 is positioned at same plane with the highest face temperature of described Semiconductor substrate 30, thus, makes the fin structure homogeneity of follow-up formation better, thereby has guaranteed the performance of formed integrated circuit (IC)-components.
Further, in the present embodiment, form semiconductor layer 33 in the Semiconductor substrate 30 of exposing after, also can carry out chemical mechanical milling tech to described semiconductor layer 33, silicon oxide layer 32 and hard mask layer 31, thereby make better described semiconductor layer 33 and the highest face temperature of described Semiconductor substrate 30 be positioned at same plane, further improve the homogeneity of the fin structure of follow-up formation.
Then,, as shown in Fig. 3 f, silicon oxide layer 32 described in etching, forms fin structure 34 and isolates the isolation structure 35 of described fin structure 34.At this, can to described silicon oxide layer 32, carry out etching by wet-etching technology, remove the silicon oxide layer 32 of segment thickness, and by remaining silicon oxide layer isolation fin structure 34.
Visible by foregoing description, in the present embodiment, the cross-sectional width of the groove 300 defining by photoetching process is the cross-sectional width sum of a fin structure 34 and two isolation structures 35, as can be seen here, with respect to prior art, in the formation method of semiconductor device provided by the present invention, the required device size defining of photoetching process is larger, thereby has reduced the requirement for photoetching process.
In addition, it should be noted that, in an embodiment of the present invention, the cross-sectional width of the groove 300 defining by photoetching process is the cross-sectional width sum of a fin structure 34 and two isolation structures 35, and in other embodiments of the invention, the cross-sectional width of the groove of described photoetching process definition can be the cross-sectional width sum of a plurality of fin structures and a plurality of isolation structures, and the application does not limit this.Certainly, under latter event, conventionally need to re-use photoetching process one time, the cross-sectional width of the groove of this photoetching process definition is for the second time the cross-sectional width sum of a fin structure and two isolation structures.
In prior art, directly by photoetching process, define the device of required formation, the present invention proposes a kind of diverse thinking, by the combination of photoetching process and deposition/growth technique, thereby relative raising the required device size defining of photoetching process, reduced the requirement of photoetching process.
Preferably, after forming fin structure 34 and isolating the isolation structure 35 of described fin structure 34, described fin structure 34 is carried out to annealing process processing, to repair the fin structure lattice damage bringing at aforementioned etching and grinding technics, and repair out-of-flatness or the wedge angle on fin structure surface, make fin structure outer surface Paint Gloss; The gas that described annealing adopts can be hydrogen (H 2) or argon gas (Ar), also or, adopt separately hydrogen (H 2) carry out annealing process, the temperature range of described annealing is for example 800 ℃～1000 ℃.
Please continue to refer to Fig. 3 f, by above-mentioned technique, formed semiconductor device 3, described semiconductor device 3 comprises:
Semiconductor substrate 30 ';
Be formed at the fin structure 34 in described Semiconductor substrate 30 '; And
The isolation structure 35 of isolating described fin structure 34.
At this, described Semiconductor substrate 30 ' is for having passed through etching technics and having removed as remaining part semiconductor substrate 30 after fin structure 34.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection range of claims.

Claims (12)

1. a formation method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided;
Utilize photoetching process definition groove, Semiconductor substrate forms groove described in etching;
Form the silicon oxide layer that covers described Semiconductor substrate;
Remove the partial oxidation silicon layer in described groove, expose part semiconductor substrate;
In the Semiconductor substrate of exposing, form semiconductor layer;
Silicon oxide layer described in etching, forms fin structure and isolates the isolation structure of described fin structure.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the cross-sectional width of described groove is the cross-sectional width sum of one or more fin structure and a plurality of isolation structures.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the cross-sectional width of described groove is the cross-sectional width sum of a fin structure and two isolation structures.
4. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the thickness of described semiconductor layer is identical with the degree of depth of described groove.
5. the formation method of the semiconductor device as described in any one in claim 1～4, is characterized in that, the material of described Semiconductor substrate is silicon or germanium silicon.
6. the formation method of semiconductor device as claimed in claim 5, is characterized in that, utilizes epitaxy technique to form described semiconductor layer.
7. the formation method of semiconductor device as claimed in claim 6, is characterized in that, the material of described semiconductor layer is silicon or germanium silicon.
8. the formation method of the semiconductor device as described in any one in claim 1～4, is characterized in that, silicon oxide layer described in etching, after forming fin structure and isolating the isolation structure of described fin structure, also comprises: described fin structure is carried out to annealing process.
9. the formation method of semiconductor device as claimed in claim 8, is characterized in that, utilizes hydrogen to carry out annealing process to described fin structure.
10. the formation method of semiconductor device as claimed in claim 8, is characterized in that, utilizes hydrogen and argon gas to carry out annealing process to described fin structure.
The formation method of 11. semiconductor device as described in any one in claim 1～4, is characterized in that, utilizes dry etch process to remove the partial oxidation silicon layer in described groove, exposes part semiconductor substrate.
The formed semiconductor device of formation method of 12. semiconductor device as described in any one in claim 1～11, is characterized in that, comprising:
Semiconductor substrate;
Be formed at the fin structure in described Semiconductor substrate; And
The isolation structure of isolating described fin structure.
CN201210225965.1A 2012-07-02 2012-07-02 Semiconductor device and forming method thereof Active CN103531467B (en)

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Cited By (1)

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CN109037402A (en) * 2018-07-25 2018-12-18 湘能华磊光电股份有限公司 The lithographic method of graphical sapphire substrate

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