CN103530246A - FPGA data managing system - Google Patents

Abstract

The invention relates to an FPGA data managing system which comprises an interrupt detection unit, an interrupt message queue, an interrupt response processing unit, a bus switch and a data cache zone. An FPGA is externally connected with multiple paths of AD converters. The interrupt detection unit completes detection of external interrupt signals and latch of channel numbers. The interrupt message queue is used for storing external interrupt channel numbers and responds according to the principle of first come, first process. The interrupt response processing unit is responsible for executing specific interrupt tasks. The bus switch is responsible for connecting a bus of the interrupt response processing unit and a responded channel bus. The data cache zone is used for storing data read from an external bus when the interrupt response processing unit executes the interrupt processing tasks. According to the FPGA data managing system, multiple peripheral interrupts of the same prior level can be processed in time and data errors or system faults caused by imbalance interrupt response are avoided.

Description

A kind of FPGA data management system

Technical field

The present invention relates to a kind of FPGA data management system.

Background technology

FPGA claims again field programmable gate array.It is a kind of programmable logic device (PLD), as a kind of semi-custom circuit in special IC field, occurs.Both solve the deficiency of custom circuit, overcome again the limited shortcoming of original programming device gate circuit.FPGA has can repeat to revise design, the fast remarkable advantage of travelling speed.Its general design that adopts hardware description language (verilog or VHDL) completing circuit, the comprehensive and placement-and-routing through specific purpose tool, forms binary file.The binary file of producing powers on and can automatically move after being burned onto on FPGA.

Because FPGA adopts the method for software programming, realize hardware circuit design, so adopt FPGA to carry out design circuit, there is very large dirigibility.For a specific function, adopt FPGA to realize than adopting the software on application specific processor to realize, maximum advantage is speed.Adopt the functional circuit of FPGA realization, can give full play of the advantage of concurrent working, and response speed can reach below 10 nanoseconds.And the function that adopts software to realize, work that can only serial, and response speed is generally at the delicate even Millisecond of hundreds of.So in modern electronic system design, it is more and more that FPGA applies.

In the application system based on FPGA, sometimes can utilize FPGA to manage a plurality of external interrupt.Traditional management method is the method adopting based on priority poll, and each is interrupted arranging fixing priority, carries out successively poll.This method is reliable and stable, but need to may can not be processed in time because of the unbalanced external interrupt that makes of interrupting processing the system of external event response in time improper for some, causes external data to lose or the system failure.Proposition of the present invention is exactly in order to address this problem, and makes a plurality of external interrupt of equal priority can be processed in time, has avoided because the unbalanced data of bringing of interrupt response are made mistakes or the system failure.

summary of the invention

The object of the present invention is to provide a kind of FPGA data management system, it makes a plurality of external interrupt of equal priority can be processed in time, has avoided because the unbalanced data of bringing of interrupt response are made mistakes or the system failure.

Technical solution of the present invention is:

A data management system, its special character is:

At FPGA, comprise interconnective interruption detecting unit, interrupt message queue, interrupt response processing unit, bus switch and data buffer; Described interruption detecting unit completes the detection of external interrupt signal and latching of channel number; The external multi-channel A/D converter of described FPGA;

Described interrupt message queue is used for storing external interrupt channel number, guarantees to respond according to the principle of interrupting first processing first;

Described interrupt response processing unit is responsible for carrying out concrete interrupt task;

Described bus switch is responsible for the bus of interrupt response processing unit to be connected with the channel bus being responded;

Described data buffer is used for depositing interrupt response processing unit and carries out the data that read from external bus while interrupting Processing tasks.

Above-mentioned FPGA data management system, is characterized in that: when the external multi-channel A/D converter of FPGA, particularly

1) interrupt detection and the record that detecting unit is responsible for external interrupt signal, the channel information of external interrupt is deposited in interrupt message queue;

2) when interrupting detecting unit, detect after the look-at-me of outside any one passage, in interrupt message queue, deposit current channel number in;

3) when storage channels, according to the principle of first depositing first, sequentially carry out, guarantee to record accurately the sequencing that interrupts generation;

4) in interrupt response processing unit pass-along message, this message queue is according to the principle of first in first out, guarantees that the interruption first occurring first processes;

5) interrupt response processing unit is carried out concrete interrupt task processing, according to different application scenarios, can design different functions, for the designed hardware platform of the present invention, reads exactly the data in AD conversion, and is written in data buffer;

6) channel number that bus switch transmits out according to message queue, carries out the multichannel of bus and selects to switch, and guarantees that the data bus of interrupt response processing unit is connected with the data bus of the AD ALT-CH alternate channel that will be responded.

Tool of the present invention has the following advantages:

1, interruption processing speed is fast.Than traditional employing software, carry out handling interrupt task, the processing that adopts FPGA to carry out task has the shorter response time.Software handling interrupt task all will be processed and three processes of popping through stacked, task at every turn, and on general processor, this process, switching time can be longer if carry out task under operating system substantially all at Microsecond grade at present.And the present invention does not have stacked and two processes of popping completely, and task handles all-pass and crosses hardware and realize, and the task processing time can reach nanosecond.This is very useful in high real-time system.

2, interrupt response is balanced in time.The classic method that adopts FPGA management interrupt task is that the polling method based on priority manages, this method is to each task fixing priority of arranging in advance, then according to this order poll check successively, there is interruption to process, do not interrupt continuing poll check.This method can cause larger poll time waste.And the present invention is first response first to the thinking of interrupt response, there is no the process of poll, thereby guarantee the corresponding in time of interrupt task.

Accompanying drawing explanation

Fig. 1 is the system logic block diagram of the present invention while realizing in FPGA.

Embodiment

For solving existing employing FPGA, manage the unbalanced problem that a plurality of equal priority are interrupted, it is example that the hardware platform of the external 4 road high-speed A/D converters of FPGA is take in the present invention, introduces the method that realizes multitask real-time management in FPGA.This management method can be generalized to other occasions that adopts FPGA to carry out real-time multi-task management, such as the serial ports of the external multichannel of FPGA, and the external multichannel CAN bus of FPGA, etc.

The implementation method of the present invention in FPGA is referring to Fig. 1.Enforcement of the present invention depends on five basic modules: interrupt detecting unit, interrupt message queue, interrupt response processing unit, bus switch and data buffer.

Interrupt detecting unit and complete the detection of external interrupt, and corresponding channel number is latched into interrupt message queue.The corresponding synchronizer of each interrupt source and a decision device.Synchronizer circuit adopts secondary d type flip flop to carry out the synchronous of signal, and the signal metastable state problem with erasure signal when the cross clock domain, guarantees that signal is by reliable samples.Latch circuit is used for latching current look-at-me, passes to passage memory circuit.When external interrupt signal is a pulse signal, after latch, can become a level signal, guarantee that look-at-me can not be missed sampling.Passage is adjudicated the responsible look-at-me that each latch is latched of memory circuit and is judged, the channel number corresponding to useful signal carries out record, is written in interrupt message queue.

Interrupt message queue is mainly realized by a FIFO.After each channel number that sends look-at-me is latched, according to the precedence occurring, be written in FIFO, when guaranteeing in commission to break task, can carry out according to the principle of first processing first.

Bus switch adopts one group of MUX to realize, the selection input signal of this MUX is exactly the channel number of interrupt message queue output, according to this channel number, in bus switch inside, carry out bus switch, the bus that the bus of interrupt response processing unit is corresponding with channel number is connected.

Interrupt response processing unit is responsible for carrying out concrete interrupt task processing capacity, and this task function is realized by state machine.The hardware platform mentioned for the present invention reads exactly the data after conversion, and leaves in the storage area of formulating in data buffer from AD converter.According to different application systems, specific tasks may be different, but task treatment scheme substantially all can be abstract reads and the large state of inner storage administration two for the external interface of data.

Claims (2)

1. a FPGA data management system, is characterized in that:

At FPGA, comprise interconnective interruption detecting unit, interrupt message queue, interrupt response processing unit, bus switch and data buffer; Described interruption detecting unit completes the detection of external interrupt signal and latching of channel number; The external multi-channel A/D converter of described FPGA;

Described interrupt message queue is used for storing external interrupt channel number, guarantees to respond according to the principle of interrupting first processing first;

Described interrupt response processing unit is responsible for carrying out concrete interrupt task;

Described bus switch is responsible for the bus of interrupt response processing unit to be connected with the channel bus being responded;

Described data buffer is used for depositing interrupt response processing unit and carries out the data that read from external bus while interrupting Processing tasks.

2. FPGA data management system according to claim 1, is characterized in that: when the external multi-channel A/D converter of FPGA, particularly

1) interrupt detection and the record that detecting unit is responsible for external interrupt signal, the channel information of external interrupt is deposited in interrupt message queue;

2) when interrupting detecting unit, detect after the look-at-me of outside any one passage, in interrupt message queue, deposit current channel number in;

3) when storage channels, according to the principle of first depositing first, sequentially carry out, guarantee to record accurately the sequencing that interrupts generation;

4) in interrupt response processing unit pass-along message, this message queue is according to the principle of first in first out, guarantees that the interruption first occurring first processes;

5) interrupt response processing unit is carried out concrete interrupt task processing, according to different application scenarios, can design different functions, for the designed hardware platform of the present invention, reads exactly the data in AD conversion, and is written in data buffer;

6) channel number that bus switch transmits out according to message queue, carries out the multichannel of bus and selects to switch, and guarantees that the data bus of interrupt response processing unit is connected with the data bus of the AD ALT-CH alternate channel that will be responded.

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