CN103500710A - 一种薄膜晶体管制作方法、薄膜晶体管及显示设备 - Google Patents
一种薄膜晶体管制作方法、薄膜晶体管及显示设备 Download PDFInfo
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Abstract
本发明公开了一种薄膜晶体管制作方法、薄膜晶体管及显示设备,涉及显示技术,在有源层材料的迁移率大于设定阈值时,为避免有源层迁移率高而导致漏电流大,对有源层进行离子注入,增大有源层表面的离子化合键的能量,从而减少空位形成的几率及降低载流子浓度,降低有源层表面的迁移率,进而降低漏电流,调节阀值电压向正方向移动,提高薄膜晶体管性能。
Description
技术领域
本发明涉及显示技术,尤其涉及一种薄膜晶体管制作方法、薄膜晶体管及显示设备。
背景技术
目前,AMOLED(Active Matrix/Organic Light Emitting Diode,有源矩阵有机发光二极管显示面板)是利用设置在电致发光片上下的两片电极产生的电流强度的变化,改变电致发光层的发光效果,从而控制发光来改变显示图像的。一般来讲,一块完整的AMOLED显示面板包括OLED构件和TFT(Thin FilmTransistor,薄膜晶体管)阵列。其中TFT开关包括栅极、源极、漏极和有源层;栅电极连接OLED的金属电极,源极连接数据线,漏极连接OLED像素电极,有源层形成在源极、漏极与栅极之间。
目前的AMOLED TFT中,为提高像素电极充电率,减少响应时间,需要尽量提高有源层的迁移率,例如,在进行TFT制作时,可以使用氮氧化锌等材料作为有源层。
但是,在使用迁移率高的材料作为有源层时,由于过大的迁移率,容易导致漏电流过大和阈值电压向负偏移大,影响TFT性能。
发明内容
本发明实施例提供一种薄膜晶体管制作方法、薄膜晶体管及显示设备,以解决使用迁移率高的材料作为有源层时,漏电流过大和阈值电压向负偏移大的问题。
本发明实施例提供的一种薄膜晶体管制作方法,包括:
通过有源层材料形成迁移率大于设定阈值的有源层图案;
对有源层图案进行离子注入,其中,所注入的离子形成的化合键的能量大于所述有源层材料中离子形成的化合键的能量。
通过对有源层进行离子注入,增大化合键的能量,减少空位形成的几率及降低载流子浓度,降低有源层表面的迁移率,进而降低漏电流,调节阀值电压向正方向移动,提高薄膜晶体管性能。
进一步,为防止离子注入对有源层图案表面造成影响,所述对有源层图案进行离子注入前,还包括:
在所述有源层图案上形成刻蚀阻挡层图案;
在所述刻蚀阻挡层图案和所述有源层图案上形成源漏极图案。
更进一步,所述对有源层图案进行离子注入前,还包括:
在所述刻蚀阻挡层图案和所述源漏极图案上形成保护层。
较佳的,所述保护层具体为:
SiOx,SiN的组合层。
进一步,所述通过有源层材料形成迁移率大于设定阈值的有源层图案前,还包括:
在基板上形成栅极图案;
在所述栅极图案和基板上形成栅极绝缘层;
此时,所述通过有源层材料形成迁移率大于设定阈值的有源层图案,具体为:
在所述栅极绝缘层上通过迁移率大于设定阈值的有源层材料形成有源层图案。
较佳的,所述有源层材料具体为:
氮氧化锌。
更佳的,所注入的离子具体为:
镓离子或铝离子。
本发明实施例还提供一种薄膜晶体管,包括有源层图案,所述有源层图案的材料的迁移率大于设定阈值,且:
所述有源层图案的表面掺杂有设定离子,所述设定离子形成的化合键的能量大于所述有源层材料中离子形成的化合键的能量。
本发明实施例还提供一种薄膜晶体管,通过本发明实施例提供的薄膜晶体管制作方法制作。
本发明实施例还提供一种显示设备,包括本发明实施例提供的薄膜晶体管。
本发明实施例提供一种薄膜晶体管制作方法、薄膜晶体管及显示设备,在有源层材料的迁移率大于设定阈值时,为避免有源层迁移率高而导致漏电流大,对有源层进行离子注入,增大有源层表面的离子化合键的能量,从而减少空位形成的几率及降低载流子浓度,降低有源层表面的迁移率,进而降低漏电流,调节阀值电压向正方向移动,提高薄膜晶体管性能。
附图说明
图1为本发明实施例提供的薄膜晶体管制作方法流程图;
图2为本发明实施例提供的较具体的薄膜晶体管制作方法流程图;
图3a为本发明实施例提供的薄膜晶体管制作过程中,形成栅极图案后的薄膜晶体管结构示意图;
图3b为本发明实施例提供的薄膜晶体管制作过程中,形成栅极绝缘层后的薄膜晶体管结构示意图;
图3c为本发明实施例提供的薄膜晶体管制作过程中,形成有源层图案后的薄膜晶体管结构示意图;
图3d为本发明实施例提供的薄膜晶体管制作过程中,形成刻蚀阻挡层图案后的薄膜晶体管结构示意图;
图3e为本发明实施例提供的薄膜晶体管制作过程中,形成源漏极图案后的薄膜晶体管结构示意图;
图3f为本发明实施例提供的薄膜晶体管制作过程中,形成保护层后的薄膜晶体管结构示意图;
图3g为本发明实施例提供的薄膜晶体管制作过程中进行离子注入的示意图;
图3h为本发明实施例提供的薄膜晶体管结构示意图。
具体实施方式
本发明实施例提供一种薄膜晶体管制作方法、薄膜晶体管及显示设备,在有源层材料的迁移率大于设定阈值时,为避免有源层迁移率高而导致漏电流大,对有源层进行离子注入,增大有源层表面的离子化合键的能量,从而减少空位形成的几率及降低载流子浓度,降低有源层表面的迁移率,进而降低漏电流,调节阀值电压向正方向移动,提高薄膜晶体管性能。
如图1所示,本发明实施例提供的薄膜晶体管制作方法,包括:
步骤S101、通过有源层材料形成迁移率大于设定阈值的有源层图案;通常,在沉积迁移率大于设定阈值的有源层材料后,进行掩膜和刻蚀即可得到相应的有源层图案;
步骤S102、对有源层图案进行离子注入,其中,所注入的离子形成的化合键的能量大于有源层材料中离子形成的化合键的能量。
离子注入的方式有很多,例如,可以使得离子源产生离子束,由引出缝将离子束引入靶室向靶片注入离子,本领域技术人员也可以通过其他方式来实现离子注入。
在对有源层图案进行离子注入后,有源层图案的表面迁移率降低,底层的迁移率仍然较高,实现了降低漏电流,调节阀值电压向正方向移动,提高薄膜晶体管性能。
通常,在迁移率大于30cm2/Vs时,即可认为迁移率较大,需要对有源层图案进行离子注入。所注入的离子形成的化合键的能量大于有源层材料中离子形成的化合键的能量时,即可减少有源层材料中的空位和载流子浓度,进而降低有源层图案的表面迁移率。
例如,当使用氮氧化锌作为有源层材料时,氮氧化锌的迁移率为100cm2/Vs,氮氧化锌中提供载流子的位置(free carrier)是氮空位,而N-Ga(氮镓键)和N-Al(氮铝键)的能量都高于N-Zn(氮锌键),所以使用Ga(镓)或者Al(铝)进行掺杂会使得氮氧化锌中氮空位的形成更加困难,进而降低其迁移率。
或者,当使用IGZO(铟镓锌氧)或者ITZO(铟锡锌氧)作为有源层材料时,提供载流子的位置是氧空位,由于O-Ga(氧镓键)和O-Al(氧铝键)的能量都高于O-Zn(氧锌键),所以也可以使用Ga(镓)或者Al(铝)进行掺杂,进而降低IGZO或者ITZO的迁移率。
为了防止离子注入时,对有源层图案的表面造成破坏,可以在形成有源层图案后,先在有源层图案上形成刻蚀阻挡层图案,并在刻蚀阻挡层图案和有源层图案上形成源漏极图案,再对有源层进行离子注入,由于所注入的离子能量较高,所以可以透过刻蚀阻挡层图案实现对有源层图案表面的离子注入。
此时,在步骤S102前,还包括:
在有源层图案上形成刻蚀阻挡层图案;
在刻蚀阻挡层图案和有源层图案上形成源漏极图案。
进一步,为防止离子注入影响TFT性能,对有源层进行离子注入前,还包括:
在刻蚀阻挡层图案和源漏极图案上形成保护层。
该保护层可以使用SiOx(氧化硅)和SiNx(氮化硅)的组合层实现,同样的,由于所注入的离子能量较高,所以可以透过保护层和刻蚀阻挡层图案实现对有源层图案表面的离子注入,同时,也避免了离子注入过程中,离子对有源层图案表面的轰击。
通常情况下,在有源层图案下,还设置有栅极和栅极绝缘层,此时,步骤S101中,通过有源层材料形成迁移率大于设定阈值的有源层图案前,还包括:
在基板上形成栅极图案;
在栅极图案和基板上形成栅极绝缘层;
此时,步骤S101中,通过有源层材料形成迁移率大于设定阈值的有源层图案,具体为:
在栅极绝缘层上通过迁移率大于设定阈值的有源层材料形成有源层图案。
具体的,如图2所示,本发明实施例提供的较具体的薄膜晶体管制作方法包括:
步骤S201、在基板上形成栅极图案,具体的,可以通过磁控溅射的方式沉积栅极材料,再对栅极材料进行图形化处理,进行曝光、显影、刻蚀和剥离工艺实现栅极图形化,其中,栅极材料可以为Mo(钼)、Al(铝)等金属,形成栅极图案后的薄膜晶体管如图3a所示;
步骤S202、在栅极图案和基板上形成栅极绝缘层,其中,栅极绝缘层可以时单层或多层的SiOx或SiNx(氮化硅),形成栅极绝缘层后的薄膜晶体管如图3b所示;
步骤S203、在栅极绝缘层上通过有源层材料形成有源层图案,具体的,可以在栅极绝缘层上沉积氮氧化锌,并对其进行图形化处理,形成有源层图案,形成有源层图案后的薄膜晶体管如图3c所示;
步骤S204、在有源层图案上形成刻蚀阻挡层图案,具体的,可以是在有源层图案上沉积刻蚀阻挡层材料并进行图形化处理,形成刻蚀阻挡层图案后的薄膜晶体管如图3d所示;
步骤S205、在刻蚀阻挡层图案和有源层图案上形成源漏极图案,具体的,可以是沉积源漏极材料并进行图形化处理,形成源漏极图案后的薄膜晶体管如图3e所示;
步骤S206、在刻蚀阻挡层图案和源漏极图案上形成保护层,该保护层可以是SiOx和SiNx的组合层,形成保护层后的薄膜晶体管如图3f所示;
步骤S207、对有源层图案进行离子注入,如图3g所示。
由于注入离子的能量较高,可透过保护层和刻蚀阻挡层注入到有源层图案的表面,使得有源层包括掺杂Ga或者Al离子的顶层和氮氧化锌底层,离子注入后的薄膜晶体管如图3h所示。
本发明实施例还相应提供一种薄膜晶体管,包括有源层图案,其中,有源层图案的材料的迁移率大于设定阈值,且:
有源层图案的表面掺杂有设定离子,设定离子形成的化合键的能量大于有源层材料中离子形成的化合键的能量。
本发明实施例还相应提供一种薄膜晶体管,通过本发明实施例提供的薄膜晶体管制作方法制作。
本发明实施例还相应提供一种显示设备,包括本发明实施例提供的薄膜晶体管。
本发明实施例提供一种薄膜晶体管制作方法、薄膜晶体管及显示设备,在有源层材料的迁移率大于设定阈值时,为避免有源层迁移率高而导致漏电流大,对有源层进行离子注入,增大有源层表面的离子化合键的能量,从而减少空位形成的几率及降低载流子浓度,降低有源层表面的迁移率,进而降低漏电流,调节阀值电压向正方向移动,提高薄膜晶体管性能。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种薄膜晶体管制作方法,其特征在于,包括:
形成迁移率大于设定阈值的有源层图案;
对有源层图案进行离子注入,其中,所注入的离子形成的化合键的能量大于所述有源层材料中离子形成的化合键的能量。
2.如权利要求1所述的方法,其特征在于,所述对有源层图案进行离子注入前,还包括:
在所述有源层图案上形成刻蚀阻挡层图案;
在所述刻蚀阻挡层图案和所述有源层图案上形成源漏极图案。
3.如权利要求2所述的方法,其特征在于,所述对有源层图案进行离子注入前,还包括:
在所述刻蚀阻挡层图案和所述源漏极图案上形成保护层。
4.如权利要求3所述的方法,其特征在于,所述保护层具体为:
SiOx,SiNx的组合层。
5.如权利要求1所述的方法,其特征在于,所述通过有源层材料形成迁移率大于设定阈值的有源层图案前,还包括:
在基板上形成栅极图案;
在所述栅极图案和基板上形成栅极绝缘层;
所述通过有源层材料形成迁移率大于设定阈值的有源层图案,具体为:
在所述栅极绝缘层上通过迁移率大于设定阈值的有源层材料形成有源层图案。
6.如权利要求1所述的方法,其特征在于,所述有源层材料具体为:
氮氧化锌。
7.如权利要求1或6所述的方法,其特征在于,所注入的离子具体为:
镓离子或铝离子。
8.一种薄膜晶体管,包括有源层图案,其特征在于,所述有源层图案的材料的迁移率大于设定阈值,且,
所述有源层图案的表面掺杂有设定离子,所述设定离子形成的化合键的能量大于所述有源层材料中离子形成的化合键的能量。
9.一种薄膜晶体管,其特征在于,通过如权利要求1-7任一所述的方法制作。
10.一种显示设备,其特征在于,包括如权利要求8或9所述的薄膜晶体管。
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US9711653B2 (en) | 2017-07-18 |
WO2015051650A1 (zh) | 2015-04-16 |
CN103500710B (zh) | 2015-11-25 |
US20150349140A1 (en) | 2015-12-03 |
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