CN103491607A - Design method for TD-LTE digital trunk time-division switch - Google Patents

Abstract

The invention discloses a design method for a TD-LTE digital trunk time-division switch. The design method comprises the following steps of carrying out main synchronizing signal detection on a received signal according to a slippage correlation basis principle, obtaining a main synchronizing signal serial number and 5ms time slot boundary information, carrying out cyclic prefix detection and auxiliary synchronizing signal detection on the received signal, obtaining a cyclic prefix type, an auxiliary synchronizing signal serial number, 10ms frame boundary information and a physical cellular identity, estimating and correcting frequency deviations, carrying out setting according to the 10ms frame boundary information and obtaining the time-division switch. The design method is suitable for FPGA hardware implementation and can effectively achieve search processing of the TD-LTE time-division switch; while a digital trunk and a cell achieve synchronous time and frequency, a main synchronizing signal, an auxiliary synchronizing signal and a cyclic prefix are detected, correct detection probability is high, and operation complexity is low. The design method for the TD-LTE digital trunk time-division switch can be widely applied to the communications industry.

Description

A kind of method for designing of the time-division switching for the TD-LTE digital junction

Technical field

The present invention relates to the communications field, relate in particular to a kind of method for designing of the time-division switching for the TD-LTE digital junction.

Background technology

Along with rise and the development of mobile Internet business and broadband services, third generation partner program has designed the Long Term Evolution standard of universal mobile telecommunications system.LTE will become in future the wide-band mobile communication technology of main flow.The introducing of LTE relay transmission technology is the requirement that high rate data transmission in order to meet next generation mobile communication system and immanent wireless signal cover.The LTE terminal must obtain Target Cell Identifier and descending timing and carrier frequency synchronization by cell search process, can the demodulation broadcast channel obtain system information and set up communication link, so be a vital physical layer procedure in the search of LTE system small area.In the implementation procedure of Cell searching, need a large amount of real-time operation amounts to process, consume the hardware handles resource, the raising of restriction terminal capabilities.Yet existing technology is tended to the Cell searching of UE terminal, in realization and be not suitable for FPGA hardware and realize.

Summary of the invention

In order to solve the problems of the technologies described above, to the purpose of this invention is to provide a kind of FPGA of being applicable to hardware and realize, and realize fast a kind of method for designing of the time-division switching for the TD-LTE digital junction that the time-division switching search is processed

The technical solution adopted in the present invention is:

A kind of method for designing of the time-division switching for the TD-LTE digital junction comprises the following steps:

A, according to slip dependency basis present principles, carry out to received signal the master sync signal detection, obtain master sync signal sequence numbering and 5ms boundary of time slot information;

B, carry out Cyclic Prefix detection and auxiliary synchronous signals to received signal and detect, obtain cyclic prefix type during, auxiliary synchronous signals sequence numbering, 10ms boundary information and Physical Cell Identifier;

C, frequency departure is estimated and proofreaied and correct;

D, according to the 10ms boundary information, arranged and obtained time-division switching.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described steps A comprises:

A1, reception signal carry out sync correlation with three groups of local primary sequence respectively;

The sync correlation result that A2, basis obtain, obtain master sync signal sequence numbering and 5ms boundary of time slot information.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described steps A 1 comprises:

Each data sequence of A11, reception signal is carried out 128 rear cumulative computings of first multiplying each other with three groups of local master sync signal sequences respectively, obtains the correlation computations result of three groups of corresponding local master sync signal sequences;

A12, according to the correlation computations result of three groups of corresponding local master sync signal sequences, obtain the maximal correlation peak value of three groups of local master sync signal sequences of three correspondences, and record data sequence that the maximal correlation peak value is corresponding in the position that receives signal.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described steps A 2 comprises:

A21, calculate respectively the mean value of the correlation computations result of three groups of corresponding local master sync signal sequences, obtain the threshold value of three groups of local master sync signal sequences of three correspondences;

A22, maximal correlation peak value and the threshold value of the same local master sync signal sequence of correspondence are compared, according to comparative result, draw the master sync signal sequence numbering, and and then obtain 5ms boundary of time slot information.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step B comprises:

B1, according to the maximal correlation peak value, corresponding data sequence, in the position that receives signal, obtains cyclic prefix type during;

B2, according to the maximal correlation peak value, corresponding data sequence is in the position and the cyclic prefix type during that receive signal, the position that draws time domain auxiliary synchronous signals sequence;

B3, the OFDM symbol of time domain auxiliary synchronous signals is carried out to 128 point quick Fourier conversion, obtain the frequency domain auxiliary synchronous signals;

B4, by 336 groups of the 0th work song frame and the 5th work song frame local auxiliary synchronous signals sequences respectively with the cumulative computing of first multiplying each other again of frequency domain auxiliary synchronous signals, obtain 336 groups of auxiliary synchronous signals correlated results;

B5, according to 336 groups of auxiliary synchronous signals correlated results, obtain maximum auxiliary synchronous signals correlated results, and and then obtain its corresponding auxiliary synchronous signals sequence numbering and 10ms boundary information;

B6, according to master sync signal sequence numbering and auxiliary synchronous signals sequence numbering, obtain Physical Cell Identifier.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step C comprises:

The first half section point of the first half section point of C1, master sync signal sequence to received signal and the local master sync signal sequence corresponding with it carries out the conjugation related operation, the second half section point of the second half section point of master sync signal sequence to received signal and the local master sync signal sequence corresponding with it carries out the conjugation related operation, obtains first half section correlated series and second half section correlated series;

C2, first half section correlated series and second half section correlated series are carried out to the conjugate multiplication computing, and and then calculate the phase place of its result;

The phase place that C3, basis obtain, obtain the frequency offset estimation value;

C4, according to the frequency offset estimation value, adjust local voltage controlled oscillator, thereby realize that frequency departure proofreaies and correct.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step D comprises:

D1, according to the 10ms boundary information, obtain its frame head position;

D2, according to frame head position and the predefined uplink-downlink configuration information of system, the up-downgoing switching point is arranged, obtain time-division switching.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step D2 is arranged the up-downgoing switching point, and it is specially:

The Cyclic Prefix of the penultimate OFDM symbol of special subframe is set to the descending up switching point that turns, and the Cyclic Prefix of first OFDM symbol of corresponding descending sub frame is set to the descending up switching point that turns.

The invention has the beneficial effects as follows:

A kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention is applicable to FPGA hardware and realizes, can effectively realize the search processing of TD-LTE time-division switching, when time and Frequency Synchronization are obtained in digital junction and community, master sync signal, auxiliary synchronous signals and Cyclic Prefix are detected, there is higher correct detection probability, and there is lower computational complexity.

The accompanying drawing explanation

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:

Fig. 1 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention;

Fig. 2 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention steps A;

Fig. 3 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention steps A 1;

Fig. 4 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention steps A 2;

Fig. 5 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention step B;

Fig. 6 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention step C;

Fig. 7 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention step D.

Embodiment

With reference to Fig. 1, Fig. 1 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention, and a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention comprises the following steps:

A, according to slip dependency basis present principles, carry out to received signal the master sync signal detection, obtain master sync signal sequence numbering and 5ms boundary of time slot information;

B, carry out Cyclic Prefix detection and auxiliary synchronous signals to received signal and detect, obtain cyclic prefix type during, auxiliary synchronous signals sequence numbering, 10ms boundary information and Physical Cell Identifier;

C, frequency departure is estimated and proofreaied and correct;

D, according to the 10ms boundary information, arranged and obtained time-division switching.

Fig. 2 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention steps A, and as the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described steps A comprises:

A1, reception signal carry out sync correlation with three groups of local primary sequence respectively;

The sync correlation result that A2, basis obtain, obtain master sync signal sequence numbering and 5ms boundary of time slot information.

Fig. 3 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention steps A 1, and as the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described steps A 1 comprises:

Each data sequence of A11, reception signal is carried out 128 rear cumulative computings of first multiplying each other with three groups of local master sync signal sequences respectively, obtains the correlation computations result of three groups of corresponding local master sync signal sequences;

A12, according to the correlation computations result of three groups of corresponding local master sync signal sequences, obtain the maximal correlation peak value of three groups of local master sync signal sequences of three correspondences, and record data sequence that the maximal correlation peak value is corresponding in the position that receives signal.

Fig. 4 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention steps A 2, and as the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described steps A 2 comprises:

A21, calculate respectively the mean value of the correlation computations result of three groups of corresponding local master sync signal sequences, obtain the threshold value of three groups of local master sync signal sequences of three correspondences;

A22, the maximal correlation peak value of the same local master sync signal sequence of correspondence and the thresholding value of cutting off from are compared, according to comparative result, draw the master sync signal sequence numbering, and and then obtain 5ms boundary of time slot information.

In the present invention, LTE data sampling frequency is 1.92MHz, and to count be 128 points to OFDM symbol FFT, and a 10ms radio frames has 1.92M data, and the 5ms frame has 9600 data.

The data of often coming in, with regard to the parallel rear accumulating operation that first multiplies each other of 128 that carries out three groups of local sequences and receiving sequence.Because local processing clock is 122.88MHz, 64 times of data sampling rate, for meeting processing speed, will be divided into 4 groups when multiplying each other accumulating operation carries out, every group of 32 sequence phase multiply accumulatings being responsible for continuous 32 receiving sequences and this locality, last 4 groups of results added obtain the accumulation result that multiplies each other of 128.

Each 5ms frame has 9600 data, and 9600 correlation computations results are also just arranged, and the correlation computations result store is three degree of depth 9600, in the memory of bit wide 32bit.。

Because signal quality may be poor, cause the maximal correlation peak value that finally obtains not obvious, correlated results that can corresponding cumulative N 5ms frame, the N value can be determined by the on-site signal quality.According to the mean value of 9600 correlated results of current 5ms frame, as threshold value corresponding to current maximal correlation peak value.

By the correlation computations result is compared, can obtain the maximal correlation peak value of N 5ms frame, with current threshold value, make comparisons, if the maximal correlation peak value is greater than threshold value, Output rusults, otherwise think that current to obtain the maximal correlation peak value incorrect, prevent in the situation that bad other master sync signal types that is mistaken for of signal quality finally draw the master sync signal sequence numbering with this

Fig. 5 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention step B, and as the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step B comprises:

B1, according to the maximal correlation peak value, corresponding data sequence, in the position that receives signal, obtains cyclic prefix type during;

B2, according to the maximal correlation peak value, corresponding data sequence is in the position and the cyclic prefix type during that receive signal, the position that draws time domain auxiliary synchronous signals sequence;

B3, the OFDM symbol of time domain auxiliary synchronous signals is carried out to 128 point quick Fourier conversion, obtain the frequency domain auxiliary synchronous signals;

B4, by 336 groups of the 0th work song frame and the 5th work song frame local auxiliary synchronous signals sequences respectively with the cumulative computing of first multiplying each other again of frequency domain auxiliary synchronous signals, obtain 336 groups of auxiliary synchronous signals correlated results;

B5, according to 336 groups of auxiliary synchronous signals correlated results, obtain maximum auxiliary synchronous signals correlated results, and and then obtain its corresponding auxiliary synchronous signals sequence numbering and 10ms boundary information;

B6, according to master sync signal sequence numbering and auxiliary synchronous signals sequence numbering, obtain Physical Cell Identifier.

Because signal quality is unsatisfactory, signal causes erroneous judgement a little less than may be too, signal frequency deviation can make master sync signal position and next 5ms frame that in the first step, the master sync signal testing result obtains differ several cycles, this can cause Cyclic Prefix detection here and auxiliary synchronous signals to detect because of dislocation has not had correlation, thereby obtains wrong result.

Improving measures is:

Supposing that Cyclic Prefix is uncertain, may be regular circulation prefix or extended cyclic prefix, the input data of this module just have two kinds may, while being assumed to be extended cyclic prefix, time slot 1 or 11 the 6th OFDM symbol, totally 128 subcarriers; While being assumed to be the regular circulation prefix, time slot 1 or 11 the 7th OFDM symbol, totally 128 subcarriers.

If in the situation that the former obtains correlation peak, what receive the base station employing is extended cyclic prefix; If in the latter case, obtain correlation peak, what receive the base station employing is the regular circulation prefix.

When 336 groups of the 0th work song frame and the 5th work song frame local auxiliary synchronous signals sequences are first multiplied each other computing cumulative with the frequency domain auxiliary synchronous signals respectively again, can adopt serial structure, 336 groups are carried out computing by group, obtain 336 groups of auxiliary synchronous signals correlated results, then according to 336 groups of auxiliary synchronous signals correlated results, obtain maximum auxiliary synchronous signals correlated results, and and then obtain its corresponding auxiliary synchronous signals sequence numbering

finally, according to master sync signal sequence numbering and auxiliary synchronous signals sequence numbering, obtain Physical Cell Identifier,

$N_{\mathrm{ID}}^{\mathrm{cell}}=3N_{\mathrm{ID}}^{\left(1\right)}+N_{\mathrm{ID}}^{\left(2\right)}$

Fig. 6 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention step C, and as the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step C comprises:

The first half section point of the first half section point of C1, master sync signal sequence to received signal and the local master sync signal sequence corresponding with it carries out the conjugation related operation, the second half section point of the second half section point of master sync signal sequence to received signal and the local master sync signal sequence corresponding with it carries out the conjugation related operation, obtains first half section correlated series and second half section correlated series;

C2, first half section correlated series and second half section correlated series are carried out to the conjugate multiplication computing, and and then calculate the phase place of its result;

The phase place that C3, basis obtain, obtain the frequency offset estimation value;

C4, according to the frequency offset estimation value, adjust local voltage controlled oscillator, thereby realize that frequency departure proofreaies and correct.

Frequency deviation estimates that with proofreading and correct the prerequisite realized be that the conventional letter Timing Synchronization is accurate, if while having carrier wave frequency deviation Δ f this time, utilize the local master sync signal sequence generated and the master sync signal received to do cross-correlation, thereby draw the frequency deviation estimation, the specific algorithm flow process is as follows:

Suppose that the master sync signal sequence that receiving terminal receives means:

r(n)=x(n)e ^-j2πΔfn/N

Local master sync signal sequence and the x (n) produced is living, so establish local sequence, is:

s(n)=x(n)

Wherein, N means counting of sequence, gets 128 here, n=1,2,3.....N, by front N/2 of receiving sequence r (n) point and rear N/2 point put to front N/2 of local sequence s (n) respectively and rear N/2 put that to do conjugation relevant, obtain first half section correlated series and second half section correlated series and be designated as respectively ZL and ZR, in the first half section, k=0,1,2 ... N/2-1, in second half section, k=N/2, N/2+1, N/2+2 ... .N, concrete theory is derived as follows:

$\mathrm{ZL}=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}\left|r\left(k\right)s^{*}\left(k\right)\right|$

$=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}{\left|x\left(k\right)\right|}^2{e}^{j2\mathrm{\πk\Δf}/N}$

$={\left|c\right|}^2(1+e^{j2\mathrm{\π\Δf}}+\mathrm{\Λ}+e^{j2\mathrm{\π}(N/2-1)\mathrm{\Δf}})$

$={\left|c\right|}^2\frac{{1-e}^{\frac{j2\mathrm{\π}}{N}\frac{N}{2}\mathrm{\Δf}}}{{1-e}^{\frac{j2\mathrm{\π}}{N}\mathrm{\Δf}}}$

$={\left|c\right|}^2\frac{\sin \frac{2\mathrm{\π}}{N}\·\frac{N}{4}\mathrm{\Δf}}{\sin \frac{2\mathrm{\π}}{N}\·\frac{1}{2}\mathrm{\Δf}}{e}^{j\frac{2\mathrm{\π}}{N}\frac{N-2}{4}\mathrm{\Δf}}$

$={\left|c\right|}^2{e}^{j\frac{2\mathrm{\π}}{N}\frac{N-2}{4}\mathrm{\Δf}}$

Wherein, C is constant, in like manner can push away to obtain ZR:

$\mathrm{ZR}=\underset{k=N/2-1}{\overset{N}{\mathrm{\Σ}}}\left|r\left(k\right)s^{*}\left(k\right)\right|$

$={\left|c\right|}^2{e}^{j\frac{2\mathrm{\πN}-2}{N4}\mathrm{\Δf}}\·e^{j\frac{2\mathrm{\πN}}{N2}\mathrm{\Δf}}$

$=\mathrm{ZL}\·e^{\mathrm{j\π\Δf}}$

Then ZL and ZR are carried out to conjugate multiplication, obtain following result:

Z=ZL·ZR ^*=|ZL| ²·e ^jπΔf

Easily try to achieve the phase theta of above formula,

θ=∠Z=πΔf

Thereby draw the frequency deviation estimation $\mathrm{\Δ}\widehat{\mathrm{}}f=\∠Z/\mathrm{\π}.$

Realization on FPGA is the frequency deviation estimated value obtained according to computing, adjusts local voltage controlled oscillator, the difference existed with the frequency of oscillation-damped device crystal oscillator own, thus realize frequency offset correction.

Fig. 7 is the flow chart of steps of a kind of method for designing of the time-division switching for the TD-LTE digital junction of the present invention step D, and as the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step D comprises:

D1, according to the 10ms boundary information, obtain its frame head position;

D2, according to frame head position and the predefined uplink-downlink configuration information of system, the up-downgoing switching point is arranged, obtain time-division switching.

As the further improvement of described a kind of method for designing of the time-division switching for the TD-LTE digital junction, described step D2 is arranged the up-downgoing switching point, and it is specially:

The Cyclic Prefix of the penultimate OFDM symbol of special subframe is set to the descending up switching point that turns, and the Cyclic Prefix of first OFDM symbol of corresponding descending sub frame is set to the descending up switching point that turns.

Time-division switching provides a level signal, in system, arranges and requires to open when up, and time-division switching is high level receiving when up, and receiving when descending is low level.

In this step, utilize the design of the characteristics simplification time-division switching of special subframe.Each special subframe is comprised of DwPTS, GP and UpPTS3 special time slot, and DwPTS means descending pilot frequency time slot, and UpPTS means uplink pilot time slot, and GP means to protect interval.For simplified design, utilize the UpPTS engaged position in the special subframe back 1 or 2 OFDM symbols, and the UpPTS front must be the characteristics of GP, turn by descending the Cyclic Prefix that up switching point fixes on the penultimate OFDM symbol of special subframe, do like this integrality that does not affect valid data.Uply turn descending switching point and utilize the Cyclic Prefix of first OFDM symbol of corresponding descending sub frame as switching point.Using 1.92MHz as the data sampling clock rate, and the 10ms frame head of take starts counting as 0, and the data of often coming in add 1, and corresponding up-downgoing switching point is as shown in table 1.

Table 1 up-downgoing switching point

In table, U2D is the up down conversion point that turns, and D2U is the descending up transfer point that turns.

More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can do and make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and the distortion that these are equal to or replacement all are included in the application's claim limited range.

Claims (8)

1. the method for designing of the time-division switching for the TD-LTE digital junction, is characterized in that, comprises the following steps:

A, according to slip dependency basis present principles, carry out to received signal the master sync signal detection, obtain master sync signal sequence numbering and 5ms boundary of time slot information;

B, carry out Cyclic Prefix detection and auxiliary synchronous signals to received signal and detect, obtain cyclic prefix type during, auxiliary synchronous signals sequence numbering, 10ms boundary information and Physical Cell Identifier;

C, frequency departure is estimated and proofreaied and correct;

D, according to the 10ms boundary information, arranged and obtained time-division switching.

2. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 1, it is characterized in that: described steps A comprises:

A1, reception signal carry out sync correlation with three groups of local primary sequence respectively;

The sync correlation result that A2, basis obtain, obtain master sync signal sequence numbering and 5ms boundary of time slot information.

3. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 2, it is characterized in that: described steps A 1 comprises:

Each data sequence of A11, reception signal is carried out 128 rear cumulative computings of first multiplying each other with three groups of local master sync signal sequences respectively, obtains the correlation computations result of three groups of corresponding local master sync signal sequences;

A12, according to the correlation computations result of three groups of corresponding local master sync signal sequences, obtain the maximal correlation peak value of three groups of local master sync signal sequences of three correspondences, and record data sequence that the maximal correlation peak value is corresponding in the position that receives signal.

4. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 3, it is characterized in that: described steps A 2 comprises:

A21, calculate respectively the mean value of the correlation computations result of three groups of corresponding local master sync signal sequences, obtain the threshold value of three groups of local master sync signal sequences of three correspondences;

A22, maximal correlation peak value and the threshold value of the same local master sync signal sequence of correspondence are compared, according to comparative result, draw the master sync signal sequence numbering, and and then obtain 5ms boundary of time slot information.

5. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 4, it is characterized in that: described step B comprises:

B1, according to the maximal correlation peak value, corresponding data sequence, in the position that receives signal, obtains cyclic prefix type during;

B2, according to the maximal correlation peak value, corresponding data sequence is in the position and the cyclic prefix type during that receive signal, the position that draws time domain auxiliary synchronous signals sequence;

B3, the OFDM symbol of time domain auxiliary synchronous signals is carried out to 128 point quick Fourier conversion, obtain the frequency domain auxiliary synchronous signals;

B4, by 336 groups of the 0th work song frame and the 5th work song frame local auxiliary synchronous signals sequences respectively with the cumulative computing of first multiplying each other again of frequency domain auxiliary synchronous signals, obtain 336 groups of auxiliary synchronous signals correlated results;

B5, according to 336 groups of auxiliary synchronous signals correlated results, obtain maximum auxiliary synchronous signals correlated results, and and then obtain its corresponding auxiliary synchronous signals sequence numbering and 10ms boundary information;

B6, according to master sync signal sequence numbering and auxiliary synchronous signals sequence numbering, obtain Physical Cell Identifier.

6. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 4, it is characterized in that: described step C comprises:

The first half section point of the first half section point of C1, master sync signal sequence to received signal and the local master sync signal sequence corresponding with it carries out the conjugation related operation, the second half section point of the second half section point of master sync signal sequence to received signal and the local master sync signal sequence corresponding with it carries out the conjugation related operation, obtains first half section correlated series and second half section correlated series;

C2, first half section correlated series and second half section correlated series are carried out to the conjugate multiplication computing, and and then calculate the phase place of its result;

The phase place that C3, basis obtain, obtain the frequency offset estimation value;

C4, according to the frequency offset estimation value, adjust local voltage controlled oscillator, thereby realize that frequency departure proofreaies and correct.

7. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 4, it is characterized in that: described step D comprises:

D1, according to the 10ms boundary information, obtain its frame head position;

D2, according to frame head position and the predefined uplink-downlink configuration information of system, the up-downgoing switching point is arranged, obtain time-division switching.

8. a kind of method for designing of the time-division switching for the TD-LTE digital junction according to claim 7 is characterized in that:

Described step D2 is arranged the up-downgoing switching point, and it is specially:

The Cyclic Prefix of the penultimate OFDM symbol of special subframe is set to the descending up switching point that turns, and the Cyclic Prefix of first OFDM symbol of corresponding descending sub frame is set to the descending up switching point that turns.

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