CN103490453A - Double-battery charging and discharging circuit - Google Patents
Double-battery charging and discharging circuit Download PDFInfo
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- CN103490453A CN103490453A CN201210191524.4A CN201210191524A CN103490453A CN 103490453 A CN103490453 A CN 103490453A CN 201210191524 A CN201210191524 A CN 201210191524A CN 103490453 A CN103490453 A CN 103490453A
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- electronic switch
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention relates to a double-battery charging and discharging circuit. A first end of a first electronic switch and a first end of a fourth electronic switch are connected with a control pin of a CPU, a first detection pin and a second detection pin are connected with the positive electrode of a first battery and the positive electrode of a second battery, a third end of the first electronic switch is connected with a first end of a second electronic switch and a first end of a third electronic switch and connected with a second end of the second electronic switch and the positive electrode of the first battery through a first resistor, a third end of the third electronic switch is connected with a third end of the second electronic switch, a second end of the third switch is connected with a charging port and a load, a third end of the fourth electronic switch is connected with a first end of a fifth electronic switch and connected with the positive electrode of the second battery and a second end of a sixth electronic switch through a second resistor, a third end of the fifth electronic switch is connected with a first end of the sixth electronic switch and a first end of a seventh electronic switch and connected with the second end of the sixth electronic switch through a third resistor, a third end of the seventh electronic switch is connected with a third end of the sixth electronic switch, and a second end of the seventh electronic switch is connected with the second end of the third electronic switch. The double-battery charging and discharging circuit prolongs standby time for an electronic device.
Description
Technical field
The present invention relates to a kind of charge-discharge circuit of double cell.
Background technology
At present, portable type electronic product, as mobile phone, notebook computer all adopt lithium battery power supply, usually guarantee by increasing battery capacity operating time or the stand-by time that electronic equipment is long as far as possible, yet, the increase of battery capacity will make that the battery charging interval is elongated, the charged electrical rheology is large, and this will make the electronic equipment lost of life even damage electronic equipment.
Summary of the invention
In view of this, be necessary to provide a kind of in the situation that guarantee that electronic equipments safety can extend the charge-discharge circuit of double cell of electronic equipment stand-by time.
A kind of charge-discharge circuit of double cell is arranged on an electronic equipment mainboard, comprise first and second battery, the first to the 3rd resistance and the first to the 7th electronic switch, the first end of described the first electronic switch connects the control pin of the CPU on described electronic equipment mainboard, the second end ground connection of described the first electronic switch, the 3rd end of described the first electronic switch connects the first end of described second and third electronic switch and connects the second end of described the second electronic switch and the positive pole of described the first battery through described the first resistance, the positive pole of described the first battery connects the first detecting pin of described CPU, the minus earth of described the first battery, the 3rd end of described the 3rd electronic switch connects the 3rd end of described the second electronic switch, the second end of described the 3rd electronic switch connects charging inlet and the load of described electronic equipment, the first end of described quadrielectron switch connects the control pin of described CPU, the second end ground connection of described quadrielectron switch, the 3rd end of described the second electronic switch connects the first end of described the 5th electronic switch and connects the second end of anodal and described the 6th electronic switch of described the second battery through described the second resistance, the second end ground connection of described the 5th electronic switch, the 3rd end of described the 5th electronic switch connects the described the 6th and the first end of the 7th electronic switch and connect the second end of described the 6th electronic switch through described the 3rd resistance, the 3rd end of described the 7th electronic switch connects the 3rd end of described the 6th electronic switch, the second end of described the 7th electronic switch connects the second end of described the 3rd electronic switch, the positive pole of described the second battery connects the second detecting pin of described CPU, the minus earth of described the second battery, when load supplying that the described first or second battery is described electronic equipment, the control pin of described CPU is controlled the described first to the 3rd electronic switch conducting, described the first cell output voltage is given the load of described electronic equipment, the control pin of described CPU is controlled described quadrielectron switch conduction, described the 5th to the 7th electronic switch cut-off, the load that output voltage is not given described electronic equipment of described the second battery, the voltage that detects described the first battery by the first detecting pin as described CPU is during lower than a predeterminated voltage, the control pin of described CPU is controlled the described first to the 3rd electronic switch cut-off, the load that output voltage is not given described electronic equipment of described the first battery, the control pin of described CPU is controlled described quadrielectron switch cut-off, described the 5th to the 7th electronic switch conducting, described the second cell output voltage is given the load of described electronic equipment, the voltage that detects described the second battery as described CPU by the second detecting pin is lower than a predeterminated voltage and detect a charger while by described charging inlet, being connected to described electronic equipment, the control pin of described CPU is controlled the described first to the 3rd electronic switch conducting, described charger is that described the first battery is charged, the control pin of described CPU is controlled described quadrielectron switch conduction, described the 5th to the 7th electronic switch cut-off, described charger described the second battery that do not charge, when the voltage that detects described the first battery by the first detecting pin as described CPU equals saturation voltage, the control pin of described CPU is controlled the described first to the 3rd electronic switch cut-off, described charger described the first battery that do not charge, the control pin of described CPU is controlled described quadrielectron switch cut-off, described the 5th to the 7th electronic switch conducting, described charger is that described the second battery is charged.
Sequentially output voltage is to described load to control first and second battery for the control pin output high level signal of the described electronic equipment with charge-discharge circuit of double cell by described CPU or low level signal, and voltage of described first and second battery of first and second detecting pin detecting by described CPU is sequentially described first and second battery charging to control described charger.Described charge-discharge circuit of double cell has improved the stand-by time of described electronic equipment.
The accompanying drawing explanation
Fig. 1 is the circuit diagram of the better embodiment of charge-discharge circuit of double cell of the present invention.
The main element symbol description
| Charge-discharge circuit of |
100 |
| |
200 |
| |
300 |
| |
400 |
| |
500 |
| Resistance | R1-R15 |
| Diode | D1-D4 |
| Electric capacity | C1-C3 |
| Field effect transistor | Q1- |
| Battery | |
| 10、20 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Please refer to Fig. 1, charge-discharge circuit of double cell 100 of the present invention is arranged on an electronic equipment mainboard.The better embodiment of described charge-discharge circuit of double cell 100 comprises resistance R 1-R15, diode D1-D4, capacitor C 1-C3, seven electronic switches (being field effect transistor Q1-Q7 in the present embodiment) and battery 10,20.In the present embodiment, described field effect transistor Q1, Q4 and Q5 are N channel field-effect pipe, and described field effect transistor Q2, Q3, Q6 and Q7 are the P-channel field-effect transistor (PEFT) pipe.In other embodiments, described electronic switch also can be triode.
The positive pole of described battery 10 connects the detecting pin ADC1 of the CPU 200 on described electronic equipment mainboard and through resistance R 2 ground connection through described resistance R 1, the negative pole of described battery 10 connects anode the ground connection of described diode D1, the negative electrode of diode D1 connects the source electrode of the anodal and described field effect transistor Q2 of described battery 10, described capacitor C 1 is connected between the positive pole and negative pole of described battery 10, described resistance R 3 and R4 are connected in turn between the source electrode and ground of described field effect transistor Q2, the source electrode of described field effect transistor Q2 also connects the anode of described diode D2 through described resistance R 6, the negative electrode of described diode D2 connects the grid of described field effect transistor Q2 and Q3 and connects the drain electrode of described field effect transistor Q1 through described resistance R 7, described resistance R 8 is serially connected between the negative electrode of the source electrode of described field effect transistor Q3 and described diode D2, the drain electrode of field effect transistor Q2 connects the drain electrode of field effect transistor Q3, the source electrode of field effect transistor Q3 connects described electronic equipment charging inlet 300 and load 400, capacitor C 2 is connected between the source electrode and ground of described field effect transistor Q3, the source ground of field effect transistor Q1, its grid is connected to described resistance R 3 and also by described resistance R 5, is connected the control pin GPIO1 of described CPU 200 with the node between R4.
The positive pole of battery 20 is through the detecting pin ADC2 of the described CPU 200 of described resistance R 9 connection and through described resistance R 10 ground connection, the negative pole of described battery 20 connects anode the ground connection of described diode D3, the negative electrode of described diode D3 connects the source electrode of the anodal and described field effect transistor Q6 of described battery 20, described capacitor C 3 is connected between the positive pole and negative pole of described battery 20, the source electrode of described field effect transistor Q6 also connects the grid of described field effect transistor Q5 and the drain electrode of field effect transistor Q4 by described resistance R 11, the source electrode of described field effect transistor Q6 also connects the anode of described diode D4 by described resistance R 12, the negative electrode of diode D4 connects the grid of described field effect transistor Q6 and Q7 and connects the drain electrode of described field effect transistor Q5 through described resistance R 14, described resistance R 15 is connected between the negative electrode of the source electrode of described field effect transistor Q7 and diode D4, the drain electrode of described field effect transistor Q7 connects the drain electrode of described field effect transistor Q6, its source electrode connects the source electrode of described field effect transistor Q3, the source ground of field effect transistor Q4 and Q5, the grid of field effect transistor Q4 connects the control pin GPIO1 of described CPU 200 through described resistance R 13.
During use, when needs battery 10 or 20 is powered for load 400, the control pin GPIO1 of CPU 200 exports a high level signal, described field effect transistor Q1 receives described high level signal and conducting, its drain electrode output one low level signal is given the grid of described field effect transistor Q2 and Q3, described field effect transistor Q2 and Q3 conducting, described battery 10 is given described load 400 by described field effect transistor Q2 and Q3 output voltage.Now, described field effect transistor Q4 receives the high level signal of control pin GPIO1 output of described CPU 200 and conducting, its drain electrode output one low level signal gives the grid of described field effect transistor Q5 so that its cut-off, the grid of described field effect transistor Q6 and Q7 receives a high level signal by diode D4 and resistance R 12 from described battery 20 to be ended, therefore, described battery 20 not output voltage give described load 400.
When described CPU 200 detects the voltage of described battery 10 lower than a predeterminated voltage by its detecting pin ADC1, during as 1V, the control pin GPIO1 pin of described CPU 200 is exported a low level signal, described field effect transistor Q1 receives described low level signal and ends, the grid of described field effect transistor Q2 and Q3 receives a high level signal by diode D2 and resistance R 6 from described battery 10 to be ended, and described battery 10 will stop output voltage to described load 400.Now, described field effect transistor Q4 receive described CPU 200 control pin GPIO1 output low level signal and end, the grid of described field effect transistor Q5 receives a high level signal and conducting by described resistance R 11 from described battery 20, its drain electrode output one low level signal gives the grid of described field effect transistor Q6 and Q7 so that its conducting, described battery 20 by described field effect transistor Q6 and Q7 output voltage to described load 400.
The voltage that detects described battery 20 as described CPU 200 by its detecting pin ADC2 lower than a predeterminated voltage (as 1V) and detect a charger 500 by charging inlet 300, be connected to as described in during electronic equipment, the control pin GPIO1 of described CPU 200 exports a high level signal, described field effect transistor Q1 receives described high level signal and conducting, its drain electrode output one low level signal gives the grid of described field effect transistor Q2 and Q3 so that its conducting, and described charger 500 is described battery 10 chargings by described field effect transistor Q2 and Q3.Now, described field effect transistor Q4 receives the high level signal of control pin GPIO1 output of described CPU 200 and conducting, its drain electrode output one low level signal gives described field effect transistor Q5 so that its cut-off, the grid of described field effect transistor Q6 and Q7 receives a high level signal by diode D4 and resistance R 12 from described battery 20 to be ended, and described charger 500 will not charged to described battery 20.
The voltage that detects described battery 10 by its detecting pin ADC1 as described CPU 200 equals saturation voltage, during as 5V, the control pin GPIO1 of described CPU 200 exports a low level signal, described field effect transistor Q1 receives described low level signal and ends, the grid of described field effect transistor Q2 and Q3 receives a high level signal by diode D2 and resistance R 6 from described battery 10 to be ended, and described charger 500 will stop described battery 10 chargings.Now, described field effect transistor Q4 receive described CPU 200 control pin GPIO1 output low level signal and end, the grid of described field effect transistor Q5 receives a high level signal and conducting by described resistance R 11 from described battery 20, its drain electrode output one low level signal gives the grid of described field effect transistor Q6 and Q7 so that its conducting, and described charger 500 is described battery 20 chargings by described field effect transistor Q6 and Q7.
The voltage that detecting pin ADC1 and the ADC2 of the described electronic equipment with charge-discharge circuit of double cell 100 by described CPU 200 detects on described battery 10 and 20 is sequentially described battery 10 and 20 chargings to control described charger 500, and the output high level signal of the control pin GPIO1 by described CPU 200 or low level signal with control battery 10 and 20 sequentially output voltage to described load 400, thereby discharge to improve the stand-by time of described electronic equipment by the priority of double cell 10 and 20.
Claims (5)
1. a charge-discharge circuit of double cell, comprise first and second battery, the first to the 3rd resistance and the first to the 7th electronic switch, the first end of described the first electronic switch connects the control pin of the CPU on described electronic equipment mainboard, the second end ground connection of described the first electronic switch, the 3rd end of described the first electronic switch connects the first end of described second and third electronic switch and connects the second end of described the second electronic switch and the positive pole of described the first battery through described the first resistance, the positive pole of described the first battery connects the first detecting pin of described CPU, the minus earth of described the first battery, the 3rd end of described the 3rd electronic switch connects the 3rd end of described the second electronic switch, the second end of described the 3rd electronic switch connects charging inlet and the load of described electronic equipment, the first end of described quadrielectron switch connects the control pin of described CPU, the second end ground connection of described quadrielectron switch, the 3rd end of described quadrielectron switch connects the first end of described the 5th electronic switch and connects the second end of anodal and described the 6th electronic switch of described the second battery through described the second resistance, the second end ground connection of described the 5th electronic switch, the 3rd end of described the 5th electronic switch connects the described the 6th and the first end of the 7th electronic switch and connect the second end of described the 6th electronic switch through described the 3rd resistance, the 3rd end of described the 7th electronic switch connects the 3rd end of described the 6th electronic switch, the second end of described the 7th electronic switch connects the second end of described the 3rd electronic switch, the positive pole of described the second battery connects the second detecting pin of described CPU, the minus earth of described the second battery, when load supplying that the described first or second battery is described electronic equipment, the control pin of described CPU is controlled the described first to the 3rd electronic switch conducting, described the first cell output voltage is given the load of described electronic equipment, the control pin of described CPU is controlled described quadrielectron switch conduction, described the 5th to the 7th electronic switch cut-off, the load that output voltage is not given described electronic equipment of described the second battery, the voltage that detects described the first battery by the first detecting pin as described CPU is during lower than a predeterminated voltage, the control pin of described CPU is controlled the described first to the 3rd electronic switch cut-off, the load that output voltage is not given described electronic equipment of described the first battery, the control pin of described CPU is controlled described quadrielectron switch cut-off, described the 5th to the 7th electronic switch conducting, described the second cell output voltage is given the load of described electronic equipment, the voltage that detects described the second battery as described CPU by the second detecting pin is lower than a predeterminated voltage and detect a charger while by described charging inlet, being connected to described electronic equipment, the control pin of described CPU is controlled the described first to the 3rd electronic switch conducting, described charger is that described the first battery is charged, the control pin of described CPU is controlled described quadrielectron switch conduction, described the 5th to the 7th electronic switch cut-off, described charger described the second battery that do not charge, when the voltage that detects described the first battery by the first detecting pin as described CPU equals saturation voltage, the control pin of described CPU is controlled the described first to the 3rd electronic switch cut-off, described charger described the first battery that do not charge, the control pin of described CPU is controlled described quadrielectron switch cut-off, described the 5th to the 7th electronic switch conducting, described charger is that described the second battery is charged.
2. charge-discharge circuit of double cell as claimed in claim 1, it is characterized in that: described the first electronic switch, quadrielectron switch and the 5th electronic switch are N channel field-effect pipe, described the second electronic switch, the 3rd electronic switch, the 6th electronic switch and the 7th electronic switch are the P-channel field-effect transistor (PEFT) pipe, grid, source electrode and the drain electrode of corresponding described field effect transistor respectively of described first the first to the 3rd end to the 7th electronic switch.
3. charge-discharge circuit of double cell as claimed in claim 1, it is characterized in that: described charge-discharge circuit of double cell also comprises the 4th to the 15 resistance, described the 4th resistance is connected to first of described CPU and detects between the positive pole of pin and described the first battery, described the 5th resistance is connected between the first detecting pin and ground of described CPU, described the 6th resistance is connected between the first end of the positive pole of described the first battery and described the first electronic switch, described the 7th resistance is connected between the first end and ground of described the first electronic switch, described the 8th resistance is connected between the first end of the control pin of described CPU and described the first electronic switch, described the 9th resistance is connected between the first end of the 3rd end of described the first electronic switch and described second and third electronic switch, the tenth resistance is connected between the first end and the second end of described the 3rd electronic switch, described the 11 resistance is connected between the second detecting pin of the positive pole of described the second battery and described CPU, described the 12 resistance is connected between the second detecting pin and ground of described CPU, described the 13 resistance is connected between the control pin of the first end of described quadrielectron switch and described CPU, described the 14 resistance be connected to described the 5th electronic switch the 3rd end and the described the 6th and the first end of the 7th electronic switch between, described the 15 resistance is connected between the first end and the second end of described the 7th electronic switch.
4. charge-discharge circuit of double cell as claimed in claim 1, it is characterized in that: described charge-discharge circuit of double cell also comprises the first to the 3rd electric capacity, described the first electric capacity is connected between the positive pole and negative pole of described the first battery, described the second electric capacity is connected between second end and ground of described the 7th electronic switch, and described the 3rd electric capacity is connected between the positive pole and negative pole of described the second battery.
5. charge-discharge circuit of double cell as claimed in claim 1, it is characterized in that: described charge-discharge circuit of double cell also comprises first to fourth diode, the negative pole of described the first battery of the anodic bonding of described the first diode, the negative electrode of described the first diode connects the positive pole of described the first battery, described the first resistance of the anodic bonding of described the second diode, the negative electrode of described the second diode connects the first end of described second and third electronic switch, the negative pole of described the second battery of the anodic bonding of described the 3rd diode, the negative electrode of described the 3rd diode connects the positive pole of described the second battery, described the 3rd resistance of the anodic bonding of described the 4th diode, the negative electrode of described the 4th diode connects the described the 6th and the first end of the 7th electronic switch.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210191524.4A CN103490453A (en) | 2012-06-12 | 2012-06-12 | Double-battery charging and discharging circuit |
| TW101121229A TW201351842A (en) | 2012-06-12 | 2012-06-14 | Charging and discharging circuit for dual batteries |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210191524.4A CN103490453A (en) | 2012-06-12 | 2012-06-12 | Double-battery charging and discharging circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103490453A true CN103490453A (en) | 2014-01-01 |
Family
ID=49830485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210191524.4A Pending CN103490453A (en) | 2012-06-12 | 2012-06-12 | Double-battery charging and discharging circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103490453A (en) |
| TW (1) | TW201351842A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107240941A (en) * | 2017-01-22 | 2017-10-10 | 湖南电将军新能源有限公司 | A kind of subregion charging method of portable power source |
| CN107707016A (en) * | 2017-09-29 | 2018-02-16 | 深圳市亿道信息股份有限公司 | A kind of plug type Designing of Reinforced Computer based on double-battery charge discharge control system |
| CN110994769A (en) * | 2019-12-29 | 2020-04-10 | 歌尔科技有限公司 | Double-battery system and mobile terminal equipment |
-
2012
- 2012-06-12 CN CN201210191524.4A patent/CN103490453A/en active Pending
- 2012-06-14 TW TW101121229A patent/TW201351842A/en unknown
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107240941A (en) * | 2017-01-22 | 2017-10-10 | 湖南电将军新能源有限公司 | A kind of subregion charging method of portable power source |
| CN107240941B (en) * | 2017-01-22 | 2020-01-07 | 湖南电将军新能源有限公司 | Partition charging method for mobile power supply |
| CN107707016A (en) * | 2017-09-29 | 2018-02-16 | 深圳市亿道信息股份有限公司 | A kind of plug type Designing of Reinforced Computer based on double-battery charge discharge control system |
| CN107707016B (en) * | 2017-09-29 | 2023-12-15 | 深圳市亿道信息股份有限公司 | Pluggable reinforced computer based on double-battery charge-discharge control system |
| CN110994769A (en) * | 2019-12-29 | 2020-04-10 | 歌尔科技有限公司 | Double-battery system and mobile terminal equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201351842A (en) | 2013-12-16 |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140101 |