CN103489765B - The manufacture method of NMOS metal gate electrode - Google Patents
The manufacture method of NMOS metal gate electrode Download PDFInfo
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- CN103489765B CN103489765B CN201210189781.4A CN201210189781A CN103489765B CN 103489765 B CN103489765 B CN 103489765B CN 201210189781 A CN201210189781 A CN 201210189781A CN 103489765 B CN103489765 B CN 103489765B
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- replacement gate
- polysilicon replacement
- semiconductor substrate
- grid structure
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000006116 polymerization reaction Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- NRCKPUWWRHKANR-UHFFFAOYSA-N [O].[N].[Si].[Hf] Chemical compound [O].[N].[Si].[Hf] NRCKPUWWRHKANR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses the manufacture method of a kind of NMOS metal gate electrode: forming grid structure at semiconductor substrate surface, grid structure includes being positioned at the high-k gate oxide contacted below polysilicon replacement gate and the side wall layer being positioned at polysilicon replacement gate both sides with Semiconductor substrate；The Semiconductor substrate of grid structure both sides carries out n-type doping and forms source region and drain region；Interlayer dielectric layer, described interlayer dielectric layer covers semiconductor substrate surface and grid structure, described interlayer dielectric layer carries out cmp to manifesting polysilicon replacement gate；Remove predetermined portions polysilicon replacement gate, and be epitaxially formed the silicon germanide layer with compressive stress on remaining polysilicon replacement gate surface, horizontal tensile stress is transferred to the channel region between source region and drain region；Remove remaining polysilicon replacement gate and the silicon germanide layer with compressive stress being epitaxially formed, at the position formation of deposits metal gate electrode of polysilicon replacement gate。Thus accurately raceway groove being applied stress。
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly to the manufacture method of a kind of NMOS metal gate electrode。
Background technology
At present, when manufacturing semiconductor device, silicon nitride can be used to cause stress in transistor channel, thus regulating carrier mobility in raceway groove。For nmos device, it is necessary in NMOS structure, deposition has the silicon nitride layer of tensile stress (tensilestress)。
The manufacture method of NMOS metal gate electrode in prior art, in conjunction with its concrete cross-sectional view, Fig. 1 a to Fig. 1 e illustrates。
Refer to Fig. 1 a, form grid structure on Semiconductor substrate 100 surface, described grid structure includes being positioned at the high-k gate oxide 102 contacted with Semiconductor substrate below polysilicon replacement gate 101 and being positioned at the side wall layer 103 of polysilicon replacement gate 101 both sides。
Concrete, it is sequentially depositing the gate oxide and polysilicon layer with high-k on a semiconductor substrate。High-k gate oxide can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., and dielectric constant is typically greater than 15；
Then polysilicon layer is performed etching, form polysilicon replacement gate 101；
Next side wall layer 103 is formed in polysilicon replacement gate both sides, particularly as follows: chemical vapor deposition (CVD) method can be passed through deposit one layer of silicon oxide on polysilicon replacement gate surface and semiconductor substrate surface, then etching forms side wall layer 103, and thickness is about tens nanometers。
Refer to Fig. 1 b, the Semiconductor substrate 100 of grid structure both sides carries out n-type doping and forms source region and drain region 104。
Wherein, nmos device electronics is as majority carrier, so the source region of nmos device and drain region are N-type, the ion of injection is phosphorus or arsenic。
Refer to Fig. 1 c, be sequentially depositing the silicon nitride layer 105 with tensilestress and interlayer dielectric layer 106 on the surface of said structure。
Wherein, the silicon nitride layer 105 with tensilestress covers source region and drain region, is then indirectly applied in the raceway groove between source region and drain region by horizontal tensile stress。
Refer to Fig. 1 d, silicon nitride layer 105 and interlayer dielectric layer 106 are carried out cmp to manifesting polysilicon replacement gate 101。
Refer to Fig. 1 e, remove polysilicon replacement gate 101, at the position formation of deposits metal gate electrode 107 of polysilicon replacement gate。
During deposition, metal gate electrode material also can cover the surface of interlayer dielectric layer 106, then passes through CMP, the metal gate electrode material on interlayer dielectric layer 106 surface is polished, ultimately forms metal gate electrode 107。Wherein, as the material of metal gate electrode can be the combination of in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) any two kinds or three kinds。
Prior art regulates carrier mobility in NMOS raceway groove, it is tensile stress is applied on source region and drain region by having the silicon nitride layer of tensile stress (tensilestress), then indirectly transverse direction tensile stress is applied in channels, therefore the effectiveness comparison applying stress is poor, it is impossible to accurately reach the requirement of device channel counter stress。
Summary of the invention
In view of this, present invention solves the technical problem that and be: accurately raceway groove is applied stress。
For solving above-mentioned technical problem, technical scheme is specifically achieved in that
The invention discloses the manufacture method of a kind of NMOS metal gate electrode, the method includes:
Forming grid structure at semiconductor substrate surface, described grid structure includes being positioned at the high-k gate oxide contacted below polysilicon replacement gate and the side wall layer being positioned at polysilicon replacement gate both sides with Semiconductor substrate；
The Semiconductor substrate of grid structure both sides carries out n-type doping and forms source region and drain region；
Interlayer dielectric layer, described interlayer dielectric layer covers semiconductor substrate surface and grid structure, described interlayer dielectric layer carries out cmp to manifesting polysilicon replacement gate；
Remove predetermined portions polysilicon replacement gate, and be epitaxially formed the silicon germanide layer with compressive stress on remaining polysilicon replacement gate surface, horizontal tensile stress is transferred to the channel region between source region and drain region；
Remove remaining polysilicon replacement gate and the silicon germanide layer with compressive stress being epitaxially formed, at the position formation of deposits metal gate electrode of polysilicon replacement gate。
The thickness of remaining polysilicon replacement gate is not more than the 1/2 of whole polysilicon replacement gate thickness。
After being epitaxially formed the silicon germanide layer with compressive stress, the method farther includes to be annealed described silicon germanide layer processing, or ultraviolet light polymerization UVcure, or the step of microwave treatment。
As seen from the above technical solutions, the method of the present invention is when making NMOS metal gate electrode, directly compressive stress is applied to the surface of raceway groove, and expand bottom sidewall by lattice misfit, thus raceway groove being produced horizontal tensile stress, regulate carrier mobility in raceway groove, compared with prior art, regulate stress more accurate。
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e is the structural representation of the concrete manufacturing process of prior art NMOS metal gate electrode。
Fig. 2 is the schematic flow sheet of NMOS metal gate electrode manufacture method of the present invention。
Fig. 3 a to Fig. 3 e is the structural representation of the concrete manufacturing process of NMOS metal gate electrode of the present invention。
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearly understand, developing simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail。Certainly the invention is not limited in this specific embodiment, the general replacement known by one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away。
The present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail, for the ease of explanation, represent that the schematic diagram of structure can be disobeyed general ratio and be made partial enlargement, should in this, as limitation of the invention, additionally, in actual making, the three-dimensional space of length, width and the degree of depth should be comprised。
The flow chart of NMOS metal gate electrode manufacture method of the present invention is as in figure 2 it is shown, be described in detail below in conjunction with Fig. 3 a to Fig. 3 e, and it comprises the following steps:
Step 21, refer to Fig. 3 a, form grid structure on Semiconductor substrate 100 surface, described grid structure includes being positioned at the high-k gate oxide 102 contacted with Semiconductor substrate 100 below polysilicon replacement gate 101 and being positioned at the side wall layer 103 of polysilicon replacement gate both sides；
Concrete, it is sequentially depositing the gate oxide and polysilicon layer with high-k on a semiconductor substrate。High-k gate oxide can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., and dielectric constant is typically greater than 15；
Then polysilicon layer is performed etching, form polysilicon replacement gate 101；
Next side wall layer 103 is formed in polysilicon replacement gate both sides, particularly as follows: chemical vapor deposition (CVD) method can be passed through deposit one layer of silicon oxide on polysilicon replacement gate surface and semiconductor substrate surface, then etching forms side wall layer 103, and thickness is about tens nanometers。
Step 22, refer to Fig. 3 b, the Semiconductor substrate 100 of grid structure both sides carries out n-type doping and forms source region and drain region 104；
Wherein, nmos device electronics is as majority carrier, so the source region of nmos device and drain region are N-type, the ion of injection is phosphorus or arsenic。
Step 23, referring to Fig. 3 c, interlayer dielectric layer 300, described interlayer dielectric layer covers semiconductor substrate surface and grid structure, described interlayer dielectric layer carries out cmp to manifesting polysilicon replacement gate 101；
Step 24, refer to Fig. 3 d, remove predetermined portions polysilicon replacement gate, and the silicon germanide layer 301 with compressive stress (compressivestress) it is epitaxially formed on remaining polysilicon replacement gate 101 ' surface, horizontal tensile stress is transferred to the channel region between source region and drain region；
Wherein, the thickness of remaining polysilicon replacement gate is not more than the 1/2 of whole polysilicon replacement gate thickness, as long as can epitaxial growth SiGe layer 301 thereon。
In silicon germanide layer 301, the atomic radius of germanium is more than silicon, therefore can expand on volume, extrudes sidewall and bottom, and so raceway groove can be produced downward compressive stress and the tensile stress of transverse direction by nature, and wherein horizontal tensile stress is the principal element that NMOS raceway groove benefits。Remaining polysilicon replacement gate 101 ' and the silicon germanide layer 301 with compressive stress being epitaxially formed will be removed due to follow-up, so the height being epitaxially formed the silicon germanide layer 301 with compressive stress does not limit, as long as raceway groove can be applied horizontal tensile stress, highly according to device, the requirement of compressive stress can be adjusted。
Step 25, refer to Fig. 3 e, remove remaining polysilicon replacement gate 101 ' and the silicon germanide layer 301 with compressive stress being epitaxially formed, at the position formation of deposits metal gate electrode 107 of polysilicon replacement gate。
During deposition, metal gate electrode material also can cover the surface of interlayer dielectric layer 300, then passes through CMP, the metal gate electrode material on interlayer dielectric layer 300 surface is polished, ultimately forms metal gate electrode 107。Wherein, as the material of metal gate electrode can be the combination of in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) any two kinds or three kinds。
Further, in order to optimize the silicon germanide layer 301 with compressive stress being epitaxially formed, raceway groove is applied the effect of stress, it is also possible to be annealed described silicon germanide layer processing, or ultraviolet light polymerization (UVcure), or the step of microwave treatment。Usually, chemical deposition equipment is both provided with UV curing apparatus, and the ultraviolet light that the present invention sends is also not necessarily limited to chemical deposition equipment, as long as the ultraviolet wavelength range that ultraviolet light polymerization adopts reaches 200～400 nanometers。
Step 24 is the key of the present invention, wherein, the silicon germanide layer 301 with compressive stress it is epitaxially formed on remaining polysilicon replacement gate 101 ' surface, this layer has the silicon germanide layer 301 of compressive stress and is located exactly at the top of channel region, so the parts transversely tensile stress that this compressive stress is produced be transferred between source region and drain region channel region after, then the silicon germanide layer 301 that this layer has compressive stress removes。To sum up, adopt method of the invention, it is possible to directly transverse direction tensile stress is applied in channels directly over raceway groove, thus accurately raceway groove being applied stress。
The above, be only presently preferred embodiments of the present invention, is not intended to limit protection scope of the present invention。All within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention。
Claims (3)
1. a manufacture method for NMOS metal gate electrode, the method includes:
Forming grid structure at semiconductor substrate surface, described grid structure includes being positioned at the high-k gate oxide contacted below polysilicon replacement gate and the side wall layer being positioned at polysilicon replacement gate both sides with Semiconductor substrate；
The Semiconductor substrate of grid structure both sides carries out n-type doping and forms source region and drain region；
Interlayer dielectric layer, described interlayer dielectric layer covers semiconductor substrate surface and grid structure, described interlayer dielectric layer carries out cmp to manifesting polysilicon replacement gate；
Remove predetermined portions polysilicon replacement gate, and be epitaxially formed the silicon germanide layer with compressive stress on remaining polysilicon replacement gate surface, horizontal tensile stress is transferred to the channel region between source region and drain region；
Remove remaining polysilicon replacement gate and the silicon germanide layer with compressive stress being epitaxially formed, at the position formation of deposits metal gate electrode of polysilicon replacement gate。
2. the method for claim 1, it is characterised in that the thickness of remaining polysilicon replacement gate is not more than the 1/2 of whole polysilicon replacement gate thickness。
3. the method for claim 1, it is characterised in that after being epitaxially formed the silicon germanide layer with compressive stress, the method farther includes to be annealed described silicon germanide layer processing, or ultraviolet light polymerization, or the step of microwave treatment。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210189781.4A CN103489765B (en) | 2012-06-11 | 2012-06-11 | The manufacture method of NMOS metal gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210189781.4A CN103489765B (en) | 2012-06-11 | 2012-06-11 | The manufacture method of NMOS metal gate electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103489765A CN103489765A (en) | 2014-01-01 |
| CN103489765B true CN103489765B (en) | 2016-06-22 |
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| CN201210189781.4A Active CN103489765B (en) | 2012-06-11 | 2012-06-11 | The manufacture method of NMOS metal gate electrode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7504693B2 (en) * | 2004-04-23 | 2009-03-17 | International Business Machines Corporation | Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering |
| US7902058B2 (en) * | 2004-09-29 | 2011-03-08 | Intel Corporation | Inducing strain in the channels of metal gate transistors |
| US7271045B2 (en) * | 2005-09-30 | 2007-09-18 | Intel Corporation | Etch stop and hard mask film property matching to enable improved replacement metal gate process |
| US8293631B2 (en) * | 2008-03-13 | 2012-10-23 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
| DE102009031110B4 (en) * | 2009-06-30 | 2013-06-20 | Globalfoundries Dresden Module One Llc & Co. Kg | Improved cover layer integrity in a gate stack by using a hard mask for spacer patterning |
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